JP2017506386A5 - - Google Patents

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Publication number
JP2017506386A5
JP2017506386A5 JP2016549723A JP2016549723A JP2017506386A5 JP 2017506386 A5 JP2017506386 A5 JP 2017506386A5 JP 2016549723 A JP2016549723 A JP 2016549723A JP 2016549723 A JP2016549723 A JP 2016549723A JP 2017506386 A5 JP2017506386 A5 JP 2017506386A5
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JP
Japan
Prior art keywords
route
expected
endpoint
substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016549723A
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English (en)
Japanese (ja)
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JP2017506386A (ja
Filing date
Publication date
Priority claimed from US14/175,429 external-priority patent/US20150227667A1/en
Priority claimed from US14/340,411 external-priority patent/US9298874B2/en
Application filed filed Critical
Publication of JP2017506386A publication Critical patent/JP2017506386A/ja
Publication of JP2017506386A5 publication Critical patent/JP2017506386A5/ja
Pending legal-status Critical Current

Links

JP2016549723A 2014-02-07 2015-02-06 時変温度ベースの２ｄおよび３ｄワイヤルーティング Pending JP2017506386A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US14/175,429 2014-02-07
US14/175,429 US20150227667A1 (en) 2014-02-07 2014-02-07 Temperature-based wire routing
US14/340,411 US9298874B2 (en) 2014-02-07 2014-07-24 Time-variant temperature-based 2-D and 3-D wire routing
US14/340,411 2014-07-24
PCT/US2015/014780 WO2015120248A1 (en) 2014-02-07 2015-02-06 Time-variant temperature-based 2-d and 3-d wire routing

Publications (2)

Publication Number Publication Date
JP2017506386A JP2017506386A (ja) 2017-03-02
JP2017506386A5 true JP2017506386A5 (enExample) 2018-03-08

Family

ID=52484603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016549723A Pending JP2017506386A (ja) 2014-02-07 2015-02-06 時変温度ベースの２ｄおよび３ｄワイヤルーティング

Country Status (5)

Country Link
US (1) US9298874B2 (enExample)
EP (1) EP3103040A1 (enExample)
JP (1) JP2017506386A (enExample)
CN (1) CN105940400A (enExample)
WO (1) WO2015120248A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9767240B2 (en) * 2015-11-19 2017-09-19 Globalfoundries Inc. Temperature-aware integrated circuit design methods and systems
US10684642B2 (en) * 2018-03-20 2020-06-16 International Business Machines Corporation Adaptive clock mesh wiring
US11165662B2 (en) * 2019-03-26 2021-11-02 International Business Machines Corporation Enabling interactive cable routing and planning optimization for customized hardware configurations
CN115239658A (zh) * 2022-07-19 2022-10-25 苏州深浅优视智能科技有限公司 基于3d视觉的自动绕线方法、系统及存储介质
CN120145986B (zh) * 2025-05-13 2025-07-18 珠海硅芯科技有限公司 2.5d堆叠芯片的布线方法、装置、存储介质及电子设备

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4227304B2 (ja) 1998-12-22 2009-02-18 富士通株式会社 概略配線方法及び装置並びに概略配線プログラムを格納した記録媒体
US6304517B1 (en) * 1999-06-18 2001-10-16 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for real time clock frequency error correction
JP3986717B2 (ja) 1999-12-01 2007-10-03 富士通株式会社 パス決定方法及び記憶媒体
US7112994B2 (en) * 2002-07-08 2006-09-26 Viciciv Technology Three dimensional integrated circuits
US7155686B2 (en) 2004-03-09 2006-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Placement and routing method to reduce Joule heating
US7526739B2 (en) * 2005-07-26 2009-04-28 R3 Logic, Inc. Methods and systems for computer aided design of 3D integrated circuits
US7725861B2 (en) 2006-05-15 2010-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method, apparatus, and system for LPC hot spot fix
JP5390168B2 (ja) 2008-11-10 2014-01-15 ルネサスエレクトロニクス株式会社 配線のレイアウト方法及びプログラム
US8669778B1 (en) * 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device

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