WO2014195806A3 - Methods and systems for insertion of spare wiring structures for improved engineering change orders - Google Patents
Methods and systems for insertion of spare wiring structures for improved engineering change orders Download PDFInfo
- Publication number
- WO2014195806A3 WO2014195806A3 PCT/IB2014/001914 IB2014001914W WO2014195806A3 WO 2014195806 A3 WO2014195806 A3 WO 2014195806A3 IB 2014001914 W IB2014001914 W IB 2014001914W WO 2014195806 A3 WO2014195806 A3 WO 2014195806A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wiring structures
- spare wiring
- spare
- structures
- integrated circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
A method for insertion of spare wiring structures into an integrated circuit comprises determining an architecture of spare wiring structures upon which to base the insertion of spare wiring structures, inserting spare wiring structures into a physical design of the integrated circuit according to the determined architecture, and outputting an engineering-change-order-ready integrated circuit layout. The determined architecture depends upon a design characteristic or design characteristic value. The spare wiring structures include a plurality of spare electrically conductive interconnect layer structures disposed on at least one of a plurality of interconnect layers, which are disposed on one or both sides of a substrate including a plurality of electronic devices. The plurality of interconnect layers include at least one horizontal interconnect layer and at least one vertical- interconnect-access (VIA) layer. The plurality of spare electrically conductive interconnect layer structures are electrically isolated from a plurality of active electrically conductive interconnect layer structures.
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361830556P | 2013-06-03 | 2013-06-03 | |
US61/830,556 | 2013-06-03 | ||
US14/270,267 US9236343B2 (en) | 2013-05-03 | 2014-05-05 | Architecture of spare wiring structures for improved engineering change orders |
US14/270,267 | 2014-05-05 | ||
US201462006758P | 2014-06-02 | 2014-06-02 | |
US62/006,758 | 2014-06-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2014195806A2 WO2014195806A2 (en) | 2014-12-11 |
WO2014195806A3 true WO2014195806A3 (en) | 2015-04-30 |
Family
ID=52008657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2014/001914 WO2014195806A2 (en) | 2013-06-03 | 2014-06-03 | Methods and systems for insertion of spare wiring structures for improved engineering change orders |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2014195806A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015015319A2 (en) * | 2013-05-03 | 2015-02-05 | Blackcomb Design Automation Inc. | Architecture of spare wiring structures for improved engineering change orders |
US20230205968A1 (en) * | 2020-06-08 | 2023-06-29 | The Regents Of The University Of California | Integrated-circuit global routing method |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4722084A (en) * | 1985-10-02 | 1988-01-26 | Itt Corporation | Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits |
US6753253B1 (en) * | 1986-06-18 | 2004-06-22 | Hitachi, Ltd. | Method of making wiring and logic corrections on a semiconductor device by use of focused ion beams |
US7337103B2 (en) * | 2004-01-15 | 2008-02-26 | International Business Machines Corporation | Method and apparatus for the automatic correction of faulty wires in a logic simulation hardware emulator / accelerator |
US20120047480A1 (en) * | 2010-08-17 | 2012-02-23 | Kabushiki Kaisha Toshiba | Design method of semiconductor integrated circuit and computer readable medium |
US8140942B2 (en) * | 2004-10-29 | 2012-03-20 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
-
2014
- 2014-06-03 WO PCT/IB2014/001914 patent/WO2014195806A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4722084A (en) * | 1985-10-02 | 1988-01-26 | Itt Corporation | Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits |
US6753253B1 (en) * | 1986-06-18 | 2004-06-22 | Hitachi, Ltd. | Method of making wiring and logic corrections on a semiconductor device by use of focused ion beams |
US7337103B2 (en) * | 2004-01-15 | 2008-02-26 | International Business Machines Corporation | Method and apparatus for the automatic correction of faulty wires in a logic simulation hardware emulator / accelerator |
US8140942B2 (en) * | 2004-10-29 | 2012-03-20 | International Business Machines Corporation | System, method and storage medium for providing fault detection and correction in a memory subsystem |
US20120047480A1 (en) * | 2010-08-17 | 2012-02-23 | Kabushiki Kaisha Toshiba | Design method of semiconductor integrated circuit and computer readable medium |
Also Published As
Publication number | Publication date |
---|---|
WO2014195806A2 (en) | 2014-12-11 |
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