CN105940400A - 基于时变温度的2-d和3-d导线布线 - Google Patents

基于时变温度的2-d和3-d导线布线 Download PDF

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Publication number
CN105940400A
CN105940400A CN201580006898.6A CN201580006898A CN105940400A CN 105940400 A CN105940400 A CN 105940400A CN 201580006898 A CN201580006898 A CN 201580006898A CN 105940400 A CN105940400 A CN 105940400A
Authority
CN
China
Prior art keywords
prospective
line
temperature
substrate
routing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201580006898.6A
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English (en)
Chinese (zh)
Inventor
C－C·刘
S·谢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/175,429 external-priority patent/US20150227667A1/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105940400A publication Critical patent/CN105940400A/zh
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/08—Thermal analysis or thermal optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CN201580006898.6A 2014-02-07 2015-02-06 基于时变温度的2-d和3-d导线布线 Pending CN105940400A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US14/175,429 2014-02-07
US14/175,429 US20150227667A1 (en) 2014-02-07 2014-02-07 Temperature-based wire routing
US14/340,411 US9298874B2 (en) 2014-02-07 2014-07-24 Time-variant temperature-based 2-D and 3-D wire routing
US14/340,411 2014-07-24
PCT/US2015/014780 WO2015120248A1 (en) 2014-02-07 2015-02-06 Time-variant temperature-based 2-d and 3-d wire routing

Publications (1)

Publication Number Publication Date
CN105940400A true CN105940400A (zh) 2016-09-14

Family

ID=52484603

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580006898.6A Pending CN105940400A (zh) 2014-02-07 2015-02-06 基于时变温度的2-d和3-d导线布线

Country Status (5)

Country Link
US (1) US9298874B2 (enExample)
EP (1) EP3103040A1 (enExample)
JP (1) JP2017506386A (enExample)
CN (1) CN105940400A (enExample)
WO (1) WO2015120248A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115239658A (zh) * 2022-07-19 2022-10-25 苏州深浅优视智能科技有限公司 基于3d视觉的自动绕线方法、系统及存储介质
CN120145986A (zh) * 2025-05-13 2025-06-13 珠海硅芯科技有限公司 2.5d堆叠芯片的布线方法、装置、存储介质及电子设备

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9767240B2 (en) * 2015-11-19 2017-09-19 Globalfoundries Inc. Temperature-aware integrated circuit design methods and systems
US10684642B2 (en) * 2018-03-20 2020-06-16 International Business Machines Corporation Adaptive clock mesh wiring
US11165662B2 (en) * 2019-03-26 2021-11-02 International Business Machines Corporation Enabling interactive cable routing and planning optimization for customized hardware configurations

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1369067A (zh) * 1999-06-18 2002-09-11 艾利森电话股份有限公司 实时时钟频率误差纠正的方法和装置
US20050034094A1 (en) * 2002-07-08 2005-02-10 Raminda Udaya Madurawe Three dimensional integrated circuits
US20100095258A1 (en) * 2008-10-11 2010-04-15 Nec Electronics Corporation Wiring layout method of integrated circuit and computer-readable medium storing a program executed by a computer to execute the same

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Publication number Priority date Publication date Assignee Title
JP4227304B2 (ja) 1998-12-22 2009-02-18 富士通株式会社 概略配線方法及び装置並びに概略配線プログラムを格納した記録媒体
JP3986717B2 (ja) 1999-12-01 2007-10-03 富士通株式会社 パス決定方法及び記憶媒体
US7155686B2 (en) 2004-03-09 2006-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Placement and routing method to reduce Joule heating
US7526739B2 (en) * 2005-07-26 2009-04-28 R3 Logic, Inc. Methods and systems for computer aided design of 3D integrated circuits
US7725861B2 (en) 2006-05-15 2010-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method, apparatus, and system for LPC hot spot fix
US8669778B1 (en) * 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1369067A (zh) * 1999-06-18 2002-09-11 艾利森电话股份有限公司 实时时钟频率误差纠正的方法和装置
US20050034094A1 (en) * 2002-07-08 2005-02-10 Raminda Udaya Madurawe Three dimensional integrated circuits
US20100095258A1 (en) * 2008-10-11 2010-04-15 Nec Electronics Corporation Wiring layout method of integrated circuit and computer-readable medium storing a program executed by a computer to execute the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CHUNCHEN LIU等: "Temperature-Aware Clock Tree Synthesis Considering Spatiotemporal Hot Spot Correlations", 《2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN》 *
TIANPEI ZHANG等: "Temperature-Aware Routing in 3D ICs", 《DESIGN AUTOMATION ON，2006. ASIA AND SOUTH PACIFIC CONFERENCE ON》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115239658A (zh) * 2022-07-19 2022-10-25 苏州深浅优视智能科技有限公司 基于3d视觉的自动绕线方法、系统及存储介质
CN120145986A (zh) * 2025-05-13 2025-06-13 珠海硅芯科技有限公司 2.5d堆叠芯片的布线方法、装置、存储介质及电子设备

Also Published As

Publication number Publication date
US9298874B2 (en) 2016-03-29
WO2015120248A1 (en) 2015-08-13
JP2017506386A (ja) 2017-03-02
EP3103040A1 (en) 2016-12-14
US20150227668A1 (en) 2015-08-13

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Application publication date: 20160914