JP2017521871A5 - - Google Patents

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Publication number
JP2017521871A5
JP2017521871A5 JP2017503100A JP2017503100A JP2017521871A5 JP 2017521871 A5 JP2017521871 A5 JP 2017521871A5 JP 2017503100 A JP2017503100 A JP 2017503100A JP 2017503100 A JP2017503100 A JP 2017503100A JP 2017521871 A5 JP2017521871 A5 JP 2017521871A5
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JP
Japan
Prior art keywords
conductive path
metal line
metal
path
auxiliary conductive
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JP2017503100A
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English (en)
Japanese (ja)
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JP2017521871A (ja
JP6509323B2 (ja
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Priority claimed from US14/340,381 external-priority patent/US9496174B2/en
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Publication of JP2017521871A5 publication Critical patent/JP2017521871A5/ja
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JP2017503100A 2014-07-24 2015-07-21 金属ラインおよびビアのマトリクスの挿入によるエレクトロマイグレーション、突入電流効果、ｉｒ電圧降下、およびジッタの軽減 Active JP6509323B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/340,381 2014-07-24
US14/340,381 US9496174B2 (en) 2014-07-24 2014-07-24 Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion
PCT/US2015/041371 WO2016014559A1 (en) 2014-07-24 2015-07-21 Mitigating electromigration, in-rush current effects, ir-voltage drop, and jitter through metal line and via matrix insertion

Publications (3)

Publication Number Publication Date
JP2017521871A JP2017521871A (ja) 2017-08-03
JP2017521871A5 true JP2017521871A5 (enExample) 2018-08-16
JP6509323B2 JP6509323B2 (ja) 2019-05-08

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ID=53765584

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JP2017503100A Active JP6509323B2 (ja) 2014-07-24 2015-07-21 金属ラインおよびビアのマトリクスの挿入によるエレクトロマイグレーション、突入電流効果、ｉｒ電圧降下、およびジッタの軽減

Country Status (5)

Country Link
US (2) US9496174B2 (enExample)
EP (1) EP3172764A1 (enExample)
JP (1) JP6509323B2 (enExample)
CN (1) CN106575311B (enExample)
WO (1) WO2016014559A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9496174B2 (en) 2014-07-24 2016-11-15 Qualcomm Incorporated Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion
KR102643003B1 (ko) 2016-12-14 2024-03-05 삼성전자주식회사 파워 레일의 오믹 강하를 감소하는 회로 체인을 포함하는 집적 회로
US10651201B2 (en) * 2017-04-05 2020-05-12 Samsung Electronics Co., Ltd. Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration
KR102157355B1 (ko) 2019-04-23 2020-09-18 삼성전자 주식회사 표준 셀들을 포함하는 집적 회로, 이를 제조하기 위한 방법 및 컴퓨팅 시스템
KR102839579B1 (ko) 2019-11-04 2025-07-28 삼성전자주식회사 집적된 표준 셀 구조를 포함하는 집적 회로
JP7563038B2 (ja) * 2020-08-14 2024-10-08 株式会社ソシオネクスト 半導体装置の電源配線構造および半導体装置の電源配線レイアウト方法

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Publication number Priority date Publication date Assignee Title
JPH0727968B2 (ja) * 1988-12-20 1995-03-29 株式会社東芝 半導体集積回路装置
US5614764A (en) * 1995-01-13 1997-03-25 Intel Corporation Endcap reservoir to reduce electromigration
US5639691A (en) 1995-06-05 1997-06-17 Advanced Micro Devices, Inc. Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device
US6069068A (en) 1997-05-30 2000-05-30 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
JP3221383B2 (ja) * 1997-12-17 2001-10-22 日本電気株式会社 半導体装置の多層配線構造
JP2926568B1 (ja) * 1998-02-25 1999-07-28 九州日本電気株式会社 半導体集積回路とその配線方法
TW434821B (en) * 2000-02-03 2001-05-16 United Microelectronics Corp Allocation structure of via plug to connect different metal layers
JP2002009159A (ja) * 2000-06-26 2002-01-11 Nec Microsystems Ltd 半導体集積回路のレイアウト設計方法及びレイアウト設計装置
JP2003031662A (ja) * 2001-07-16 2003-01-31 Mitsubishi Electric Corp 半導体集積回路の配線方法、半導体集積回路、及び配線方法をコンピュータに実行させるプログラム
US6717268B2 (en) 2001-11-13 2004-04-06 Intel Corporation Electromigration-reliability improvement of dual damascene interconnects
JP2005051152A (ja) 2003-07-31 2005-02-24 Nec Electronics Corp 半導体装置およびそれを用いた信頼性評価方法
TWI220268B (en) * 2003-09-17 2004-08-11 Faraday Tech Corp Method for programming a routing layout design through one via layer
US7131096B1 (en) 2004-06-01 2006-10-31 Pulsic Limited Method of automatically routing nets according to current density rules
JP4602112B2 (ja) * 2005-02-17 2010-12-22 株式会社東芝 半導体集積回路の製造方法及び半導体集積回路
US7308669B2 (en) * 2005-05-18 2007-12-11 International Business Machines Corporation Use of redundant routes to increase the yield and reliability of a VLSI layout
JP2007214397A (ja) 2006-02-10 2007-08-23 Nec Corp 半導体集積回路
WO2008048130A1 (en) 2006-10-16 2008-04-24 Freescale Semiconductor, Inc. System and method for electromigration tolerant cell synthesis
US9379059B2 (en) 2008-03-21 2016-06-28 Mediatek Inc. Power and ground routing of integrated circuit devices with improved IR drop and chip performance
CN101567359B (zh) 2008-04-25 2011-12-07 原景科技股份有限公司 半导体装置
US8138603B2 (en) 2008-05-06 2012-03-20 International Business Machines Corporation Redundancy design with electro-migration immunity
JP2011091178A (ja) * 2009-10-22 2011-05-06 Renesas Electronics Corp 多層配線及び半導体装置
US8901738B2 (en) 2012-11-12 2014-12-02 International Business Machines Corporation Method of manufacturing an enhanced electromigration performance hetero-junction bipolar transistor
US9496174B2 (en) 2014-07-24 2016-11-15 Qualcomm Incorporated Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion

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