JP6509323B2 - 金属ラインおよびビアのマトリクスの挿入によるエレクトロマイグレーション、突入電流効果、ir電圧降下、およびジッタの軽減 - Google Patents
金属ラインおよびビアのマトリクスの挿入によるエレクトロマイグレーション、突入電流効果、ir電圧降下、およびジッタの軽減 Download PDFInfo
- Publication number
- JP6509323B2 JP6509323B2 JP2017503100A JP2017503100A JP6509323B2 JP 6509323 B2 JP6509323 B2 JP 6509323B2 JP 2017503100 A JP2017503100 A JP 2017503100A JP 2017503100 A JP2017503100 A JP 2017503100A JP 6509323 B2 JP6509323 B2 JP 6509323B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive path
- metal line
- metal
- current
- path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- Evolutionary Computation (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/340,381 | 2014-07-24 | ||
| US14/340,381 US9496174B2 (en) | 2014-07-24 | 2014-07-24 | Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion |
| PCT/US2015/041371 WO2016014559A1 (en) | 2014-07-24 | 2015-07-21 | Mitigating electromigration, in-rush current effects, ir-voltage drop, and jitter through metal line and via matrix insertion |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017521871A JP2017521871A (ja) | 2017-08-03 |
| JP2017521871A5 JP2017521871A5 (enExample) | 2018-08-16 |
| JP6509323B2 true JP6509323B2 (ja) | 2019-05-08 |
Family
ID=53765584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017503100A Active JP6509323B2 (ja) | 2014-07-24 | 2015-07-21 | 金属ラインおよびビアのマトリクスの挿入によるエレクトロマイグレーション、突入電流効果、ir電圧降下、およびジッタの軽減 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US9496174B2 (enExample) |
| EP (1) | EP3172764A1 (enExample) |
| JP (1) | JP6509323B2 (enExample) |
| CN (1) | CN106575311B (enExample) |
| WO (1) | WO2016014559A1 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9496174B2 (en) | 2014-07-24 | 2016-11-15 | Qualcomm Incorporated | Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion |
| KR102643003B1 (ko) | 2016-12-14 | 2024-03-05 | 삼성전자주식회사 | 파워 레일의 오믹 강하를 감소하는 회로 체인을 포함하는 집적 회로 |
| US10651201B2 (en) * | 2017-04-05 | 2020-05-12 | Samsung Electronics Co., Ltd. | Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration |
| KR102157355B1 (ko) | 2019-04-23 | 2020-09-18 | 삼성전자 주식회사 | 표준 셀들을 포함하는 집적 회로, 이를 제조하기 위한 방법 및 컴퓨팅 시스템 |
| KR102839579B1 (ko) | 2019-11-04 | 2025-07-28 | 삼성전자주식회사 | 집적된 표준 셀 구조를 포함하는 집적 회로 |
| JP7563038B2 (ja) * | 2020-08-14 | 2024-10-08 | 株式会社ソシオネクスト | 半導体装置の電源配線構造および半導体装置の電源配線レイアウト方法 |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0727968B2 (ja) * | 1988-12-20 | 1995-03-29 | 株式会社東芝 | 半導体集積回路装置 |
| US5614764A (en) * | 1995-01-13 | 1997-03-25 | Intel Corporation | Endcap reservoir to reduce electromigration |
| US5639691A (en) | 1995-06-05 | 1997-06-17 | Advanced Micro Devices, Inc. | Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device |
| US6069068A (en) | 1997-05-30 | 2000-05-30 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
| JP3221383B2 (ja) * | 1997-12-17 | 2001-10-22 | 日本電気株式会社 | 半導体装置の多層配線構造 |
| JP2926568B1 (ja) * | 1998-02-25 | 1999-07-28 | 九州日本電気株式会社 | 半導体集積回路とその配線方法 |
| TW434821B (en) * | 2000-02-03 | 2001-05-16 | United Microelectronics Corp | Allocation structure of via plug to connect different metal layers |
| JP2002009159A (ja) * | 2000-06-26 | 2002-01-11 | Nec Microsystems Ltd | 半導体集積回路のレイアウト設計方法及びレイアウト設計装置 |
| JP2003031662A (ja) * | 2001-07-16 | 2003-01-31 | Mitsubishi Electric Corp | 半導体集積回路の配線方法、半導体集積回路、及び配線方法をコンピュータに実行させるプログラム |
| US6717268B2 (en) | 2001-11-13 | 2004-04-06 | Intel Corporation | Electromigration-reliability improvement of dual damascene interconnects |
| JP2005051152A (ja) | 2003-07-31 | 2005-02-24 | Nec Electronics Corp | 半導体装置およびそれを用いた信頼性評価方法 |
| TWI220268B (en) * | 2003-09-17 | 2004-08-11 | Faraday Tech Corp | Method for programming a routing layout design through one via layer |
| US7131096B1 (en) | 2004-06-01 | 2006-10-31 | Pulsic Limited | Method of automatically routing nets according to current density rules |
| JP4602112B2 (ja) * | 2005-02-17 | 2010-12-22 | 株式会社東芝 | 半導体集積回路の製造方法及び半導体集積回路 |
| US7308669B2 (en) * | 2005-05-18 | 2007-12-11 | International Business Machines Corporation | Use of redundant routes to increase the yield and reliability of a VLSI layout |
| JP2007214397A (ja) | 2006-02-10 | 2007-08-23 | Nec Corp | 半導体集積回路 |
| WO2008048130A1 (en) | 2006-10-16 | 2008-04-24 | Freescale Semiconductor, Inc. | System and method for electromigration tolerant cell synthesis |
| US9379059B2 (en) | 2008-03-21 | 2016-06-28 | Mediatek Inc. | Power and ground routing of integrated circuit devices with improved IR drop and chip performance |
| CN101567359B (zh) | 2008-04-25 | 2011-12-07 | 原景科技股份有限公司 | 半导体装置 |
| US8138603B2 (en) | 2008-05-06 | 2012-03-20 | International Business Machines Corporation | Redundancy design with electro-migration immunity |
| JP2011091178A (ja) * | 2009-10-22 | 2011-05-06 | Renesas Electronics Corp | 多層配線及び半導体装置 |
| US8901738B2 (en) | 2012-11-12 | 2014-12-02 | International Business Machines Corporation | Method of manufacturing an enhanced electromigration performance hetero-junction bipolar transistor |
| US9496174B2 (en) | 2014-07-24 | 2016-11-15 | Qualcomm Incorporated | Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion |
-
2014
- 2014-07-24 US US14/340,381 patent/US9496174B2/en active Active
-
2015
- 2015-07-21 EP EP15745068.5A patent/EP3172764A1/en not_active Withdrawn
- 2015-07-21 WO PCT/US2015/041371 patent/WO2016014559A1/en not_active Ceased
- 2015-07-21 JP JP2017503100A patent/JP6509323B2/ja active Active
- 2015-07-21 CN CN201580039977.7A patent/CN106575311B/zh active Active
-
2016
- 2016-11-01 US US15/340,812 patent/US10008425B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP3172764A1 (en) | 2017-05-31 |
| JP2017521871A (ja) | 2017-08-03 |
| US20160027691A1 (en) | 2016-01-28 |
| CN106575311A (zh) | 2017-04-19 |
| US20170047259A1 (en) | 2017-02-16 |
| US10008425B2 (en) | 2018-06-26 |
| US9496174B2 (en) | 2016-11-15 |
| CN106575311B (zh) | 2019-10-22 |
| WO2016014559A1 (en) | 2016-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6509323B2 (ja) | 金属ラインおよびビアのマトリクスの挿入によるエレクトロマイグレーション、突入電流効果、ir電圧降下、およびジッタの軽減 | |
| US11030383B2 (en) | Integrated device and method of forming the same | |
| JP5301262B2 (ja) | 半導体装置、及び動作モ−ド切換方法 | |
| TW201729343A (zh) | 實體設計中之電阻減緩 | |
| US8407542B2 (en) | Implementing switching factor reduction in LBIST | |
| US10579773B2 (en) | Layouting of interconnect lines in integrated circuits | |
| CN111463182A (zh) | 用于使用外部互连来路由管芯信号的方法和装置 | |
| US7661084B2 (en) | Implementing memory read data eye stretcher | |
| US20170046464A1 (en) | Slack redistribution for additional power recovery | |
| US10296699B1 (en) | Implementing circuit designs adapted for partial reconfiguration | |
| JP4738216B2 (ja) | 半導体集積回路装置、及びその回路挿入手法 | |
| US10664641B2 (en) | Integrated device and method of forming the same | |
| US20160267214A1 (en) | Clock tree design methods for ultra-wide voltage range circuits | |
| US12381149B2 (en) | Cell optimization through source resistance improvement | |
| US20150186586A1 (en) | Integrated circuit layouts and methods to improve performance | |
| CN203895442U (zh) | 单元库与基于单元库形成的集成电路结构 | |
| US7539046B2 (en) | Integrated circuit with magnetic memory | |
| Mahdoum | Architectural synthesis of networks on chip | |
| US20150032931A1 (en) | Synchronous Bus Width Adaptation | |
| Bashirullah et al. | Low-power design methodology for an on-chip bus with adaptive bandwidth capability | |
| US9595304B1 (en) | Current-mode sense amplifier | |
| US9484073B1 (en) | Current-mode sense amplifier | |
| CN115394754A (zh) | 用于减少串扰的信号迹线配置 | |
| US20150303145A1 (en) | Back end of line (beol) local optimization to improve product performance | |
| Wu et al. | Process antenna effect elimination in ultra deep submicron |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170125 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180702 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180702 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20181026 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181105 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190128 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190304 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190402 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6509323 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |