JP6509323B2 - 金属ラインおよびビアのマトリクスの挿入によるエレクトロマイグレーション、突入電流効果、ir電圧降下、およびジッタの軽減 - Google Patents

金属ラインおよびビアのマトリクスの挿入によるエレクトロマイグレーション、突入電流効果、ir電圧降下、およびジッタの軽減 Download PDF

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JP6509323B2
JP6509323B2 JP2017503100A JP2017503100A JP6509323B2 JP 6509323 B2 JP6509323 B2 JP 6509323B2 JP 2017503100 A JP2017503100 A JP 2017503100A JP 2017503100 A JP2017503100 A JP 2017503100A JP 6509323 B2 JP6509323 B2 JP 6509323B2
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conductive path
metal line
metal
current
path
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JP2017521871A (ja
JP2017521871A5 (enExample
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チュン−チェン・リュウ
ジュ−イ・ル
シェンチョン・シェ
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クアルコム,インコーポレイテッド
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/394Routing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Layout of the interconnection structure
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10Integrated device layouts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2017503100A 2014-07-24 2015-07-21 金属ラインおよびビアのマトリクスの挿入によるエレクトロマイグレーション、突入電流効果、ir電圧降下、およびジッタの軽減 Active JP6509323B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/340,381 2014-07-24
US14/340,381 US9496174B2 (en) 2014-07-24 2014-07-24 Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion
PCT/US2015/041371 WO2016014559A1 (en) 2014-07-24 2015-07-21 Mitigating electromigration, in-rush current effects, ir-voltage drop, and jitter through metal line and via matrix insertion

Publications (3)

Publication Number Publication Date
JP2017521871A JP2017521871A (ja) 2017-08-03
JP2017521871A5 JP2017521871A5 (enExample) 2018-08-16
JP6509323B2 true JP6509323B2 (ja) 2019-05-08

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JP2017503100A Active JP6509323B2 (ja) 2014-07-24 2015-07-21 金属ラインおよびビアのマトリクスの挿入によるエレクトロマイグレーション、突入電流効果、ir電圧降下、およびジッタの軽減

Country Status (5)

Country Link
US (2) US9496174B2 (enExample)
EP (1) EP3172764A1 (enExample)
JP (1) JP6509323B2 (enExample)
CN (1) CN106575311B (enExample)
WO (1) WO2016014559A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9496174B2 (en) 2014-07-24 2016-11-15 Qualcomm Incorporated Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion
KR102643003B1 (ko) 2016-12-14 2024-03-05 삼성전자주식회사 파워 레일의 오믹 강하를 감소하는 회로 체인을 포함하는 집적 회로
US10651201B2 (en) * 2017-04-05 2020-05-12 Samsung Electronics Co., Ltd. Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration
KR102157355B1 (ko) 2019-04-23 2020-09-18 삼성전자 주식회사 표준 셀들을 포함하는 집적 회로, 이를 제조하기 위한 방법 및 컴퓨팅 시스템
KR102839579B1 (ko) 2019-11-04 2025-07-28 삼성전자주식회사 집적된 표준 셀 구조를 포함하는 집적 회로
JP7563038B2 (ja) * 2020-08-14 2024-10-08 株式会社ソシオネクスト 半導体装置の電源配線構造および半導体装置の電源配線レイアウト方法

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US5614764A (en) * 1995-01-13 1997-03-25 Intel Corporation Endcap reservoir to reduce electromigration
US5639691A (en) 1995-06-05 1997-06-17 Advanced Micro Devices, Inc. Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device
US6069068A (en) 1997-05-30 2000-05-30 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
JP3221383B2 (ja) * 1997-12-17 2001-10-22 日本電気株式会社 半導体装置の多層配線構造
JP2926568B1 (ja) * 1998-02-25 1999-07-28 九州日本電気株式会社 半導体集積回路とその配線方法
TW434821B (en) * 2000-02-03 2001-05-16 United Microelectronics Corp Allocation structure of via plug to connect different metal layers
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JP2003031662A (ja) * 2001-07-16 2003-01-31 Mitsubishi Electric Corp 半導体集積回路の配線方法、半導体集積回路、及び配線方法をコンピュータに実行させるプログラム
US6717268B2 (en) 2001-11-13 2004-04-06 Intel Corporation Electromigration-reliability improvement of dual damascene interconnects
JP2005051152A (ja) 2003-07-31 2005-02-24 Nec Electronics Corp 半導体装置およびそれを用いた信頼性評価方法
TWI220268B (en) * 2003-09-17 2004-08-11 Faraday Tech Corp Method for programming a routing layout design through one via layer
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US7308669B2 (en) * 2005-05-18 2007-12-11 International Business Machines Corporation Use of redundant routes to increase the yield and reliability of a VLSI layout
JP2007214397A (ja) 2006-02-10 2007-08-23 Nec Corp 半導体集積回路
WO2008048130A1 (en) 2006-10-16 2008-04-24 Freescale Semiconductor, Inc. System and method for electromigration tolerant cell synthesis
US9379059B2 (en) 2008-03-21 2016-06-28 Mediatek Inc. Power and ground routing of integrated circuit devices with improved IR drop and chip performance
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Also Published As

Publication number Publication date
EP3172764A1 (en) 2017-05-31
JP2017521871A (ja) 2017-08-03
US20160027691A1 (en) 2016-01-28
CN106575311A (zh) 2017-04-19
US20170047259A1 (en) 2017-02-16
US10008425B2 (en) 2018-06-26
US9496174B2 (en) 2016-11-15
CN106575311B (zh) 2019-10-22
WO2016014559A1 (en) 2016-01-28

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