Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
  • G06F30/394—Routing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5226—Via connections in a multilevel interconnection structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/528—Layout of the interconnection structure
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• Various features generally relate to integrated circuits (IC), and more particularly to ICs and methods of manufacturing the same that feature metal line and via matrix insertion to reduce and/or mitigate electromigration, in-rush current effects including IR-voltage drop, and jitter.
• IC integrated circuits
• Electromigration is the transport of material caused by the movement of ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms.
• a conductor such as a wire line or interconnect in an IC, is especially susceptible to electromigration when current densities through the conductor are relatively high. Electromigration decreases the reliability of ICs because it may result in voids (i.e., open circuit) and/or shorts along conductive paths within the IC, which may ultimately cause the IC to fail. As IC dimensions continue to decrease in size, electromigration increases in effect and significance.
• In-rush current is the maximum, instantaneous input current drawn by an electrical device or circuit when turned ON or otherwise activated in some way.
• clock-gating is widely used on modern ICs. Consequently however, in-rush current issues result when large currents flow into a circuit when the clock-gating is turned OFF, which may cause considerable IR-voltage drop. The resulting IR-voltage drop may cause operational status changes in transistors, such as turning ON a transistor that is supposed to be OFF.
• in-rush current issues are typical near power switches of the IC, which often makes it a location specific issue. However, chip area at such locations may be very limited due to the IC's design, and thus the amount of chip area occupied by a proposed solution to the in-rush current issue should be as small as possible.
• Jitter is the frequency deviation from the static periodicity of a periodic signal.
• the sources of jitter include power supply noise, data path noise, phase distortion on the circuit (e.g., caused by phase-lock-loops), etc. Jitter can be quite problematic for ICs related to many different applications.
• de-caps are inserted at strategic points in a circuit where one or more of the above problems are anticipated.
• de-caps have distinct drawbacks.
• de-caps have a frequency derived impedance that is selected based on the anticipated operating frequency of the circuit. Problematically, changes to the operating frequency of the circuit (e.g., when the IC enters a lower power state) may negatively affect the performance of the de-cap, which may have to be re-tuned to re- optimize performance.
• One feature provides a method of manufacturing an integrated circuit.
• the method comprises performing routing of the integrated circuit to generate a plurality of conductive paths across a plurality of metal layers, identifying a first conductive path of the plurality of conductive paths having a current and a current density, the first conductive path including at least a first metal line within a first metal layer, and after performing the steps of routing and identifying, forming an auxiliary conductive path that includes forming a first via, a second metal line, and a second via.
• the first via electrically couples to the second metal line that is in turn electrically coupled to the second via.
• the second metal line is positioned within a second metal layer that is different than the first metal layer, and the first and second vias are positioned between the first metal layer and the second metal layer.
• the first and second vias electrically couple the first metal line to the second metal line such that the auxiliary conductive path reduces the current and the current density of the first conductive path by diverting a portion of the current flowing through the first conductive path.
• a path length of the auxiliary conductive path is different than a path length of the first conductive path.
• the path length of the auxiliary conductive path is greater than the path length of the first conductive path.
• the method further comprises, after performing the steps of routing and identifying, forming a second auxiliary conductive path that includes a third metal line, a fourth metal line, and a fifth metal line, the third metal line electrically coupled to the fourth metal line that is in turn electrically coupled to the fifth metal line, the third, fourth, and fifth metal lines all positioned within the second metal layer, and the third and fifth metal lines electrically couple the fourth metal line to the second metal line such that the second auxiliary conductive path further reduces the current and the current density of the first conductive path by diverting an additional portion of the current flowing through the first conductive.
• a path length for each of the first conductive path, the auxiliary conductive path, and the second auxiliary conductive path are different from one another.
• the method further comprises, after performing the steps of routing and identifying, forming a second auxiliary conductive path that includes forming a third via, a third metal line, and a fourth via, the third via electrically coupled to the third metal line that is in turn electrically coupled to the fourth via, the third metal line positioned within a third metal layer that is different than the first and second metal layers, the third and fourth vias positioned between the second and third metal layers, and the third and fourth vias electrically couple the third metal line to the second metal line such that the second auxiliary conductive path further reduces the current and the current density of the first conductive path by diverting an additional portion of the current flowing through the first conductive.
• forming the auxiliary conductive path further includes a third and fourth metal line in the second metal layer, a first end of the second metal line electrically coupled to the first via through the third metal line, and a second end of the second metal line electrically coupled to the second via through the fourth metal line.
• an end of the second metal line includes a metal extension piece that extends beyond a juncture where the second metal line coupled to a via, the extension piece adapted to collect atoms and/or form a void due to electromigration.
• the auxiliary conductive path is formed by inserting the first and second vias and the second metal line into a layout design of the integrated circuit after placing and routing of the integrated circuit has been performed.
• Another feature provides an integrated circuit comprising a first conductive path that includes at least a first metal line within a first metal layer, and at least one auxiliary conductive path that includes a first via, a second metal line, and a second via.
• the first via is electrically coupled to the second metal line that is in turn electrically coupled to the second via, and the second metal line is positioned within a second metal layer that is different than the first metal layer.
• the first and second vias are positioned between the first metal layer and the second metal layer, and wherein the first and second vias electrically couple the first metal line to the second metal line such that the auxiliary conductive path reduces the current and the current density of the first conductive path by diverting a portion of the current flowing through the first conductive path.
• the integrated circuit further comprises a second auxiliary conductive path that includes a third metal line, a fourth metal line, and a fifth metal line, the third metal line electrically coupled to the fourth metal line that is in turn electrically coupled to the fifth metal line.
• the third, fourth, and fifth metal lines are all positioned within the second metal layer, and the third and fifth metal lines electrically couple the fourth metal line to the second metal line such that the second auxiliary conductive path further reduces the current and the current density of the first conductive path by diverting an additional portion of the current flowing through the first conductive.
• the integrated circuit further comprises a second auxiliary conductive path that includes a third via, a third metal line, and a fourth via, the third via electrically coupled to the third metal line that is in turn electrically coupled to the fourth via, the third metal line positioned within a third metal layer that is different than the first and second metal layers, the third and fourth vias positioned between the second and third metal layers, and the third and fourth vias electrically couple the third metal line to the second metal line such that the second auxiliary conductive path further reduces the current and the current density of the first conductive path by diverting an additional portion of the current flowing through the first conductive.
• Another feature provides an integrated circuit prepared by the process comprising performing routing of the integrated circuit to generate a plurality of conductive paths across a plurality of metal layers, identifying a first conductive path of the plurality of conductive paths having a current and a current density, the first conductive path including at least a first metal line within a first metal layer, and after performing the steps of routing and identifying, forming an auxiliary conductive path that includes forming a first via, a second metal line, and a second via, the first via electrically coupled to the second metal line that is in turn electrically coupled to the second via, the second metal line positioned within a second metal layer that is different than the first metal layer, the first and second vias positioned between the first metal layer and the second metal layer, and wherein the first and second vias electrically couple the first metal line to the second metal line such that the auxiliary conductive path reduces the current and the current density of the first conductive path by diverting a portion of the current flowing through the first conductive path.
• FIG. 1 illustrates a perspective view of an exemplary integrated circuit (IC) featuring metal line and via matrix insertion.
• IC integrated circuit
• FIG. 2 illustrates a schematic, cross-sectional view of the IC along the line 2-2.
• FIG. 3 illustrates a conceptual, perspective view of a first conductive path in the IC.
• FIG. 4 illustrates a conceptual, perspective view of a second conductive path within the IC featuring metal line-via matrix insertion.
• FIG. 5 illustrates a multi-stage buffer path.
• FIG. 6 illustrates the multi-stage buffer path after metal line-via matrix insertion.
• FIG. 7 illustrates the relative IR-voltage drop versus time for stages A, B, and C of the buffer path shown in FIGS. 5 and 6.
• FIG. 8 illustrates a conceptual, perspective view of a third conductive path within the IC featuring metal line-via matrix insertion.
• FIG. 9 illustrates a conceptual, perspective view of a fourth conductive path within the IC featuring metal line-via matrix insertion.
• FIG. 10 illustrates a conceptual, perspective view of a fifth conductive path within the IC featuring a metal line-via matrix insertion.
• FIG. 11 illustrates a flowchart for a method manufacturing an integrated circuit.
• objects A and C may still be considered electrically coupled to one another— even if they do not directly physically touch each other— if object B is a conductor that allows for the flow of electrical current to take place from object A to object C and/or from object C to object A.
• the metal line-via matrix consists of one or more additional metal lines and one or more additional vias that are inserted into the integrated circuit's layout at a specific point to lower the current and current density through a first conductive path that has been determined to suffer from electromigration, IR- voltage drop, and/or jitter.
• the metal line- via matrix provides one or more auxiliary conductive paths to divert and carry a portion of the current that would otherwise flow through the first conductive path. This mitigates electromigration issues and IR-voltage drop along the first conductive path. It may also help alleviate problems due to jitter along the path.
• FIG. 1 illustrates a perspective view of an exemplary integrated circuit (IC) 100 featuring metal line and via matrix insertion according to one aspect of the disclosure.
• the IC 100 may be any type of IC including, but not limited to, a processor, a processing circuit within a processor, a memory circuit, etc.
• the IC 100 may be found in any electronic device including electronic communication devices such as, but not limited, to mobile phones, computers, tablets, watches, glasses, etc.
• the IC 100 is a "flip-chip" IC.
• the methods and devices described herein equally apply to any other type of IC including a wire-bonded ICs.
• FIG. 2 illustrates a schematic, cross-sectional view of the IC 100 along the line 2-2 (see FIG. 1).
• the IC 100 includes a plurality of metal layers (e.g., M A , M B , M c , M D , etc.) having metal lines/traces 201 , 202, 203 that may be electrically coupled together through conductive vias (VA, VB, VC, etc.).
• the network of metal lines 201 , 202, 203 and vias 204, 205 may, for example, electrically couple a transistor 206 or other circuit element(s) to other portions of the IC 100 such as other devices, power networks, ground networks, etc. by providing a conductive path.
• metal lines 201 , 202, 203 and/or vias 204, 205 may be susceptible to electromigration, IR-voltage drop caused by in-rush currents, and/or jitter, and thus the methods and devices for reducing these problematic effects can be applied to such an IC 100.
• current Ij flowing through the metal lines 201 , 203 and via 205 may have a relatively high current density and cause electromigration, IR-voltage drop, and/or jitter problems.
• the IC 100 includes metal line and via insertion to reduce the current density and current Ij thereby alleviating electromigration, IR- voltage drop, and jitter.
• four (4) metal layers are depicted. However, in practice the methods and devices described herein apply to an IC having any plurality of metal and via layers.
• FIG. 3 illustrates, according to one non-limiting example, a conceptual, perspective view of a conductive path 300 in the IC 100.
• the conductive path 300 includes a first conductive path 302 that extends from point A to point B and includes the metal lines 201 , 203 and via 205.
• the first conductive path 302 carries the current Ij that flows according to the dashed, directional arrows shown in FIG. 3.
• current Ii flows: (1 ) along the first metal line 201 in a direction starting from the positive X-axis towards the negative X-axis; (2) then down the via 205 (i.e., from the positive Y-axis to the negative Y-axis); and (3) then through the second metal line 203 in a direction from the negative Z-axis to the positive Z-axis.
• the magnitude of the current I A entering point A is equal to the magnitude of the current h leaving point B. Since the first conductive path 302 shown is the only available path for the current IA to flow into and the current h to flow out of, the magnitude of the current Ii is equal to the magnitude of the currents and h.
• the first metal line 201 may be in a higher metal layer (e.g. metal layer Mc) than the second metal line 203 (e.g., in metal layer MB), and the via 205 may be in via layer VB.
• the first metal line 201 may be in any metal layer that is different than the second metal line 203, and one or more vias 205 may electrically couple the two lines 201 , 203 together.
• the direction of the currents I A, and h may be reversed.
• the conductive paths 300, 302 shown in FIG. 3 are generated after placing and routing of the IC 100 (or at least a portion of the IC 100 that includes the conductive paths 300, 302) is performed/completed. After the place and route design stage is performed it may be determined (e.g., through simulation/testing) that the first conductive path 302 is susceptible to electromigration due to high current density and in-rush current induced IR-voltage drop due to the large current flowing through it. The conductive path 302 may also, or in the alternative, be susceptible to jitter issues.
• inserting one or more additional conductive paths composed of metal lines and vias into the layout design of the IC may reduce the current density and current of the first conductive path 302, and consequently alleviate electromigration, IR- voltage drop, and/or jitter problems.
• FIG. 4 illustrates a conceptual, perspective view of a conductive path 400 within the IC 100 featuring metal line-via matrix insertion according to one non-limiting example.
• the conductive path 400 extends from point A to point B and includes the first conductive path 302 (e.g., may be referred to as "main conductive path") discussed above with respect to FIG. 3, and also includes an auxiliary conductive path 402 (e.g., may be referred to as "second conductive path”) formed by the insertion of additional metal lines 410, 412 and vias 420, 422, 424.
• the first inserted metal line 410 may be in a different (e.g., lower) metal layer than the second inserted metal line 412.
• the first inserted metal line 410 and second inserted metal line 412 may be in the same metal layer as the second metal line 203 and first metal line 201 of the first conductive path 302, respectively.
• the inserted vias 420, 422, 424 may be in the same via layer as the via 205 of the first conductive path 302.
• the metal line-via matrix that comprises the auxiliary conductive path 402 is inserted into the layout design of the IC 100 after the place and route stage of the IC 100 (or some portion of the IC 100 thereof that includes the first conductive path 302) has been performed.
• the magnitude of the current 1A in FIG. 4 entering point A is equal to the magnitude of the current h leaving point B.
• a portion of the current I A shown in FIG. 4 flows along the first conductive path 302 as current Ij and another portion of the current 1A flows along the auxiliary conductive path 402 as current along the dashed, directional arrows.
• the current I 2 flows: (1) down through a first inserted via 420 in a direction from the positive Y-axis to the negative Y- axis; (2) through a first inserted metal line 410 in a direction from the negative Z-axis to the positive Z-axis; (3) up through a second inserted via 422 in a direction from the negative Y-axis to the positive Y-axis; (4) through a second inserted metal line 412 in a direction from the positive X-axis to the negative X-axis; and (5) then back down a third inserted via 424 in a direction from the positive Y-axis to the negative Y-axis where it rejoins the first conductive path's 302 current Ij to form current IB that flows out from point B.
• the auxiliary conductive path 402 diverts a portion of the current that would otherwise ordinarily flow through the first conductive path 302.
• the current density of the first conductive path 302 e.g., current I
• the amount of current (e.g., which may be an in-rush current) flowing through the first conductive path 302 is also reduced resulting in reduced IR-voltage drop. Insertion of the metal line-via matrix may also help reduce jitter along the first conductive path 302.
• the metal line-via matrix provides additional features/properties that reduce in-rush current induced IR-voltage drops.
• the auxiliary conductive path 402 of the metal line-via matrix has a different length than the first conductive path 302 and consequently it takes a different amount of time for its current I 2 to flow from point A to point B than the current In the non-limiting example shown in FIG.
• the second conductive path 402 is longer than the first conductive path 302 and thus it takes a longer period of time for its current I2 to flow from point A to point B than the current Since the latencies of the auxiliary conductive path 402 and first conductive path 302 are different, in-rush current flowing through the general conductive path 400 (which includes paths 302, 402) is distributed across a longer time interval. This significantly reduces the impact (e.g., reduces IR-voltage drop) of a sudden influx of current.
• the optimal length of the auxiliary conductive path 402 may be decided by the resistor-capacitor delay (i.e., RC delay) associated with the conductive path 400 and the clock frequency of the circuit (e.g., clock frequency of IC 100) having the conductive path 400.
• FIGS. 5 - 7 together illustrate how the differing latencies (i.e., signal path delays) of the auxiliary conductive path 402 and the first conductive path 302 help distribute the in-rush current across a longer time interval to reduce the maximum inrush current induced IR-voltage drop.
• FIG. 5 illustrates a multi-stage buffer path 500 according to one aspect of the disclosure.
• the buffer path 500 includes a first buffer 502, a second 504, a third buffer 506, and a fourth buffer 508. Additional buffers (not shown) may follow the fourth buffer 508.
• the portion of the buffer path 500 between the first buffer 502 and the second buffer 504 may be considered the Stage A, the portion between the second buffer 504 and the third buffer 506 stage B, and the portion between the third buffer 506 and the fourth buffer 508 stage C.
• An in-rush current designated by the dashed arrow in FIG. 5, flows through the buffers path 500.
• the conductive path coupling the first buffer 502 to the second buffer 504 is the conductive path 300 of FIG. 3, which includes the first conductive path 302.
• FIG. 6 illustrates the multi-stage buffer path 500 after metal line-via matrix insertion where the conductive path coupling the first buffer 502 to the second buffer 504 is now the conductive path 400 of FIG. 4, which not only includes the first conductive path 302, but also includes the auxiliary conductive path 402.
• the auxiliary conductive path 402 has a different (e.g., longer) path delay than the first conductive path 302.
• FIG. 7 illustrates the relative IR-voltage drop versus time for stages A, B, and C of the buffer path 500 shown in FIGS. 5 and 6 according to the specific conductive path placed between the first and second buffers 502, 504 (e.g., either conductive path 300 of FIG. 3 or the conductive path 400 of FIG. 4).
• the top third of FIG. 7 shows the in-rush current induced IR-voltage drop of the buffer path 500 when the conductive path 300 of FIG. 3, which includes only the first conductive path 302, electrically couples the first and second buffers 502, 504 to each other.
• the observed maximum IR-voltage drop at the first conductive path 302 causes the voltage at stage A to drop to voltage Vi, which is relatively low. This may cause circuit malfunction if, for example, the low voltage level causes some transistors to turn ON when they should be OFF or turn OFF when they should be on, among other issues.
• the middle third of FIG. 7 shows the in-rush current induced IR-voltage drop of the buffer path 500 when the conductive path 400 of FIG. 4, which includes both the first conductive path 302 and the auxiliary conductive path 402, electrically couples the first and second buffers 502, 504 to each other.
• the observed maximum IR-voltage drop at the first conductive path 302 and the auxiliary conductive path 402 causes the voltage level at stage A of each of these paths 302, 402 to drop to about voltage V 2 (where V2 is greater than Vj) and to be time shifted with respect to each other because of their different path delays.
• V 2 where V2 is greater than Vj
• FIG. 7 shows the in-rush current induced IR- voltage drop of the buffer path 500 when again the conductive path 400 of FIG. 4 electrically couples the first and second buffers 502, 504 to each other.
• the curve shown here represents the composite maximum IR-voltage drop at stage A, which causes the voltage level of the conductive path 400 to drop to voltage V3. Since V3 is greater than Vi, inserting the metal line-via matrix reduces the maximum in-rush induced IR voltage drop of the first conductive path 302 by an amount V3 - Vj.
• the longer signal path delay associated with the auxiliary conductive path 402 causes the overall in-rush current to flow through the conductive path 400 over a greater period of time causing the IR-voltage drop to lengthen in time from to to 3 ⁇ 4 instead of from to to ti.
• the later stages (e.g., stages B and C) of the buffer path 500 exhibit very similarly shaped curves as stage A except with less pronounced (i.e., less magnitude) in-rush current induced IR-voltage drop due to the effect of the buffers 504, 506.
• a metal line-via matrix comprising one or more auxiliary conductive paths of any size and shape may be inserted after place and route of the IC 500 is performed and problematic conductive paths are identified that are prone to electromigration, IR-voltage drop, and/or jitter.
• the metal line-via matrix inserted may generally comprise a first conductive path that includes at least a first metal line within a first metal layer, and at least one auxiliary conductive path that includes: a second metal line within a second metal layer; a first via between the first metal layer and the second metal layer; and a second via between the first metal layer and the second metal layer.
• the first and second vias electrically couple the first metal line to the second metal line such that the auxiliary conductive path reduces a current and a current density of the first conductive path by sharing/diverting a portion of a current flowing through the first conductive path.
• metal line-via matrices according to different aspects that provide auxiliary conductive paths to reduce electromigration, IR-voltage drop, and/or jitter of a first conductive path.
• FIG. 8 illustrates a conceptual, perspective view of a conductive path 800 within the IC 100 featuring metal line-via matrix insertion according to another non- limiting example. Similar to the conductive path 400 shown in FIG. 4, the conductive path 800 of FIG. 8 extends from point A to point B and includes the first conductive path 302. The conductive path 800 also includes additional auxiliary current paths formed by the insertion of a metal line-via matrix that includes metal lines 410, 412, 810, 812, 814, 816 and vias 420, 422, 424. Some inserted metal lines 410, 814, 816 may be in a different (e.g., lower) metal layer than other inserted metal lines 412, 810, 812.
• Some inserted metal lines 410, 814, 816 may be in the same metal layer as the second metal line 203 of the first conductive path 302, and other inserted metal lines 412, 810, 812 may be in the same metal layer as the first metal line 201 of the first conductive path 302.
• the inserted vias 420, 422, 424 may be in the same via layer as the via 205 of the first conductive path 302.
• the metal line-via matrix shown in FIG. 8 is inserted after the place and route stage of the IC 100 (or some portion of the IC 100 thereof that includes the first conductive path 302) has been performed.
• auxiliary conductive path currents h, h, h, h, h, h, h, , an d ho generally flow in a direction from point A to point B as shown with the dashed, directional arrows.
• the inserted metal line-via matrix diverts a portion of the current that would otherwise ordinarily flow through the first conductive path 302.
• this current e.g., currents h, h, U, , h, h, h, h, and ho
• the current density and current of the first conductive path 302 is reduced, and consequently any existing electromigration, in-rush current induced IR-voltage drop, and/or jitter issues along the first conductive path 302 may also be reduced.
• FIG. 9 illustrates a conceptual, perspective view of a conductive path 900 within the IC 100 featuring metal line-via matrix insertion according to another non- limiting example.
• the conductive path 900 shown in FIG. 9 is very similar to the conductive path 400 shown in FIG. 4, except that the first metal line 201 of the first conductive path 302 and the first inserted metal line 410 of the metal line-via matrix include metal extension pieces 902, 904. That is, the first metal line 201 is extended to form the first extension piece 902, and the second inserted metal line 410 is formed to be longer so that it includes the second extension piece 904.
• the extension pieces 902, 904 extend beyond the juncture where the metal lines 201, 410 couple to the vias 205, 422.
• the extension pieces 902, 904 act as atom and/or hole (i.e., void) collection pools that buffer the effects of atom and/or hole build up from electromigration.
• the extension pieces 902, 904 are carefully formed so that they do not extend out too close to other conductive paths of the IC 100 where atom build up from electromigration may cause a short.
• the ends 906, 908 of the extension pieces 902, 904 do not electrically couple to anything (i.e., they lead nowhere), if an open circuit along the extension pieces 902, 904 forms due to electromigration induced voids, the extension pieces 902, 904 will not cause failure of the conductive path 900.
• the extension pieces 902, 904 formed at the metal lines 201, 410 shown in FIG. 9 are merely examples. Extension pieces may be formed along any metal line and/or via of a conductive path (e.g., first conductive path and/or auxiliary conductive path) of the IC 100.
• FIG. 10 illustrates a conceptual, perspective view of a conductive path 1000 within the IC 100 featuring a metal line-via matrix insertion according to another non-limiting example.
• a first conductive path 1002 that only included a first metal line 1004 is the original conductive path that was prone to electromigration, in-rush current induced IR-voltage drop, and/or jitter. Consequently, the remaining metal lines 1010 and vias 1020 shown (not all are labeled in FIG. 10 for clarity) are inserted after place and route of the IC 100 to create auxiliary conductive paths (labeled ux, not all are labeled for clarity) to reduce the current density and current through the first conductive path 1002.
• auxiliary conductive paths labeled ux, not all are labeled for clarity
• the metal line-via matrix of FIG. 8 may be considered a "2x2" matrix
• the one illustrated in FIG. 10 may be considered a "3x3" matrix since it includes inserted metal lines in three different metal layers (e.g., M A , M B , M c , etc.), and vias there between.
• Other non-limiting metal line-via matrix sizes include 4x4, 2x4, 4x2, 2x3, 3x2, 1x2, 2x1, etc.
• FIG. 1 1 illustrates a flowchart 1 100 for a method manufacturing an integrated circuit according to one aspect of the disclosure.
• routing of the integrated circuit is performed to generate a plurality of conductive paths across a plurality of metal layers 1 102.
• a first conductive path of the plurality of conductive paths is identified having a current and a current density, where the first conductive path includes at least a first metal line within a first metal layer 1 104.
• an auxiliary conductive path is formed that includes a first via electrically coupled to a second metal line that is electrically coupled to a second via.
• the second metal line is positioned within a second metal layer that is different than the first metal layer.
• the first and second vias are positioned between the first metal layer and the second metal layer. Moreover, the first and second vias electrically couple the first metal line to the second metal line such that the auxiliary conductive path reduces the current and the current density of the first conductive path by diverting a portion of the current flowing through the first conductive path 1 106.
• metal line-via matrix insertion to combat electromigration, IR-voltage drop, and jitter as described above consumes significantly less power.
• metal line-via matrices take up very little space compared to traditional de-caps.
• FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11 may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from the invention.
• the algorithms described herein may also be efficiently implemented in software and/or embedded in hardware.
• aspects of the present disclosure may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged.
• a process is terminated when its operations are completed.
• a process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
• a process corresponds to a function
• its termination corresponds to a return of the function to the calling function or the main function.
• a storage medium may represent one or more devices for storing data, including read-only memory (ROM), random access memory (RAM), magnetic disk storage mediums, optical storage mediums, flash memory devices and/or other machine-readable mediums and, processor-readable mediums, and/or computer- readable mediums for storing information.
• ROM read-only memory
• RAM random access memory
• magnetic disk storage mediums magnetic disk storage mediums
• optical storage mediums flash memory devices and/or other machine-readable mediums and, processor-readable mediums, and/or computer- readable mediums for storing information.
• the terms “machine-readable medium”, “computer-readable medium”, and/or “processor-readable medium” may include, but are not limited to non-transitory mediums such as portable or fixed storage devices, optical storage devices, and various other mediums capable of storing or containing instruction(s) and/or data.
• various methods described herein may be fully or partially implemented by instructions and/or data that may be stored in a "machine- readable medium”, “computer-readable medium”, and/or “processor-readable medium” and executed by one or more processors, machines and/or devices.
• aspects of the disclosure may be implemented by hardware, software, firmware, middleware, microcode, or any combination thereof.
• the program code or code segments to perform the necessary tasks may be stored in a machine-readable medium such as a storage medium or other storage(s).
• a processor may perform the necessary tasks.
• a code segment may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements.
• a code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.
• DSP digital signal processor
• ASIC application specific integrated circuit
• FPGA field programmable gate array
• a general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
• a processor may also be implemented as a combination of computing components, e.g., a combination of a DSP and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
• a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
• a storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

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