CN106575311B - 通过金属线和通孔矩阵插入来减轻电迁移、涌入电流效应、ir电压降和抖动 - Google Patents

通过金属线和通孔矩阵插入来减轻电迁移、涌入电流效应、ir电压降和抖动 Download PDF

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CN106575311B
CN106575311B CN201580039977.7A CN201580039977A CN106575311B CN 106575311 B CN106575311 B CN 106575311B CN 201580039977 A CN201580039977 A CN 201580039977A CN 106575311 B CN106575311 B CN 106575311B
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conductive path
metal wire
metal
hole
integrated circuit
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CN106575311A (zh
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C－C·刘
J-Y·陆
S·谢
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201580039977.7A 2014-07-24 2015-07-21 通过金属线和通孔矩阵插入来减轻电迁移、涌入电流效应、ir电压降和抖动 Active CN106575311B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/340,381 2014-07-24
US14/340,381 US9496174B2 (en) 2014-07-24 2014-07-24 Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion
PCT/US2015/041371 WO2016014559A1 (en) 2014-07-24 2015-07-21 Mitigating electromigration, in-rush current effects, ir-voltage drop, and jitter through metal line and via matrix insertion

Publications (2)

Publication Number Publication Date
CN106575311A CN106575311A (zh) 2017-04-19
CN106575311B true CN106575311B (zh) 2019-10-22

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CN201580039977.7A Active CN106575311B (zh) 2014-07-24 2015-07-21 通过金属线和通孔矩阵插入来减轻电迁移、涌入电流效应、ir电压降和抖动

Country Status (5)

Country Link
US (2) US9496174B2 (enExample)
EP (1) EP3172764A1 (enExample)
JP (1) JP6509323B2 (enExample)
CN (1) CN106575311B (enExample)
WO (1) WO2016014559A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9496174B2 (en) 2014-07-24 2016-11-15 Qualcomm Incorporated Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion
KR102643003B1 (ko) 2016-12-14 2024-03-05 삼성전자주식회사 파워 레일의 오믹 강하를 감소하는 회로 체인을 포함하는 집적 회로
US10651201B2 (en) * 2017-04-05 2020-05-12 Samsung Electronics Co., Ltd. Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration
KR102157355B1 (ko) 2019-04-23 2020-09-18 삼성전자 주식회사 표준 셀들을 포함하는 집적 회로, 이를 제조하기 위한 방법 및 컴퓨팅 시스템
KR102839579B1 (ko) 2019-11-04 2025-07-28 삼성전자주식회사 집적된 표준 셀 구조를 포함하는 집적 회로
JP7563038B2 (ja) * 2020-08-14 2024-10-08 株式会社ソシオネクスト 半導体装置の電源配線構造および半導体装置の電源配線レイアウト方法

Citations (5)

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US5614764A (en) * 1995-01-13 1997-03-25 Intel Corporation Endcap reservoir to reduce electromigration
TW434821B (en) * 2000-02-03 2001-05-16 United Microelectronics Corp Allocation structure of via plug to connect different metal layers
JP2005051152A (ja) * 2003-07-31 2005-02-24 Nec Electronics Corp 半導体装置およびそれを用いた信頼性評価方法
TW200512799A (en) * 2003-09-17 2005-04-01 Faraday Tech Corp Method for programming a routing layout design through one via layer
JP2007214397A (ja) * 2006-02-10 2007-08-23 Nec Corp 半導体集積回路

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JPH0727968B2 (ja) * 1988-12-20 1995-03-29 株式会社東芝 半導体集積回路装置
US5639691A (en) 1995-06-05 1997-06-17 Advanced Micro Devices, Inc. Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device
US6069068A (en) 1997-05-30 2000-05-30 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
JP3221383B2 (ja) * 1997-12-17 2001-10-22 日本電気株式会社 半導体装置の多層配線構造
JP2926568B1 (ja) * 1998-02-25 1999-07-28 九州日本電気株式会社 半導体集積回路とその配線方法
JP2002009159A (ja) * 2000-06-26 2002-01-11 Nec Microsystems Ltd 半導体集積回路のレイアウト設計方法及びレイアウト設計装置
JP2003031662A (ja) * 2001-07-16 2003-01-31 Mitsubishi Electric Corp 半導体集積回路の配線方法、半導体集積回路、及び配線方法をコンピュータに実行させるプログラム
US6717268B2 (en) 2001-11-13 2004-04-06 Intel Corporation Electromigration-reliability improvement of dual damascene interconnects
US7131096B1 (en) 2004-06-01 2006-10-31 Pulsic Limited Method of automatically routing nets according to current density rules
JP4602112B2 (ja) * 2005-02-17 2010-12-22 株式会社東芝 半導体集積回路の製造方法及び半導体集積回路
US7308669B2 (en) * 2005-05-18 2007-12-11 International Business Machines Corporation Use of redundant routes to increase the yield and reliability of a VLSI layout
WO2008048130A1 (en) 2006-10-16 2008-04-24 Freescale Semiconductor, Inc. System and method for electromigration tolerant cell synthesis
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CN101567359B (zh) 2008-04-25 2011-12-07 原景科技股份有限公司 半导体装置
US8138603B2 (en) 2008-05-06 2012-03-20 International Business Machines Corporation Redundancy design with electro-migration immunity
JP2011091178A (ja) * 2009-10-22 2011-05-06 Renesas Electronics Corp 多層配線及び半導体装置
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Publication number Priority date Publication date Assignee Title
US5614764A (en) * 1995-01-13 1997-03-25 Intel Corporation Endcap reservoir to reduce electromigration
TW434821B (en) * 2000-02-03 2001-05-16 United Microelectronics Corp Allocation structure of via plug to connect different metal layers
US6483045B1 (en) * 2000-02-03 2002-11-19 United Microelectronics Corp. Via plug layout structure for connecting different metallic layers
JP2005051152A (ja) * 2003-07-31 2005-02-24 Nec Electronics Corp 半導体装置およびそれを用いた信頼性評価方法
TW200512799A (en) * 2003-09-17 2005-04-01 Faraday Tech Corp Method for programming a routing layout design through one via layer
JP2007214397A (ja) * 2006-02-10 2007-08-23 Nec Corp 半導体集積回路

Also Published As

Publication number Publication date
EP3172764A1 (en) 2017-05-31
JP2017521871A (ja) 2017-08-03
US20160027691A1 (en) 2016-01-28
CN106575311A (zh) 2017-04-19
US20170047259A1 (en) 2017-02-16
US10008425B2 (en) 2018-06-26
US9496174B2 (en) 2016-11-15
WO2016014559A1 (en) 2016-01-28
JP6509323B2 (ja) 2019-05-08

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