JP2017503303A5 - - Google Patents

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Publication number
JP2017503303A5
JP2017503303A5 JP2016544821A JP2016544821A JP2017503303A5 JP 2017503303 A5 JP2017503303 A5 JP 2017503303A5 JP 2016544821 A JP2016544821 A JP 2016544821A JP 2016544821 A JP2016544821 A JP 2016544821A JP 2017503303 A5 JP2017503303 A5 JP 2017503303A5
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JP
Japan
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dram
pin
line
back channel
channel line
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Pending
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JP2016544821A
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English (en)
Japanese (ja)
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JP2017503303A (ja
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Publication date
Priority claimed from US14/591,056 external-priority patent/US9881656B2/en
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Publication of JP2017503303A publication Critical patent/JP2017503303A/ja
Publication of JP2017503303A5 publication Critical patent/JP2017503303A5/ja
Pending legal-status Critical Current

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JP2016544821A 2014-01-09 2015-01-08 ダイナミックランダムアクセスメモリ(dram)バックチャネル通信システムおよび方法 Pending JP2017503303A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461925299P 2014-01-09 2014-01-09
US61/925,299 2014-01-09
US14/591,056 2015-01-07
US14/591,056 US9881656B2 (en) 2014-01-09 2015-01-07 Dynamic random access memory (DRAM) backchannel communication systems and methods
PCT/US2015/010583 WO2015105948A1 (en) 2014-01-09 2015-01-08 Dynamic random access memory (dram) backchannel communication systems and methods

Publications (2)

Publication Number Publication Date
JP2017503303A JP2017503303A (ja) 2017-01-26
JP2017503303A5 true JP2017503303A5 (enExample) 2018-02-08

Family

ID=53495711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016544821A Pending JP2017503303A (ja) 2014-01-09 2015-01-08 ダイナミックランダムアクセスメモリ(dram)バックチャネル通信システムおよび方法

Country Status (10)

Country Link
US (2) US9881656B2 (enExample)
EP (1) EP3092568A1 (enExample)
JP (1) JP2017503303A (enExample)
KR (1) KR20160106096A (enExample)
CN (1) CN105917312B (enExample)
AR (1) AR099040A1 (enExample)
BR (1) BR112016015961A2 (enExample)
CA (1) CA2932653A1 (enExample)
TW (1) TW201543498A (enExample)
WO (1) WO2015105948A1 (enExample)

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AR099040A1 (es) 2014-01-09 2016-06-22 Qualcomm Inc Sistemas y métodos de comunicación de canal de retorno de la memoria dinámica de acceso aleatorio (dram)
US9728245B2 (en) 2015-02-28 2017-08-08 Intel Corporation Precharging and refreshing banks in memory device with bank group architecture
US10783950B2 (en) * 2015-09-02 2020-09-22 Nvidia Corporation Memory management systems and methods using a management communication bus
KR20190087893A (ko) 2018-01-17 2019-07-25 삼성전자주식회사 클럭을 공유하는 반도체 패키지 및 전자 시스템
US11036578B2 (en) 2018-04-12 2021-06-15 Samsung Electronics Co., Ltd. Semiconductor memory devices and memory systems including the same
CN110729006B (zh) * 2018-07-16 2022-07-05 超威半导体(上海)有限公司 存储器控制器中的刷新方案
US10747613B2 (en) * 2018-09-07 2020-08-18 Toshiba Memory Corporation Pooled frontline ECC decoders in memory systems
CN114556431B (zh) * 2019-10-29 2025-05-27 Oppo广东移动通信有限公司 增强现实的3d重建
US11392299B2 (en) 2019-12-20 2022-07-19 Micron Technology, Inc. Multi-purpose signaling for a memory system
US11360695B2 (en) 2020-09-16 2022-06-14 Micron Technology, Inc. Apparatus with combinational access mechanism and methods for operating the same

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CA2074307C (en) 1991-07-29 1995-12-12 Leslie J. Sell Rope guide
JPH065069A (ja) * 1992-06-18 1994-01-14 Nec Corp ダイナミック・ランダム・アクセス・メモリ
JP3376960B2 (ja) * 1999-06-01 2003-02-17 日本電気株式会社 半導体記憶装置およびそれを用いたシステム
JP4069078B2 (ja) * 2004-01-07 2008-03-26 松下電器産業株式会社 Dram制御装置およびdram制御方法
US7627804B2 (en) 2006-06-30 2009-12-01 Intel Corporation Memory device with speculative commands to memory core
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KR101308047B1 (ko) 2007-02-08 2013-09-12 삼성전자주식회사 메모리 시스템, 이 시스템을 위한 메모리, 및 이 메모리를위한 명령 디코딩 방법
US8132074B2 (en) 2007-11-19 2012-03-06 Intel Corporation Reliability, availability, and serviceability solutions for memory technology
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KR101873526B1 (ko) 2011-06-09 2018-07-02 삼성전자주식회사 에러 정정회로를 구비한 온 칩 데이터 스크러빙 장치 및 방법
KR101253199B1 (ko) * 2011-07-25 2013-04-10 엘지전자 주식회사 조명 장치
KR101962874B1 (ko) * 2012-04-24 2019-03-27 삼성전자주식회사 메모리 장치, 메모리 컨트롤러, 메모리 시스템 및 이의 동작 방법
AR099040A1 (es) 2014-01-09 2016-06-22 Qualcomm Inc Sistemas y métodos de comunicación de canal de retorno de la memoria dinámica de acceso aleatorio (dram)

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