JP2017503303A - ダイナミックランダムアクセスメモリ（ｄｒａｍ）バックチャネル通信システムおよび方法 - Google Patents

ダイナミックランダムアクセスメモリ（ｄｒａｍ）バックチャネル通信システムおよび方法 Download PDF

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Publication number
JP2017503303A
JP2017503303A JP2016544821A JP2016544821A JP2017503303A JP 2017503303 A JP2017503303 A JP 2017503303A JP 2016544821 A JP2016544821 A JP 2016544821A JP 2016544821 A JP2016544821 A JP 2016544821A JP 2017503303 A JP2017503303 A JP 2017503303A
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Prior art keywords
dram
line
memory system
drams
back channel
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JP2016544821A
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Japanese (ja)
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JP2017503303A5 (enExample
Inventor
ディヴィッド・イアン・ウェスト
マイケル・ジョセフ・ブルノリ
デクスター・タミオ・チュン
ヴァイシュナヴ・シュリニヴァス
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クアルコム，インコーポレイテッド
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Publication of JP2017503303A publication Critical patent/JP2017503303A/ja
Publication of JP2017503303A5 publication Critical patent/JP2017503303A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Transceivers (AREA)
  • Detection And Correction Of Errors (AREA)
JP2016544821A 2014-01-09 2015-01-08 ダイナミックランダムアクセスメモリ（ｄｒａｍ）バックチャネル通信システムおよび方法 Pending JP2017503303A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461925299P 2014-01-09 2014-01-09
US61/925,299 2014-01-09
US14/591,056 US9881656B2 (en) 2014-01-09 2015-01-07 Dynamic random access memory (DRAM) backchannel communication systems and methods
US14/591,056 2015-01-07
PCT/US2015/010583 WO2015105948A1 (en) 2014-01-09 2015-01-08 Dynamic random access memory (dram) backchannel communication systems and methods

Publications (2)

Publication Number Publication Date
JP2017503303A true JP2017503303A (ja) 2017-01-26
JP2017503303A5 JP2017503303A5 (enExample) 2018-02-08

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Family Applications (1)

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JP2016544821A Pending JP2017503303A (ja) 2014-01-09 2015-01-08 ダイナミックランダムアクセスメモリ（ｄｒａｍ）バックチャネル通信システムおよび方法

Country Status (10)

Country Link
US (2) US9881656B2 (enExample)
EP (1) EP3092568A1 (enExample)
JP (1) JP2017503303A (enExample)
KR (1) KR20160106096A (enExample)
CN (1) CN105917312B (enExample)
AR (1) AR099040A1 (enExample)
BR (1) BR112016015961A2 (enExample)
CA (1) CA2932653A1 (enExample)
TW (1) TW201543498A (enExample)
WO (1) WO2015105948A1 (enExample)

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AR099040A1 (es) 2014-01-09 2016-06-22 Qualcomm Inc Sistemas y métodos de comunicación de canal de retorno de la memoria dinámica de acceso aleatorio (dram)
US9728245B2 (en) 2015-02-28 2017-08-08 Intel Corporation Precharging and refreshing banks in memory device with bank group architecture
US10783950B2 (en) * 2015-09-02 2020-09-22 Nvidia Corporation Memory management systems and methods using a management communication bus
KR20190087893A (ko) 2018-01-17 2019-07-25 삼성전자주식회사 클럭을 공유하는 반도체 패키지 및 전자 시스템
US11036578B2 (en) 2018-04-12 2021-06-15 Samsung Electronics Co., Ltd. Semiconductor memory devices and memory systems including the same
CN110729006B (zh) * 2018-07-16 2022-07-05 超威半导体(上海)有限公司 存储器控制器中的刷新方案
US10747613B2 (en) * 2018-09-07 2020-08-18 Toshiba Memory Corporation Pooled frontline ECC decoders in memory systems
WO2021082771A1 (en) * 2019-10-29 2021-05-06 Guangdong Oppo Mobile Telecommunications Corp., Ltd. Augmented reality 3d reconstruction
US11392299B2 (en) 2019-12-20 2022-07-19 Micron Technology, Inc. Multi-purpose signaling for a memory system
US11360695B2 (en) 2020-09-16 2022-06-14 Micron Technology, Inc. Apparatus with combinational access mechanism and methods for operating the same

Citations (5)

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JPS57150227A (en) * 1981-03-12 1982-09-17 Nec Corp Buffer circuit
JPH065069A (ja) * 1992-06-18 1994-01-14 Nec Corp ダイナミック・ランダム・アクセス・メモリ
US20080005647A1 (en) * 2006-06-30 2008-01-03 Intel Corporation Memory device with speculative commands to memory core
US20110246713A1 (en) * 2010-04-01 2011-10-06 Bains Kuljit S Fast exit from self-refresh state of a memory device
US20130279283A1 (en) * 2012-04-24 2013-10-24 Eun-Sung Seo Memory devices and memory controllers

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CA2074307C (en) 1991-07-29 1995-12-12 Leslie J. Sell Rope guide
JP3376960B2 (ja) * 1999-06-01 2003-02-17 日本電気株式会社 半導体記憶装置およびそれを用いたシステム
JP4069078B2 (ja) * 2004-01-07 2008-03-26 松下電器産業株式会社 Ｄｒａｍ制御装置およびｄｒａｍ制御方法
US7937641B2 (en) 2006-12-21 2011-05-03 Smart Modular Technologies, Inc. Memory modules with error detection and correction
KR101308047B1 (ko) 2007-02-08 2013-09-12 삼성전자주식회사 메모리 시스템, 이 시스템을 위한 메모리, 및 이 메모리를위한 명령 디코딩 방법
US8132074B2 (en) 2007-11-19 2012-03-06 Intel Corporation Reliability, availability, and serviceability solutions for memory technology
US9158616B2 (en) 2009-12-09 2015-10-13 Intel Corporation Method and system for error management in a memory device
US9432298B1 (en) * 2011-12-09 2016-08-30 P4tents1, LLC System, method, and computer program product for improving memory systems
KR101873526B1 (ko) 2011-06-09 2018-07-02 삼성전자주식회사 에러 정정회로를 구비한 온 칩 데이터 스크러빙 장치 및 방법
KR101253199B1 (ko) * 2011-07-25 2013-04-10 엘지전자 주식회사 조명 장치
AR099040A1 (es) 2014-01-09 2016-06-22 Qualcomm Inc Sistemas y métodos de comunicación de canal de retorno de la memoria dinámica de acceso aleatorio (dram)

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57150227A (en) * 1981-03-12 1982-09-17 Nec Corp Buffer circuit
JPH065069A (ja) * 1992-06-18 1994-01-14 Nec Corp ダイナミック・ランダム・アクセス・メモリ
US20080005647A1 (en) * 2006-06-30 2008-01-03 Intel Corporation Memory device with speculative commands to memory core
US20110246713A1 (en) * 2010-04-01 2011-10-06 Bains Kuljit S Fast exit from self-refresh state of a memory device
US20130279283A1 (en) * 2012-04-24 2013-10-24 Eun-Sung Seo Memory devices and memory controllers

Also Published As

Publication number Publication date
WO2015105948A1 (en) 2015-07-16
TW201543498A (zh) 2015-11-16
US9881656B2 (en) 2018-01-30
CN105917312A (zh) 2016-08-31
US20180114553A1 (en) 2018-04-26
AR099040A1 (es) 2016-06-22
CA2932653A1 (en) 2015-07-16
KR20160106096A (ko) 2016-09-09
EP3092568A1 (en) 2016-11-16
BR112016015961A2 (pt) 2017-08-08
US10224081B2 (en) 2019-03-05
US20150194197A1 (en) 2015-07-09
CN105917312B (zh) 2019-03-08

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