JP2017227892A5 - - Google Patents

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JP2017227892A5
JP2017227892A5 JP2017116554A JP2017116554A JP2017227892A5 JP 2017227892 A5 JP2017227892 A5 JP 2017227892A5 JP 2017116554 A JP2017116554 A JP 2017116554A JP 2017116554 A JP2017116554 A JP 2017116554A JP 2017227892 A5 JP2017227892 A5 JP 2017227892A5
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characteristic
feature
lut
design layout
plasma
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JP2017116554A
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JP2017227892A (ja
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JP2017116554A 2016-06-21 2017-06-14 物理学ベースのエッチングプロファイルモデリングフレームワークを用いた高速エッジ配置誤差予測によるフォトレジスト設計レイアウトパターン近接効果補正 Pending JP2017227892A (ja)

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Application Number Priority Date Filing Date Title
US15/188,910 2016-06-21
US15/188,910 US10197908B2 (en) 2016-06-21 2016-06-21 Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework

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JP2017227892A JP2017227892A (ja) 2017-12-28
JP2017227892A5 true JP2017227892A5 (enExample) 2018-02-15

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JP2017116554A Pending JP2017227892A (ja) 2016-06-21 2017-06-14 物理学ベースのエッチングプロファイルモデリングフレームワークを用いた高速エッジ配置誤差予測によるフォトレジスト設計レイアウトパターン近接効果補正

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US (2) US10197908B2 (enExample)
JP (1) JP2017227892A (enExample)
KR (1) KR102415463B1 (enExample)
CN (2) CN107526864B (enExample)
SG (1) SG10201705049VA (enExample)
TW (1) TWI738796B (enExample)

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