JP2017187526A - 表示装置 - Google Patents
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- JP2017187526A JP2017187526A JP2016074019A JP2016074019A JP2017187526A JP 2017187526 A JP2017187526 A JP 2017187526A JP 2016074019 A JP2016074019 A JP 2016074019A JP 2016074019 A JP2016074019 A JP 2016074019A JP 2017187526 A JP2017187526 A JP 2017187526A
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- Prior art keywords
- electrode
- transistor
- insulating film
- display device
- film
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Images
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
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Abstract
【解決手段】第1の電極、第1の電極上の第1の絶縁膜、および第1の絶縁膜上の第2の電極を有する容量と、容量上の第1のトランジスタを有する表示装置が提供される。第1のトランジスタは、第2の電極、第2の電極上の第2の絶縁膜、第2の絶縁膜上の酸化物半導体膜、および酸化物半導体膜上に位置し、酸化物半導体膜と電気的に接続される第1のソース電極と第1のドレイン電極を有する。
【選択図】図4
Description
本実施形態では、本発明の実施形態の一つに係る半導体装置とそれを含む表示装置の構造に関し、図1乃至図5を用いて説明する。
本実施形態に係る表示装置100を模式的に示した斜視図を図1に示す。表示装置100は行方向と列方向に配置される複数の画素104を備えた表示領域106、ゲート側駆動回路108を基板102の一方の面(上面)に有している。表示領域106、ゲート側駆動回路108は基板102と対向基板116との間に設けられる。
図3に画素104の等価回路を示す。画素104は複数の配線とトランジスタや容量などの複数の半導体素子を有している。具体的には、第1の走査線120、第2の走査線126、第3の走査線128、映像信号線122、リセット電源線130、電流供給線124が画素104に設けられている。第1の走査線120、第2の走査線126、第3の走査線128はゲート側駆動回路108から複数の画素104にわたって行方向に伸びる。一方映像信号線122、リセット電源線130は第1の走査線120、第2の走査線126、第3の走査線128と略直交し、複数の画素104にわたって列方向に伸びる。
図4に画素104の上面模式図を示す。図4では表示素子150は図示していない。第2のトランジスタ142は半導体膜160を有しており、映像信号線122が第2のトランジスタ142のソース電極(第2のソース電極)を兼ねている。第2のトランジスタ142のドレイン電極(第2のドレイン電極)166はコンタクトホール(図中点線の丸。以下同様)を通して容量148の第2の電極172に接続され、第2の電極172は容量148の第1の電極170と対を形成している。
本実施形態では、第1実施形態で述べた表示装置100の作製方法について、図6乃至図10を用いて説明する。ここでは表示素子150として発光素子を用い、半導体膜180が酸化物半導体を、半導体膜160、162、164がポリシリコンを含有するケースを例示して説明する。図6乃至図10は図4における鎖線A−B、C−D、E−Fに沿った断面模式図である。
まず基板102上にアンダーコート192を形成する(図6(A))。基板102は第1実施形態で示した各半導体素子を支持する機能を有する。したがって基板102には、この上に形成される各半導体素子のプロセスの温度に対する耐熱性とプロセスで使用される薬品に対する化学的安定性を有する材料を使用すればよい。具体的には、基板102はガラスや石英、プラスチック、金属、セラミックなどを含むことができる。表示装置100に可撓性を付与する場合には、高分子材料を用いることができ、例えばポリイミド、ポリアミド、ポリエステル、ポリカーボナートに例示される高分子材料を使用することができる。なお、可撓性の表示装置100を形成する場合、基板102は基材、あるいはベースフィルムと呼ばれることがある。
次に、ゲート電極168、第2の電極172を覆うように第2の絶縁膜196を形成する(図6(C))。第2の絶縁膜196は単層構造、積層構造のいずれの構造を有していてもよい。
次に第1のトランジスタ140、第2のトランジスタ142を覆うように平坦化膜198を形成する(図8(A))。平坦化膜198は有機絶縁体を用いて形成することができる。有機絶縁体としてエポキシ樹脂、アクリル樹脂、ポリイミド、ポリアミド、ポリエステル、ポリカーボナート、ポリシロキサンなどの高分子材料が挙げられ、スピンコート法、インクジェット法、印刷法、ディップコーティング法などの湿式成膜法によって形成することができる。平坦化膜198は上記有機絶縁体を含む層と無機絶縁体を含む層の積層構造を有していてもよい。この場合、無機絶縁体としては酸化ケイ素や窒化ケイ素、窒化酸化ケイ素、酸化窒化ケイ素などのシリコンを含有する無機絶縁体が挙げられ、スパッタリング法やCVD法によって形成することができる。
任意の構成として、対向電極156上にパッシベーション膜(封止膜)206を形成することができる(図10)。パッシベーション膜206は先に形成した表示素子150に外部からの水分の侵入を防止することを機能の一つとしている。パッシベーション膜206としてはガスバリア性の高いものが好ましい。例えば窒化ケイ素や酸化ケイ素、窒化酸化ケイ素、酸化窒化ケイ素などの無機材料を用いてパッシベーション膜206を形成することが好ましい。あるいはアクリル樹脂やポリシロキサン、ポリイミド、ポリエステルなどを含む有機樹脂を用いてもよい。図10で例示した構造では、パッシベーション膜206は第1の層208、第2の層210、第3の層212を含む三層構造を有している。
本実施形態では、本発明の実施形態の一つに係る表示装置300に関し、図11を用いて説明する。第1、第2実施形態と重複する内容に関しては説明を割愛することがある。
本実施形態では、本発明の実施形態の一つに係る表示装置400に関し、図1、2、12、13を用いて説明する。第1乃至第3実施形態と重複する内容に関しては説明を割愛することがある。
本実施形態では、本発明の実施形態の一つに係る表示装置500に関し、図1、2、14、15を用いて説明する。第1乃至第4実施形態と重複する内容に関しては説明を割愛することがある。
本実施形態では、本発明の実施形態の一つに係る表示装置600に関し、図1乃至3、16、17を用いて説明する。第1乃至第5実施形態と重複する内容に関しては説明を割愛することがある。
Claims (13)
- 第1の電極、前記第1の電極上の第1の絶縁膜、および前記第1の絶縁膜上の第2の電極を有する容量と、
前記容量上の第1のトランジスタを有し、
前記第1のトランジスタは、
前記第2の電極、
前記第2の電極上の第2の絶縁膜、
前記第2の絶縁膜上の酸化物半導体膜、および
前記酸化物半導体膜上に位置し、前記酸化物半導体膜と電気的に接続される第1のソース電極と第1のドレイン電極を有する表示装置。 - 第1の電極、前記第1の電極上の第1の絶縁膜、および前記第1の絶縁膜上の第2の電極を有する容量と、
前記容量上の第1のトランジスタを有し、
前記第1のトランジスタは、
前記第2の電極、
前記第2の電極上の第2の絶縁膜、
前記第2の絶縁膜上の酸化物半導体膜、
前記酸化物半導体膜上の第3の絶縁膜、
前記第3の絶縁膜上の第3の電極、および
前記第3の電極上に位置し、前記酸化物半導体膜と電気的に接続される第1のソース電極と第1のドレイン電極を有する表示装置。 - 前記第3の電極は前記酸化物半導体膜と重なる、請求項2に記載の表示装置。
- 前記第2の電極と前記第3の電極は互いに電気的に接続される、請求項2に記載の表示装置。
- 前記第2の電極は前記容量と前記第1のトランジスタによって共有される、請求項1または2に記載の表示装置。
- 前記第1の電極はケイ素を含む、請求項1または2に記載の表示装置。
- 前記酸化物半導体膜は前記第2の電極と重なる、請求項1または2に記載の表示装置。
- 前記酸化物半導体膜の面積は前記第2の電極の面積よりも小さい、請求項1または2に記載の表示装置。
- 第2のトランジスタをさらに有し、
前記第2のトランジスタは、
前記第1の絶縁膜の下の半導体膜、
前記第1の絶縁膜上のゲート電極、
前記ゲート電極上の前記第2の絶縁膜、および
前記第2の絶縁膜上に位置し、前記半導体膜と電気的に接続される第2のソース電極と第2のドレイン電極を有し、
前記半導体膜はケイ素を有する、請求項1または2に記載の表示装置。 - 前記第2のソース電極と前記第2のドレイン電極の一方が前記第2の電極に電気的に接続される、請求項9に記載の表示装置。
- 前記第1のソース電極、前記第1のドレイン電極、前記第2のソース電極、前記第2のドレイン電極は互いに同一の層に存在する、請求項9に記載の表示装置。
- 前記第1のソース電極と前記第1のドレイン電極上にさらに層間膜を有し、
前記層間膜は前記第2のソース電極と前記第2の絶縁膜の間、および前記第2のドレイン電極と前記第2の絶縁膜の間に挟まれる、請求項9に記載の表示装置。 - 前記第1のソース電極と前記第1のドレイン電極の一方と電気的に接続される発光素子をさらに有する、請求項9に記載の表示装置。
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