JP2017157582A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2017157582A JP2017157582A JP2016036621A JP2016036621A JP2017157582A JP 2017157582 A JP2017157582 A JP 2017157582A JP 2016036621 A JP2016036621 A JP 2016036621A JP 2016036621 A JP2016036621 A JP 2016036621A JP 2017157582 A JP2017157582 A JP 2017157582A
- Authority
- JP
- Japan
- Prior art keywords
- bonding layer
- region
- metal foil
- semiconductor device
- atomic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
Abstract
【解決手段】実施形態の半導体装置は、半導体素子と、金属箔と、半導体素子と金属箔の間に設けられスズとアンチモンを含み菱面体結晶構造を有する第1の領域を有する接合層と、を備える。
【選択図】図1
Description
本実施形態の半導体装置は、半導体素子と、金属箔と、半導体素子と金属箔の間に設けられスズとアンチモンを含み菱面体結晶構造を有する第1の領域を有する接合層と、を備える。
20 第2の領域(Sn基マトリックス)
100 接合層
100a 第1の接合層(接合層)
100b 第2の接合層(接合層)
110 半導体素子
112 冷却器
114 放熱グリース
116 ベース板
118 第1の金属箔(金属箔)
120 絶縁板
122 第2の金属箔(金属箔)
124 ワイヤ
126 ゲル
128 ケース
130 半導体装置
200 第1の銅板
202 第3の接合層(接合層)
204 第2の銅板
206 Niメッキ部
210 第1の試料
300 配線
302 セラミックス基板
304 第4の接合層(接合層)
306 放熱板
310 第2の試料
Claims (5)
- 半導体素子と、
金属箔と、
前記半導体素子と前記金属箔の間に設けられスズとアンチモンを含み菱面体結晶構造を有する第1の領域を有する接合層と、
を備える半導体装置。 - 前記第1の領域における第1のスズの量と前記第1の領域における第1のアンチモンの量の和に対する前記第1のスズの量の割合は40原子%以上60原子%以下である請求項1記載の半導体装置。
- 前記接合層が、スズを含み正方晶結晶構造を有する第2の領域をさらに備える請求項1又は請求項2記載の半導体装置。
- 前記接合層が、コバルト又はニッケルをさらに含み、コバルトの量とニッケルの量の和の割合は0.05原子%以上0.2原子%以下である請求項3記載の半導体装置。
- 前記接合層における2θ=40度未満における前記第1の領域のX線回折ピークの強度は、2θ=40度未満におけるスズのX線回折ピークの強度より強い請求項3又は4記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016036621A JP2017157582A (ja) | 2016-02-29 | 2016-02-29 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016036621A JP2017157582A (ja) | 2016-02-29 | 2016-02-29 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2017157582A true JP2017157582A (ja) | 2017-09-07 |
Family
ID=59810730
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016036621A Pending JP2017157582A (ja) | 2016-02-29 | 2016-02-29 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2017157582A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020130039A1 (ja) * | 2018-12-18 | 2020-06-25 | 株式会社半導体熱研究所 | 半導体デバイス接合部材 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008031550A (ja) * | 2006-06-26 | 2008-02-14 | Hitachi Cable Ltd | PbフリーのSn系材料及び配線用導体並びに端末接続部並びにPbフリーはんだ合金 |
WO2009131114A1 (ja) * | 2008-04-23 | 2009-10-29 | 千住金属工業株式会社 | 鉛フリーはんだ |
WO2014163167A1 (ja) * | 2013-04-02 | 2014-10-09 | 千住金属工業株式会社 | 鉛フリーはんだ合金と車載電子回路 |
WO2014181883A1 (ja) * | 2013-05-10 | 2014-11-13 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
-
2016
- 2016-02-29 JP JP2016036621A patent/JP2017157582A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008031550A (ja) * | 2006-06-26 | 2008-02-14 | Hitachi Cable Ltd | PbフリーのSn系材料及び配線用導体並びに端末接続部並びにPbフリーはんだ合金 |
WO2009131114A1 (ja) * | 2008-04-23 | 2009-10-29 | 千住金属工業株式会社 | 鉛フリーはんだ |
WO2014163167A1 (ja) * | 2013-04-02 | 2014-10-09 | 千住金属工業株式会社 | 鉛フリーはんだ合金と車載電子回路 |
WO2014181883A1 (ja) * | 2013-05-10 | 2014-11-13 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
Non-Patent Citations (1)
Title |
---|
伊藤和生,久米道之: "1-ヒドロキシエタン-1,1-ジホスホン酸溶液から電析したスズ−アンチモン合金の構造", 表面技術, vol. 第46巻,第2号, JPN6018015706, 1995, JP, pages 104 - 108, ISSN: 0003910390 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020130039A1 (ja) * | 2018-12-18 | 2020-06-25 | 株式会社半導体熱研究所 | 半導体デバイス接合部材 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6642865B2 (ja) | はんだ接合部 | |
JP6272512B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP4904767B2 (ja) | 半導体装置 | |
JP7115591B2 (ja) | 半導体装置用はんだ材 | |
JP6983187B2 (ja) | 電力用半導体装置 | |
JP5214936B2 (ja) | 半導体装置 | |
US20240075559A1 (en) | Solder material | |
JP2018187670A (ja) | はんだ合金およびそれを用いた接合構造体 | |
JP6621068B2 (ja) | 実装構造体 | |
JP5252024B2 (ja) | 半導体装置 | |
JP5370460B2 (ja) | 半導体モジュール | |
JP2017157582A (ja) | 半導体装置 | |
JP5978589B2 (ja) | パワー半導体装置の製造方法 | |
JP2016122719A (ja) | 半導体モジュールの製造方法 | |
US11756916B2 (en) | Method for the manufacture of integrated devices including a die fixed to a leadframe | |
JP6998557B2 (ja) | はんだ合金およびそれを用いた接合構造体 | |
JP6355091B1 (ja) | はんだ合金およびそれを用いた接合構造体 | |
Dietrich | Joining and package technology for 175° C Tj increasing reliability in automotive applications | |
JP2015185679A (ja) | パワーモジュール用基板及びヒートシンク付パワーモジュール用基板 | |
JP2020098848A (ja) | 半導体素子接合部材 | |
JP2015173215A (ja) | 半導体装置及びその製造方法 | |
JP2020006403A (ja) | 接合体とそれを用いた半導体装置 | |
Takaaki et al. | Improvement of High Power Cycling Reliability having Sn-Cu Based Solder | |
JP2009004548A (ja) | 半導体装置およびこれに用いる導電性樹脂 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20170831 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20170914 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20170915 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20180424 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180508 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20181113 |