JP2017126724A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP2017126724A JP2017126724A JP2016006575A JP2016006575A JP2017126724A JP 2017126724 A JP2017126724 A JP 2017126724A JP 2016006575 A JP2016006575 A JP 2016006575A JP 2016006575 A JP2016006575 A JP 2016006575A JP 2017126724 A JP2017126724 A JP 2017126724A
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Abstract
Description
本発明の目的は、従来に比べてVCE(sat)および電力損失を低減することができる半導体装置およびその製造方法を提供することである。
前記欠陥層は、4He、3He、H、P、F、Ar、As、SbおよびSiの少なくとも一種を含んでいてもよい。この場合、前記半導体装置は、たとえば、ドリフト層を有する第1導電型の半導体基板の表面部に第2導電型のベース層を形成し、当該ベース層の表面部に第1導電型のエミッタ層を形成する工程と、前記半導体基板の裏面から、第1エネルギで第1導電型不純物を注入し、次に、前記第1エネルギとは異なる第2エネルギで第1導電型不純物を注入することによって、前記ドリフト層よりも高い不純物濃度を有し、かつ前記半導体基板の裏面からの深さ方向に関して2つのピークを持つ不純物濃度のプロファイルを有するバッファ層を形成する工程と、前記半導体基板の裏面から第2導電型不純物を注入することによって、前記バッファ層に対して前記半導体基板の裏面側にコレクタ層を形成する工程と、前記半導体基板の裏面に対して4He、3He、H、P、F、Ar、As、SbおよびSiの少なくとも一種の粒子を照射し、前記半導体基板をアニール処理することによって、前記半導体基板の裏面からの深さ方向に関して半値幅が2μm以下の不純物濃度のプロファイルを有する欠陥層を前記ドリフト層に形成する工程とを含む、半導体装置の製造方法によって製造することができる。
また、前記半導体装置の製造方法は、前記コレクタ層の形成後、前記バッファ層および前記コレクタ層内の不純物を活性化させる第1アニール処理工程を含み、前記欠陥層を形成するときのアニール処理は、前記第1アニール処理工程時よりも低温で前記半導体基板をアニール処理する第2アニール処理工程を含むことが好ましい。この場合、前記第1アニール処理工程は、第1エネルギ密度を有するレーザ照射による第1レーザアニール工程を含み、前記第2アニール処理工程は、前記第1エネルギ密度よりも低い第2エネルギ密度を有するレーザ照射による第2レーザアニール工程を含んでいてもよい。より具体的には、前記第1エネルギ密度が1J/cm2〜3J/cm2であり、前記第2エネルギ密度が0.1J/cm2〜0.5J/cm2であってもよい。
また、前記半導体装置の製造方法において、前記粒子は、イオン注入装置、サイクロトロンまたはバンデグラフによって照射されてもよい。
また、本発明の一実施形態に係る半導体装置は、次に示す特徴を備えていてもよい。
前記バッファ層の前記不純物濃度のプロファイルは、前記半導体基板の前記裏面から相対的に浅い領域に第1ピークを有し、前記第1ピークよりも相対的に深い領域に前記第1ピークよりも低い不純物濃度の第2ピークを有していてもよい。
前記半導体基板は、40μm〜200μmの厚さを有していてもよい。
前記半導体装置は、前記半導体基板の表面から前記エミッタ層および前記ベース層を貫通して前記ドリフト層に達するゲートトレンチと、前記ゲートトレンチの内面に形成されたゲート絶縁膜を介して前記ゲートトレンチに埋め込まれたゲート電極とを含んでいてもよい。つまり、トレンチゲート型のIGBTを備えていてもよい。むろん、前記半導体装置は、プレーナゲート型のIGBTを備えていてもよい。
前記ドリフト層は、前記ベース層の直下に形成され、前記ドリフト層の他領域よりも相対的に高い不純物濃度を有するエンハンス層を含んでいてもよい。
前記半導体基板は、シリコン基板を含んでいてもよい。
図1Aは、本発明の一実施形態に係る半導体装置1の模式的な外観図であり、図1Bは、半導体装置1の内部構造を示す図である。
図1Aおよび図1Bに示すように、半導体装置1は、スイッチング素子チップ2(IGBT)およびダイオードチップ3を備え、これらが樹脂パッケージ4で封止された構造を有している。半導体装置1は、さらに、両方のチップ2,3に電気的に接続された3つの端子5〜7を備えている。
ゲート端子5は、スイッチング素子チップ2のゲートパッド8に、ボンディングワイヤ9を介して接続されている。
コレクタ端子6は、スイッチング素子チップ2およびダイオードチップ3の各裏面に接合されたアイランド10を有し、スイッチング素子チップ2のコレクタ(後述するコレクタメタル42)およびダイオードチップ3のカソード(図示せず)に直接接続されている。
コレクタ端子6およびエミッタ端子7は、それぞれ、ダイオードチップ3のカソードおよびアノード用の端子を兼ねており、これにより、スイッチング素子チップ2とダイオードチップ3とが互いに並列に接続されている。
図2Aは、図1Aおよび図1Bのスイッチング素子チップ2の模式的な平面図であり、主に、スイッチング素子チップ2のパッドレイアウトを示すものである。
まず、図2Aに示すように、スイッチング素子チップ2の最表面には、たとえばアルミニウム(AlSiCu、AlCu等)からなる、ゲートメタル14およびエミッタメタル15が形成されている。ゲートメタル14およびエミッタメタル15はパッシベーション膜16で選択的に覆われている。
図2Bに示すように、スイッチング素子チップ2の内部には、ゲートパッド8およびゲートフィンガー17の直下に、たとえばポリシリコンからなるゲート埋め込み部21が形成されている。
ゲート電極25は、当該対辺に平行なストライプ状に多数形成されている(図2Bでは一部のみを図示)。各ゲート電極25の一端部が主線部23に接続され、他端部が周囲線部24に接続されている。このようなストライプ状のゲート電極25が、主線部23を挟んで両側の領域22に形成されており、隣り合うゲート電極25と、それらの端部同士を接続する主線部23および周囲線部24とで取り囲まれた部分に単位セル26が区画されている(図2Bの斜線部)。
スイッチング素子チップ2は、nチャンネル型IGBTであって、半導体基板27を含む。半導体基板27は、たとえば、40μm〜200μmの厚さ(一例として60μm)を有している。
p−型コレクタ層28、p−型ベース層32およびp+型ベースコンタクト層34は、p型不純物がドープされた半導体層である。より具体的には、n−型の半導体基板27に対してp型不純物をイオン注入することによって形成された半導体層であってもよい。p型不純物としては、B(ホウ素)、Al(アルミニウム)、Ga(ガリウム)などを適用することができる。
一方、n+型バッファ層29、n−型ドリフト層30、n型エンハンス層31およびn+型エミッタ層33は、n型不純物がドープされた半導体層である。より具体的には、n−型ドリフト層30はn−型の半導体基板27の不純物濃度が維持された半導体層であってよく、n+型バッファ層29、n型エンハンス層31およびn+型エミッタ層33は、n−型の半導体基板27に対してさらにn型不純物をイオン注入することによって形成された半導体層であってもよい。n型不純物としては、P(リン)、As(砒素)、Sb(アンチモン)などを用いることができる。
このn−型ドリフト層30に対して半導体基板27の表面側には、p−型ベース層32が配置され、そのp−型ベース層32の表面部にさらに、n+型エミッタ層33が配置されている。n+型エミッタ層33は、半導体基板27の表面を形成している。そして、半導体基板27の表面からn+型エミッタ層33およびp−型ベース層32を貫通してn−型ドリフト層30に達するようにゲートトレンチ36が形成されている。n−型ドリフト層30のうち当該ゲートトレンチ36の下部を覆う部分が、n−型ドリフト層30の他領域(n−型領域)よりも相対的に高い不純物濃度を有するn型エンハンス層31となっている。つまり、n型エンハンス層31は、p−型ベース層32の直下全体にp−型ベース層32に接するように形成されており、ゲートトレンチ36の下部内面を形成している。
図3Aに示すように、ゲートトレンチ36は、平面視ストライプ状に形成されている。ストライプ状のゲートトレンチ36のピッチP1は、たとえば、2μm〜7μmである。また、各ゲートトレンチ36は、2μm〜6μmの深さD1を有している。ゲートトレンチ36には、たとえば酸化シリコン等からなるゲート絶縁膜37を介して、ゲート電極25が埋め込まれている。このゲートトレンチ36およびゲート電極25は、図2Bでも示したが、半導体基板27においてストライプ状の単位セル26を区画する。なお、ゲートトレンチ36は、この実施形態で図示したストライプ状に限らず、たとえば、格子状(四角格子、六角格子等)、千鳥格子状に形成されていてもよい。
層間絶縁膜39上には、たとえばTi/TiNからなるバリアメタル41を介して、エミッタメタル15が形成されている。エミッタメタル15は、コンタクトホール40およびコンタクトトレンチ38を介して、p+型ベースコンタクト層34に接続されている。
図4は、n+型バッファ層29および欠陥層35の不純物濃度を説明するための図である。図4では、比較のため、ピークが一つしかないn+型バッファ層29の不純物濃度のプロファイルも示している。次に、図3Bに図4を加えて、n+型バッファ層29および欠陥層35の形成位置、不純物濃度等について説明する。
スイッチング素子チップ2を製造するには、まず、半導体基板27のもとになる半導体ウエハが準備される(ステップS1)。使用される半導体ウエハ(シリコンウエハ)は、エピタキシャルウエハおよびFZウエハのいずれであってもよいが、低VCE(sat)および高速スイッチングを実現する観点から、FZウエハである方が好ましい。FZウエハであれば、キャリア濃度の勾配が小さく移動度の大きい電子電流成分が増加するので、少ないキャリアで多くの電流を流すことができる。
次に、半導体基板27(半導体ウエハ)が選択的にエッチングされることによって、ゲートトレンチ36が形成される(ステップS3)。これにより、半導体基板27のアクティブ領域に多数の単位セル26が区画される。
次に、ゲートトレンチ36にポリシリコン等の電極材料が埋め込まれることによって、ゲートトレンチ36内にゲート電極25が形成される(ステップS5)。
次に、半導体基板27の表面にp型不純物(たとえばB(ホウ素))が選択的に注入され、その後のアニール処理で拡散させることによって、半導体基板27の表面部にp−型ベース層32が形成される(ステップS6)。
次に、半導体基板27が選択的にエッチングされることによって、各単位セル26にコンタクトトレンチ38が形成される(ステップS8)。
次に、たとえばスパッタ法によってバリアメタル41が形成され(ステップS10)、さらにスパッタ法によって、エミッタメタル15が形成される(ステップS11)。
次の工程は、n+型バッファ層29およびp−型コレクタ層28のインプラ工程である。この工程では、まず、半導体基板27の裏面側から、第1エネルギ(たとえば、1200keV程度)でn型不純物(たとえばP(リン))が注入され(ステップS14)、続けて第1エネルギよりも低い第2エネルギ(たとえば、600keV程度)でn型不純物が注入される(ステップS15)。さらに、半導体基板27の裏面側から、n+型バッファ層29のときによりも低いエネルギでp型不純物(たとえばB(ホウ素))が注入される(ステップS16)。
次に、半導体基板27の裏面側から、欠陥層35の形成のための粒子照射が行われる。この実施形態では、4Heが照射される(ステップS18)。なお、このときに照射される粒子としては、前述したように、4Heの他、3He、H、P、F、Ar、As、SbおよびSiの少なくとも一種の粒子であってもよい。また、照射装置としては、たとえば、イオン注入装置、サイクロトロンまたはバンデグラフを使用できる。
以上、本発明の一実施形態について説明したが、本発明は、他の形態で実施することもできる。
また、スイッチング素子チップ2は、前述のトレンチゲート型IGBTではなく、プレーナゲート型IGBTを備えていてもよい。
<試作品の作製>
まず、以下で説明する特性比較に使用する試作品として、実施例1および参考例1,2に係る半導体装置を作製した。
(1)実施例1
実施例1の半導体装置は、図3Aおよび図3Bの構造(基板厚さ=60μm、ゲートトレンチピッチP1=3.4μm、ゲートトレンチ深さD1=2.3μm)を有し、さらに、n+型バッファ層29の不純物濃度プロファイルが図4のプロファイル43(ダブルピーク)である半導体装置とした。
(2)参考例1
参考例1の半導体装置は、基板厚さ=70μm、ゲートトレンチピッチP1=7.0μm、ゲートトレンチ深さD1=5.0μm、n+型バッファ層29の不純物濃度プロファイルが図4のプロファイル46(シングルピーク)であり、n型エンハンス層31および欠陥層35を備えていない点において、実施例1の半導体装置と異なる半導体装置とした。
(3)参考例2
参考例2の半導体装置は、n型エンハンス層31および欠陥層35を備えていない点において、実施例1の半導体装置と異なる半導体装置とした。
(4)参考例3
参考例3の半導体装置は、欠陥層35を備えていない点において、実施例1の半導体装置と異なる半導体装置とした。
<特性評価>
実施例1および参考例1,2,3の半導体装置の(1)耐圧、(2)VCE(sat)特性、(3)スイッチング特性および(4)効率特性を、それぞれ評価した。結果を、図6〜図12に示す。
2 スイッチング素子チップ
25 ゲート電極
27 半導体基板
28 p−型コレクタ層
29 n+型バッファ層
30 n−型ドリフト層
31 n型エンハンス層
32 p−型ベース層
33 n+型エミッタ層
35 欠陥層
36 ゲートトレンチ
37 ゲート絶縁膜
43 プロファイル
44 第1ピーク
45 第2ピーク
47 プロファイル
48 ピーク
Claims (17)
- 第1導電型のドリフト層を挟んで表面側に第1導電型のエミッタ層が形成され、裏面側に第2導電型のコレクタ層が形成された半導体基板と、
前記ドリフト層と前記エミッタ層との間の第2導電型のベース層と、
前記コレクタ層と前記ドリフト層との間の第1導電型のバッファ層であって、前記ドリフト層よりも高い不純物濃度を有し、かつ前記半導体基板の裏面からの深さ方向に関して2つのピークを持つ不純物濃度のプロファイルを有するバッファ層と、
前記ドリフト層に形成され、前記半導体基板の裏面からの深さ方向に関して半値幅が2μm以下の不純物濃度のプロファイルを有する欠陥層とを含む、半導体装置。 - 前記欠陥層は、4He、3He、H、P、F、Ar、As、SbおよびSiの少なくとも一種を含む、請求項1に記載の半導体装置。
- 前記欠陥層は、前記半導体基板の裏面から1μm〜3μmの間に形成されている、請求項1または2に記載の半導体装置。
- 前記バッファ層の前記不純物濃度のプロファイルは、前記半導体基板の前記裏面から相対的に浅い領域に第1ピークを有し、前記第1ピークよりも相対的に深い領域に前記第1ピークよりも低い不純物濃度の第2ピークを有している、請求項1〜3のいずれか一項に記載の半導体装置。
- 前記第1ピークの不純物濃度は、2×1016cm−3〜2×1018cm−3であり、前記第2ピークの不純物濃度は、6×1015cm−3〜6×1017cm−3である、請求項4に記載の半導体装置。
- 前記半導体基板は、40μm〜200μmの厚さを有している、請求項1〜5のいずれか一項に記載の半導体装置。
- 前記半導体基板の表面から前記エミッタ層および前記ベース層を貫通して前記ドリフト層に達するゲートトレンチと、
前記ゲートトレンチの内面に形成されたゲート絶縁膜を介して前記ゲートトレンチに埋め込まれたゲート電極とを含む、請求項1〜6のいずれか一項に記載の半導体装置。 - 前記ゲートトレンチは、2μm〜7μmのピッチで形成されている、請求項7に記載の半導体装置。
- 前記ゲートトレンチは、2μm〜6μmの深さを有している、請求項7または8に記載の半導体装置。
- 前記ドリフト層は、前記ベース層の直下に形成され、前記ドリフト層の他領域よりも相対的に高い不純物濃度を有するエンハンス層を含む、請求項7〜9のいずれか一項に記載の半導体装置。
- 前記半導体基板は、シリコン基板を含む、請求項1〜10のいずれか一項に記載の半導体装置。
- ドリフト層を有する第1導電型の半導体基板の表面部に第2導電型のベース層を形成し、当該ベース層の表面部に第1導電型のエミッタ層を形成する工程と、
前記半導体基板の裏面から、第1エネルギで第1導電型不純物を注入し、次に、前記第1エネルギとは異なる第2エネルギで第1導電型不純物を注入することによって、前記ドリフト層よりも高い不純物濃度を有し、かつ前記半導体基板の裏面からの深さ方向に関して2つのピークを持つ不純物濃度のプロファイルを有するバッファ層を形成する工程と、
前記半導体基板の裏面から第2導電型不純物を注入することによって、前記バッファ層に対して前記半導体基板の裏面側にコレクタ層を形成する工程と、
前記半導体基板の裏面に対して4He、3He、H、P、F、Ar、As、SbおよびSiの少なくとも一種の粒子を照射し、前記半導体基板をアニール処理することによって、前記半導体基板の裏面からの深さ方向に関して半値幅が2μm以下の不純物濃度のプロファイルを有する欠陥層を前記ドリフト層に形成する工程とを含む、半導体装置の製造方法。 - 前記第1エネルギは、前記第2エネルギよりも高い、請求項12に記載の半導体装置の製造方法。
- 前記コレクタ層の形成後、前記バッファ層および前記コレクタ層内の不純物を活性化させる第1アニール処理工程を含み、
前記欠陥層を形成するときのアニール処理は、前記第1アニール処理工程時よりも低温で前記半導体基板をアニール処理する第2アニール処理工程を含む、請求項12または13に記載の半導体装置の製造方法。 - 前記第1アニール処理工程は、第1エネルギ密度を有するレーザ照射による第1レーザアニール工程を含み、
前記第2アニール処理工程は、前記第1エネルギ密度よりも低い第2エネルギ密度を有するレーザ照射による第2レーザアニール工程を含む、請求項14に記載の半導体装置の製造方法。 - 前記第1エネルギ密度は1J/cm2〜3J/cm2であり、前記第2エネルギ密度は0.1J/cm2〜0.5J/cm2である、請求項15に記載の半導体装置の製造方法。
- 前記粒子は、イオン注入装置、サイクロトロンまたはバンデグラフによって照射される、請求項12〜16のいずれか一項に記載の半導体装置の製造方法。
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