JP2017028096A - 薄膜キャパシタ及び半導体装置 - Google Patents
薄膜キャパシタ及び半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 145
- 239000003990 capacitor Substances 0.000 title claims abstract description 69
- 239000010409 thin film Substances 0.000 title claims abstract description 63
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- 239000010410 layer Substances 0.000 description 132
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- 230000000052 comparative effect Effects 0.000 description 17
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- 239000010949 copper Substances 0.000 description 9
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
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- 230000003746 surface roughness Effects 0.000 description 6
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052742 iron Inorganic materials 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
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- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
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Abstract
Description
図1は本発明の一実施形態に係る薄膜キャパシタの概略断面図である。本実施形態の薄膜キャパシタ10は、第1電極層(以下、下部電極層と言うことがある)1と、第2電極層(以下、上部電極層と言うことがある)3と、上記第1電極層1及び上記第2電極層3の間に設けられた誘電体層2とを備える。言い換えると、上記薄膜キャパシタ10は第1電極層1と第2電極層3との間に誘電体層2を挟み込むように構成されている。
図2は本発明の一実施形態に係る半導体装置の概略断面図である。本実施形態の半導体装置20は、支持基板13と、上記支持基板13の一方の主面上に搭載された半導体素子11と、上述の薄膜キャパシタ10とを備える。上記半導体装置20において、上記薄膜キャパシタ10は、上記第2電極層(上部電極層)3と上記半導体素子11とが対向するように、上記支持基板13内に埋め込まれている。薄膜キャパシタ10を支持基板13内に埋め込むことによって、複雑な構造を有することなく、バンプなどのハンダが溶融して薄膜キャパシタに接触することにより生じるショート不良を抑制することができる。
(表面積Sの測定方法)
下記実施例及び比較例で得られた薄膜キャパシタ10の下部電極層1の下面4の表面積Sを、非接触断面粗さ測定装置(商品名:NH−3N、三鷹光器社製)により、測定した。
下記実施例及び比較例で得られた薄膜キャパシタ10の下部電極層1の下面4の粗さ曲線を、接触式表面粗さ計(商品名:サーフコム1500S、東京精密社製)にて触針して、計測し、十点平均粗さRzを算出した。なお、十点平均粗さRzは、粗さ曲線からその平均線の方向に基準長さだけを抜き取り、この抜き取り部分の平均線から縦倍率の方向に測定した、最も高い山頂から5番目までの山頂の標高の絶対値の平均値と、最も低い谷底から5番目までの谷底の標高の絶対値の平均値との和を求め、この値をマイクロメートルで表したものを言う(JIS B0601(2013)附属書JA参照)。
[薄膜キャパシタ及び半導体装置の作製]
下部電極層1と、上部電極層3と、下部電極層1及び上部電極層3の間に設けられた誘電体層2とを備える薄膜キャパシタ10を作製した。上記下部電極層1には、厚さ方向の投影面積S0が100mm2であり、算術平均厚さ40μmの電解Ni箔を用い、電解ドラムの表面状態を調節することで、一方の面(下面)の表面積Sを下記表1に記載のとおりに100mm2から1000mm2の範囲で変更した。上記誘電体層2は、厚さ800nmのBaTiO3からなり、上記下部電極層1の他方の面(上面)上に形成した。上記上部電極層3は、上記誘電体層2上に、厚さ0.5μmのNi層、厚さ1.0μmのCu層、及び厚さ16.5μmのCu層をこの順で積層することにより形成した。
図3(a)及び(b)に示すように、支持基板13の下部電極層1側の主面に形成した引出電極を、球状バンプ14を介して母基板24と接続した。次に、作製した半導体装置20の半導体素子11の上面に熱電対Aのプラス端子21とマイナス端子22との熱接点23を設け、半導体装置の温度が測定可能となるようにした。熱電対Aには、K型熱電対を用いた。半導体装置20及び熱電対Aを300Kに設定した恒温槽内に配置した。十分な時間を経過させた後、半導体素子11の温度が恒温槽の温度設定値とほぼ同じとなったことを確認した。
下部電極層1として電解Ni箔に代えて、それぞれ電解Fe箔及び電解Cu箔を用いたこと以外は、実施例1と同様にして、実施例4及び実施例5の半導体装置20を作製した。実施例4及び実施例5で得られた半導体装置に対し、実施例1と同様の工程で放熱性試験を行った。実施例4及び実施例5の半導体装置20における、下部電極層1の材料、S/S0比、下部電極層1の熱伝導率λ、下面4の十点平均粗さRz、及び、放熱性試験における2000ミリ秒後の半導体素子温度の到達点をまとめて表3に示す。
図8は実施例6〜12で得られた半導体装置の概略断面図である。下部電極層1に、Arイオンビームによる逆スパッタリングにて、下面4の表面粗さを調整した電解Ni箔を用いたこと以外は、実施例1と同様にして、実施例6〜12の半導体装置を作製した。なお、実施例6〜12では、電解Ni箔の下面4の十点平均粗さRzがそれぞれ0.02μm、0.10μm、0.50μm、1.00μm、2.00μm、3.00μm及び4.00μmとなるように、逆スパッタリングを行った。各実施例について、半導体装置を5つずつ作製し、それぞれの半導体装置に対して実施例1と同様の工程で放熱性試験を行った。なお、薄膜キャパシタ10が埋め込まれた支持基板13の内部をX線CTスキャナを用いて観察したところ、下部電極層1の下面4の十点平均粗さRzは埋め込まれる前から変化しておらず、半導体装置製造工程において下部電極層1に変形がなかったことを確認した。実施例6〜12の半導体装置における下面4の十点平均粗さRz、S/S0比、支持基板13内の下部電極層1の下面4の付近の空隙15の数、及び、放熱性試験における2000ミリ秒後の半導体素子温度の到達点を、表4にまとめて示す。
下部電極層1として電解Ni箔に代えて、電解Fe箔を用いたこと以外は、実施例6〜12と同様にして、実施例13〜19の半導体装置20を作製した。実施例13〜19で得られた半導体装置に対し、実施例6と同様の工程で放熱性試験を行った。実施例13〜19の半導体装置20における、下部電極層1の材料、下部電極層1の熱伝導率λ、S/S0比、下面4の十点平均粗さRz、及び、放熱性試験における2000ミリ秒後の半導体素子温度の到達点をまとめて表5に示す。
下部電極層1として電解Ni箔に代えて、電解Cu箔を用いたこと以外は、実施例6〜12と同様にして、実施例20〜26の半導体装置20を作製した。実施例20〜26で得られた半導体装置に対し、実施例6と同様の工程で放熱性試験を行った。実施例20〜26の半導体装置20における、下部電極層1の材料、S/S0比、下面4の十点平均粗さRz、下部電極層1の熱伝導率λ、及び、放熱性試験における2000ミリ秒後の半導体素子温度の到達点をまとめて表5に示す。
Claims (4)
- 第1電極層と、第2電極層と、前記第1電極層及び前記第2電極層の間に設けられた誘電体層とを備え、
前記第1電極層の前記誘電体層と反対側の面の表面積Sと前記第1電極層の厚さ方向の投影面積S0との比(S/S0)が1.01〜5.00である、薄膜キャパシタ。 - 前記第1電極層の熱伝導率λが90W/(m・K)以上である、請求項1に記載の薄膜キャパシタ。
- 前記第1電極層の前記誘電体層と反対側の面の十点平均粗さRzが0.02〜2.00μmである、請求項1又は2に記載の薄膜キャパシタ。
- 支持基板と、前記支持基板の一方の主面上に搭載された半導体素子と、請求項1〜3のいずれか一項に記載の薄膜キャパシタとを備え、
前記薄膜キャパシタが、前記第2電極層と前記半導体素子とが対向するように、前記支持基板内に埋め込まれている、半導体装置。
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