JP2016520239A5 - - Google Patents

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Publication number
JP2016520239A5
JP2016520239A5 JP2016516741A JP2016516741A JP2016520239A5 JP 2016520239 A5 JP2016520239 A5 JP 2016520239A5 JP 2016516741 A JP2016516741 A JP 2016516741A JP 2016516741 A JP2016516741 A JP 2016516741A JP 2016520239 A5 JP2016520239 A5 JP 2016520239A5
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JP
Japan
Prior art keywords
output
circuit
multiplexer
switch box
decoder
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JP2016516741A
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English (en)
Japanese (ja)
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JP6130058B2 (ja
JP2016520239A (ja
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Priority claimed from US13/905,032 external-priority patent/US9465758B2/en
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Publication of JP2016520239A5 publication Critical patent/JP2016520239A5/ja
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Publication of JP6130058B2 publication Critical patent/JP6130058B2/ja
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JP2016516741A 2013-05-29 2014-05-27 条件付きのチャネルルーティングおよびインプレースの機能性を持つ再設定可能な命令セルのアレイ Active JP6130058B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/905,032 US9465758B2 (en) 2013-05-29 2013-05-29 Reconfigurable instruction cell array with conditional channel routing and in-place functionality
US13/905,032 2013-05-29
PCT/US2014/039612 WO2014193851A2 (en) 2013-05-29 2014-05-27 Reconfigurable instruction cell array with conditional channel routing and in-place functionality

Publications (3)

Publication Number Publication Date
JP2016520239A JP2016520239A (ja) 2016-07-11
JP2016520239A5 true JP2016520239A5 (enExample) 2017-01-12
JP6130058B2 JP6130058B2 (ja) 2017-05-17

Family

ID=51168336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016516741A Active JP6130058B2 (ja) 2013-05-29 2014-05-27 条件付きのチャネルルーティングおよびインプレースの機能性を持つ再設定可能な命令セルのアレイ

Country Status (6)

Country Link
US (1) US9465758B2 (enExample)
EP (1) EP3005140A2 (enExample)
JP (1) JP6130058B2 (enExample)
KR (1) KR101746819B1 (enExample)
CN (1) CN105247505B (enExample)
WO (1) WO2014193851A2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170083313A1 (en) * 2015-09-22 2017-03-23 Qualcomm Incorporated CONFIGURING COARSE-GRAINED RECONFIGURABLE ARRAYS (CGRAs) FOR DATAFLOW INSTRUCTION BLOCK EXECUTION IN BLOCK-BASED DATAFLOW INSTRUCTION SET ARCHITECTURES (ISAs)
US20190235863A1 (en) * 2018-01-31 2019-08-01 Qualcomm Incorporated Sort instructions for reconfigurable computing cores
DE102019006293A1 (de) * 2019-09-05 2021-03-11 PatForce GmbH Switchbox

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3308770B2 (ja) * 1994-07-22 2002-07-29 三菱電機株式会社 情報処理装置および情報処理装置における計算方法
US5956518A (en) 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
JP4213044B2 (ja) * 2002-03-18 2009-01-21 エヌエックスピー ビー ヴィ Ｌｕｔベースのリコンフィギュラブル・ロジック・アーキテクチャのためのコンフィギュレーション・メモリの実装
US7193994B1 (en) 2002-08-16 2007-03-20 Intel Corporation Crossbar synchronization technique
US20050289326A1 (en) 2004-06-26 2005-12-29 Hong Kong University Of Science & Technology Packet processor with mild programmability
US7804504B1 (en) 2004-12-13 2010-09-28 Massachusetts Institute Of Technology Managing yield for a parallel processing integrated circuit
JP6059413B2 (ja) * 2005-04-28 2017-01-11 クアルコム，インコーポレイテッド 再構成可能命令セル・アレイ
JP5020029B2 (ja) * 2007-11-16 2012-09-05 株式会社メガチップス 画像処理装置
US20090193384A1 (en) 2008-01-25 2009-07-30 Mihai Sima Shift-enabled reconfigurable device
GB2471067B (en) 2009-06-12 2011-11-30 Graeme Roy Smith Shared resource multi-thread array processor
KR101451254B1 (ko) * 2010-07-16 2014-10-15 엠.에스. 라마이아 스쿨 오브 어드밴스드 스터디스 데이터 인터페이스 회로
US9392640B2 (en) * 2012-10-01 2016-07-12 Freescale Semiconductor, Inc. Method and system for automatically controlling the insertion of control word in CPRI daisy chain configuration

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