CN105247505B - 具有条件通道路由和就地功能性的可重配置指令单元阵列 - Google Patents

具有条件通道路由和就地功能性的可重配置指令单元阵列 Download PDF

Info

Publication number
CN105247505B
CN105247505B CN201480030820.3A CN201480030820A CN105247505B CN 105247505 B CN105247505 B CN 105247505B CN 201480030820 A CN201480030820 A CN 201480030820A CN 105247505 B CN105247505 B CN 105247505B
Authority
CN
China
Prior art keywords
output
multiplexer
decoder
circuit
switch box
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201480030820.3A
Other languages
English (en)
Chinese (zh)
Other versions
CN105247505A (zh
Inventor
I·诺西亚斯
S·赫瓦姆
M·I·R·穆尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105247505A publication Critical patent/CN105247505A/zh
Application granted granted Critical
Publication of CN105247505B publication Critical patent/CN105247505B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Multi Processors (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
CN201480030820.3A 2013-05-29 2014-05-27 具有条件通道路由和就地功能性的可重配置指令单元阵列 Expired - Fee Related CN105247505B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/905,032 US9465758B2 (en) 2013-05-29 2013-05-29 Reconfigurable instruction cell array with conditional channel routing and in-place functionality
US13/905,032 2013-05-29
PCT/US2014/039612 WO2014193851A2 (en) 2013-05-29 2014-05-27 Reconfigurable instruction cell array with conditional channel routing and in-place functionality

Publications (2)

Publication Number Publication Date
CN105247505A CN105247505A (zh) 2016-01-13
CN105247505B true CN105247505B (zh) 2017-12-12

Family

ID=51168336

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480030820.3A Expired - Fee Related CN105247505B (zh) 2013-05-29 2014-05-27 具有条件通道路由和就地功能性的可重配置指令单元阵列

Country Status (6)

Country Link
US (1) US9465758B2 (enExample)
EP (1) EP3005140A2 (enExample)
JP (1) JP6130058B2 (enExample)
KR (1) KR101746819B1 (enExample)
CN (1) CN105247505B (enExample)
WO (1) WO2014193851A2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170083313A1 (en) * 2015-09-22 2017-03-23 Qualcomm Incorporated CONFIGURING COARSE-GRAINED RECONFIGURABLE ARRAYS (CGRAs) FOR DATAFLOW INSTRUCTION BLOCK EXECUTION IN BLOCK-BASED DATAFLOW INSTRUCTION SET ARCHITECTURES (ISAs)
US20190235863A1 (en) * 2018-01-31 2019-08-01 Qualcomm Incorporated Sort instructions for reconfigurable computing cores
DE102019006293A1 (de) * 2019-09-05 2021-03-11 PatForce GmbH Switchbox

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956518A (en) * 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
CN1643792A (zh) * 2002-03-18 2005-07-20 皇家飞利浦电子股份有限公司 基于lut可重配置逻辑体系结构的配置存储器实现
WO2006114642A1 (en) * 2005-04-28 2006-11-02 The University Court Of The University Of Edinburgh Reconfigurable instruction cell array
US7193994B1 (en) * 2002-08-16 2007-03-20 Intel Corporation Crossbar synchronization technique
US8155113B1 (en) * 2004-12-13 2012-04-10 Massachusetts Institute Of Technology Processing data in a parallel processing environment
CN103026349A (zh) * 2010-07-16 2013-04-03 拉迈亚高级研究院 数据接口电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3308770B2 (ja) * 1994-07-22 2002-07-29 三菱電機株式会社 情報処理装置および情報処理装置における計算方法
US20050289326A1 (en) 2004-06-26 2005-12-29 Hong Kong University Of Science & Technology Packet processor with mild programmability
JP5020029B2 (ja) * 2007-11-16 2012-09-05 株式会社メガチップス 画像処理装置
US20090193384A1 (en) 2008-01-25 2009-07-30 Mihai Sima Shift-enabled reconfigurable device
GB2471067B (en) 2009-06-12 2011-11-30 Graeme Roy Smith Shared resource multi-thread array processor
US9392640B2 (en) * 2012-10-01 2016-07-12 Freescale Semiconductor, Inc. Method and system for automatically controlling the insertion of control word in CPRI daisy chain configuration

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956518A (en) * 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
CN1643792A (zh) * 2002-03-18 2005-07-20 皇家飞利浦电子股份有限公司 基于lut可重配置逻辑体系结构的配置存储器实现
US7193994B1 (en) * 2002-08-16 2007-03-20 Intel Corporation Crossbar synchronization technique
US8155113B1 (en) * 2004-12-13 2012-04-10 Massachusetts Institute Of Technology Processing data in a parallel processing environment
WO2006114642A1 (en) * 2005-04-28 2006-11-02 The University Court Of The University Of Edinburgh Reconfigurable instruction cell array
CN103026349A (zh) * 2010-07-16 2013-04-03 拉迈亚高级研究院 数据接口电路

Also Published As

Publication number Publication date
JP2016520239A (ja) 2016-07-11
KR101746819B1 (ko) 2017-06-13
CN105247505A (zh) 2016-01-13
US20140359174A1 (en) 2014-12-04
JP6130058B2 (ja) 2017-05-17
WO2014193851A3 (en) 2015-03-05
US9465758B2 (en) 2016-10-11
EP3005140A2 (en) 2016-04-13
WO2014193851A2 (en) 2014-12-04
KR20160015275A (ko) 2016-02-12

Similar Documents

Publication Publication Date Title
KR102438730B1 (ko) 공간 다중화를 지원하는 디램 기초의 재설정 가능 논리 장치
US6803787B1 (en) State machine in a programmable logic device
US20040019765A1 (en) Pipelined reconfigurable dynamic instruction set processor
US9588773B2 (en) Software based application specific integrated circuit
US20120191967A1 (en) Configurable data processing system and method
US9081060B2 (en) Buffer testing for reconfigurable instruction cell arrays
US20040111590A1 (en) Self-configuring processing element
CN105247505B (zh) 具有条件通道路由和就地功能性的可重配置指令单元阵列
US20190235863A1 (en) Sort instructions for reconfigurable computing cores
CN105009106B (zh) 可重配置指令单元阵列的并行配置
EP3044879B1 (en) Serial configuration of a reconfigurable instruction cell array
JP6385962B2 (ja) 埋込み再構成可能コンピューティングのためのスイッチングファブリック
US10289382B2 (en) Selectively combinable directional shifters
WO2011131250A1 (en) Reuse of constants between arithmetic logic units and look-up-tables
JP2010086256A (ja) 並列処理型プロセッサ

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20171212

Termination date: 20210527

CF01 Termination of patent right due to non-payment of annual fee