JP6130058B2 - 条件付きのチャネルルーティングおよびインプレースの機能性を持つ再設定可能な命令セルのアレイ - Google Patents

条件付きのチャネルルーティングおよびインプレースの機能性を持つ再設定可能な命令セルのアレイ Download PDF

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JP6130058B2
JP6130058B2 JP2016516741A JP2016516741A JP6130058B2 JP 6130058 B2 JP6130058 B2 JP 6130058B2 JP 2016516741 A JP2016516741 A JP 2016516741A JP 2016516741 A JP2016516741 A JP 2016516741A JP 6130058 B2 JP6130058 B2 JP 6130058B2
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output
circuit
multiplexer
decoder
switch box
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Japanese (ja)
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JP2016520239A (ja
JP2016520239A5 (enExample
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ノーシアス、イオアニス
クハワム、サミ
ムーア、マーク・イアン・ロイ
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Multi Processors (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
JP2016516741A 2013-05-29 2014-05-27 条件付きのチャネルルーティングおよびインプレースの機能性を持つ再設定可能な命令セルのアレイ Active JP6130058B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/905,032 US9465758B2 (en) 2013-05-29 2013-05-29 Reconfigurable instruction cell array with conditional channel routing and in-place functionality
US13/905,032 2013-05-29
PCT/US2014/039612 WO2014193851A2 (en) 2013-05-29 2014-05-27 Reconfigurable instruction cell array with conditional channel routing and in-place functionality

Publications (3)

Publication Number Publication Date
JP2016520239A JP2016520239A (ja) 2016-07-11
JP2016520239A5 JP2016520239A5 (enExample) 2017-01-12
JP6130058B2 true JP6130058B2 (ja) 2017-05-17

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JP2016516741A Active JP6130058B2 (ja) 2013-05-29 2014-05-27 条件付きのチャネルルーティングおよびインプレースの機能性を持つ再設定可能な命令セルのアレイ

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US (1) US9465758B2 (enExample)
EP (1) EP3005140A2 (enExample)
JP (1) JP6130058B2 (enExample)
KR (1) KR101746819B1 (enExample)
CN (1) CN105247505B (enExample)
WO (1) WO2014193851A2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170083313A1 (en) * 2015-09-22 2017-03-23 Qualcomm Incorporated CONFIGURING COARSE-GRAINED RECONFIGURABLE ARRAYS (CGRAs) FOR DATAFLOW INSTRUCTION BLOCK EXECUTION IN BLOCK-BASED DATAFLOW INSTRUCTION SET ARCHITECTURES (ISAs)
US20190235863A1 (en) * 2018-01-31 2019-08-01 Qualcomm Incorporated Sort instructions for reconfigurable computing cores
DE102019006293A1 (de) * 2019-09-05 2021-03-11 PatForce GmbH Switchbox

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3308770B2 (ja) * 1994-07-22 2002-07-29 三菱電機株式会社 情報処理装置および情報処理装置における計算方法
US5956518A (en) 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US7183796B2 (en) * 2002-03-18 2007-02-27 Nxp Bv. Configuration memory implementation for LUT-based reconfigurable logic architectures
US7193994B1 (en) 2002-08-16 2007-03-20 Intel Corporation Crossbar synchronization technique
US20050289326A1 (en) 2004-06-26 2005-12-29 Hong Kong University Of Science & Technology Packet processor with mild programmability
US8155113B1 (en) 2004-12-13 2012-04-10 Massachusetts Institute Of Technology Processing data in a parallel processing environment
DE602006021001D1 (de) * 2005-04-28 2011-05-12 Univ Edinburgh Umkonfigurierbares anweisungs-zellen-array
JP5020029B2 (ja) * 2007-11-16 2012-09-05 株式会社メガチップス 画像処理装置
US20090193384A1 (en) 2008-01-25 2009-07-30 Mihai Sima Shift-enabled reconfigurable device
GB2471067B (en) 2009-06-12 2011-11-30 Graeme Roy Smith Shared resource multi-thread array processor
KR101451254B1 (ko) * 2010-07-16 2014-10-15 엠.에스. 라마이아 스쿨 오브 어드밴스드 스터디스 데이터 인터페이스 회로
US9392640B2 (en) * 2012-10-01 2016-07-12 Freescale Semiconductor, Inc. Method and system for automatically controlling the insertion of control word in CPRI daisy chain configuration

Also Published As

Publication number Publication date
US9465758B2 (en) 2016-10-11
KR20160015275A (ko) 2016-02-12
JP2016520239A (ja) 2016-07-11
CN105247505A (zh) 2016-01-13
WO2014193851A2 (en) 2014-12-04
WO2014193851A3 (en) 2015-03-05
US20140359174A1 (en) 2014-12-04
EP3005140A2 (en) 2016-04-13
KR101746819B1 (ko) 2017-06-13
CN105247505B (zh) 2017-12-12

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