GB2578972A8 - Instruction and logic to provide vector scatter-op and gather-op functionality - Google Patents

Instruction and logic to provide vector scatter-op and gather-op functionality Download PDF

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Publication number
GB2578972A8
GB2578972A8 GB1916688.3A GB201916688A GB2578972A8 GB 2578972 A8 GB2578972 A8 GB 2578972A8 GB 201916688 A GB201916688 A GB 201916688A GB 2578972 A8 GB2578972 A8 GB 2578972A8
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United Kingdom
Prior art keywords
data elements
source register
instruction
gather
functionality
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB1916688.3A
Other versions
GB2578972A (en
GB2578972B (en
GB201916688D0 (en
Inventor
Ould-Ahmed-Vall Elmoustapha
A Doshi Kshitij
R Yount Charles
Sair Suleyman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to GB1916688.3A priority Critical patent/GB2578972B/en
Priority claimed from GB201402493A external-priority patent/GB2508533B/en
Publication of GB201916688D0 publication Critical patent/GB201916688D0/en
Publication of GB2578972A publication Critical patent/GB2578972A/en
Publication of GB2578972A8 publication Critical patent/GB2578972A8/en
Application granted granted Critical
Publication of GB2578972B publication Critical patent/GB2578972B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Abstract

Decoding an SIMD instruction comprising a first operation and a scatter operation. The SIMD instruction is to indicate a first source register with a first plurality of data elements, indicate a second source register comprising a second plurality of data element different from the first, and indicate a third source register which has a plurality of indices, each corresponding to the first plurality of elements. Also included is or more execution units to perform the first operation on the first and second data elements to form corresponding result data elements, and then perform a scatter operation to store each result data element in memory. The first operation may be binary, addition, multiplication or ternary. The first source register may comprise 512 bits and wherein the data elements of the first source register are one of 32 bit data elements and 64 bit data elements.
GB1916688.3A 2011-09-26 2011-09-26 Instruction and logic to provide vector scatter-op and gather-op functionality Active GB2578972B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB1916688.3A GB2578972B (en) 2011-09-26 2011-09-26 Instruction and logic to provide vector scatter-op and gather-op functionality

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB201402493A GB2508533B (en) 2011-09-26 2011-09-26 Instruction and logic to provide vector scatter-op and gather-op functionality
GB1916688.3A GB2578972B (en) 2011-09-26 2011-09-26 Instruction and logic to provide vector scatter-op and gather-op functionality

Publications (4)

Publication Number Publication Date
GB201916688D0 GB201916688D0 (en) 2020-01-01
GB2578972A GB2578972A (en) 2020-06-03
GB2578972A8 true GB2578972A8 (en) 2020-07-08
GB2578972B GB2578972B (en) 2020-10-07

Family

ID=69063429

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1916688.3A Active GB2578972B (en) 2011-09-26 2011-09-26 Instruction and logic to provide vector scatter-op and gather-op functionality

Country Status (1)

Country Link
GB (1) GB2578972B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111930471B (en) * 2020-08-14 2023-05-26 中国科学院上海高等研究院 Parallel simulation evaluation selection method based on GPU

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7984273B2 (en) * 2007-12-31 2011-07-19 Intel Corporation System and method for using a mask register to track progress of gathering elements from memory

Also Published As

Publication number Publication date
GB2578972A (en) 2020-06-03
GB2578972B (en) 2020-10-07
GB201916688D0 (en) 2020-01-01

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