JP2016519420A5 - - Google Patents
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- Publication number
- JP2016519420A5 JP2016519420A5 JP2016500941A JP2016500941A JP2016519420A5 JP 2016519420 A5 JP2016519420 A5 JP 2016519420A5 JP 2016500941 A JP2016500941 A JP 2016500941A JP 2016500941 A JP2016500941 A JP 2016500941A JP 2016519420 A5 JP2016519420 A5 JP 2016519420A5
- Authority
- JP
- Japan
- Prior art keywords
- assembly
- traces
- solder resist
- trace
- resist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/798,678 | 2013-03-13 | ||
| US13/798,678 US8896118B2 (en) | 2013-03-13 | 2013-03-13 | Electronic assembly with copper pillar attach substrate |
| PCT/US2014/022334 WO2014164402A1 (en) | 2013-03-13 | 2014-03-10 | Copper pillar attach substrate |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016519420A JP2016519420A (ja) | 2016-06-30 |
| JP2016519420A5 true JP2016519420A5 (enExample) | 2017-04-13 |
| JP6503334B2 JP6503334B2 (ja) | 2019-04-17 |
Family
ID=51523877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016500941A Active JP6503334B2 (ja) | 2013-03-13 | 2014-03-10 | 銅ピラー取り付け基板 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8896118B2 (enExample) |
| JP (1) | JP6503334B2 (enExample) |
| CN (1) | CN105190879B (enExample) |
| WO (1) | WO2014164402A1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6777148B2 (ja) * | 2016-07-28 | 2020-10-28 | 三菱電機株式会社 | 半導体装置 |
| JP6691031B2 (ja) * | 2016-10-05 | 2020-04-28 | 新光電気工業株式会社 | 配線基板及びその製造方法、半導体パッケージ |
| CN109729639B (zh) * | 2018-12-24 | 2020-11-20 | 奥特斯科技(重庆)有限公司 | 在无芯基板上包括柱体的部件承载件 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11191672A (ja) * | 1997-12-25 | 1999-07-13 | Victor Co Of Japan Ltd | プリント配線基板 |
| JP3891838B2 (ja) * | 2001-12-26 | 2007-03-14 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
| JP3829325B2 (ja) * | 2002-02-07 | 2006-10-04 | 日本電気株式会社 | 半導体素子およびその製造方法並びに半導体装置の製造方法 |
| KR100722645B1 (ko) * | 2006-01-23 | 2007-05-28 | 삼성전기주식회사 | 반도체 패키지용 인쇄회로기판 및 그 제조방법 |
| JP2008098402A (ja) * | 2006-10-12 | 2008-04-24 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| KR20090080623A (ko) * | 2008-01-22 | 2009-07-27 | 삼성전기주식회사 | 포스트 범프 및 그 형성방법 |
| JP5088489B2 (ja) * | 2008-03-03 | 2012-12-05 | セイコーエプソン株式会社 | 半導体モジュール及びその製造方法 |
| US7851345B2 (en) * | 2008-03-19 | 2010-12-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming oxide layer on signal traces for electrical isolation in fine pitch bonding |
| WO2010103934A1 (ja) * | 2009-03-12 | 2010-09-16 | ナミックス株式会社 | アンダーフィル材、及び、電子部品の実装方法 |
| KR101609023B1 (ko) | 2009-12-23 | 2016-04-04 | 스카이워크스 솔루션즈, 인코포레이티드 | 표면 마운트 스파크 갭 |
| US8587119B2 (en) * | 2010-04-16 | 2013-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive feature for semiconductor substrate and method of manufacture |
| US8367467B2 (en) | 2010-04-21 | 2013-02-05 | Stats Chippac, Ltd. | Semiconductor method of forming bump on substrate to prevent ELK ILD delamination during reflow process |
| US9905524B2 (en) * | 2011-07-29 | 2018-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures in semiconductor device and packaging assembly |
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2013
- 2013-03-13 US US13/798,678 patent/US8896118B2/en active Active
-
2014
- 2014-03-10 CN CN201480014113.5A patent/CN105190879B/zh active Active
- 2014-03-10 JP JP2016500941A patent/JP6503334B2/ja active Active
- 2014-03-10 WO PCT/US2014/022334 patent/WO2014164402A1/en not_active Ceased