JP2016518730A - 上面および側壁保護のためのモールドを備える半導体デバイス - Google Patents

上面および側壁保護のためのモールドを備える半導体デバイス Download PDF

Info

Publication number
JP2016518730A
JP2016518730A JP2016515351A JP2016515351A JP2016518730A JP 2016518730 A JP2016518730 A JP 2016518730A JP 2016515351 A JP2016515351 A JP 2016515351A JP 2016515351 A JP2016515351 A JP 2016515351A JP 2016518730 A JP2016518730 A JP 2016518730A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
mold
metal
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016515351A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016518730A5 (https=
Inventor
レイナンテ・タムナン・アルヴァラド
リザベス・アン・キーサー
ジアンウェン・シュウ
Original Assignee
クアルコム,インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム,インコーポレイテッド filed Critical クアルコム,インコーポレイテッド
Publication of JP2016518730A publication Critical patent/JP2016518730A/ja
Publication of JP2016518730A5 publication Critical patent/JP2016518730A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/014Manufacture or treatment using batch processing
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36Removing material
    • B23K26/40Removing material taking account of the properties of the material involved
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00Cutting or separating of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/141Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00Materials to be soldered, welded or cut
    • B23K2103/16Composite materials
    • B23K2103/166Multilayered materials
    • B23K2103/172Multilayered materials wherein at least one of the layers is non-metallic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00Materials to be soldered, welded or cut
    • B23K2103/50Inorganic materials other than metals or composite materials
    • B23K2103/52Ceramics
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36Removing material
    • B23K26/362Laser etching
    • B23K26/364Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36Removing material
    • B23K26/38Removing material by boring or cutting
    • B23K26/382Removing material by boring or cutting by boring
    • B23K26/389Removing material by boring or cutting by boring of fluid openings, e.g. nozzles, jets
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/0198Manufacture or treatment batch processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • H10W72/242Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • H10W72/244Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/252Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/922Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/923Bond pads having multiple stacked layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/9415Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/942Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/134Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being in grooves in the semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Microelectronics & Electronic Packaging (AREA)
JP2016515351A 2013-05-20 2014-05-12 上面および側壁保護のためのモールドを備える半導体デバイス Pending JP2016518730A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/898,427 US10141202B2 (en) 2013-05-20 2013-05-20 Semiconductor device comprising mold for top side and sidewall protection
US13/898,427 2013-05-20
PCT/US2014/037739 WO2014189704A1 (en) 2013-05-20 2014-05-12 Semiconductor device comprising mold for top side and sidewall protection

Publications (2)

Publication Number Publication Date
JP2016518730A true JP2016518730A (ja) 2016-06-23
JP2016518730A5 JP2016518730A5 (https=) 2017-06-15

Family

ID=50897962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016515351A Pending JP2016518730A (ja) 2013-05-20 2014-05-12 上面および側壁保護のためのモールドを備える半導体デバイス

Country Status (5)

Country Link
US (1) US10141202B2 (https=)
EP (1) EP3000128B1 (https=)
JP (1) JP2016518730A (https=)
CN (1) CN105229784A (https=)
WO (1) WO2014189704A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018168316A1 (ja) * 2017-03-13 2018-09-20 三菱電機株式会社 半導体装置および半導体装置の製造方法
JPWO2022249526A1 (https=) * 2021-05-25 2022-12-01

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10720495B2 (en) * 2014-06-12 2020-07-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US10128207B2 (en) * 2015-03-31 2018-11-13 Stmicroelectronics Pte Ltd Semiconductor packages with pillar and bump structures
CN106505055B (zh) * 2015-09-08 2019-08-27 中芯国际集成电路制造(天津)有限公司 半导体结构及其形成方法
US20190131247A1 (en) * 2017-10-31 2019-05-02 Microchip Technology Incorporated Semiconductor Wafer Cutting Using A Polymer Coating To Reduce Physical Damage
KR102600001B1 (ko) 2018-10-18 2023-11-08 삼성전자주식회사 스크라이브 레인을 포함하는 반도체 칩
US12113038B2 (en) * 2020-01-03 2024-10-08 Qualcomm Incorporated Thermal compression flip chip bump for high performance and fine pitch
US12021013B2 (en) * 2021-01-29 2024-06-25 Mediatek Inc. Ball pad design for semiconductor packages
US11887955B2 (en) * 2021-08-26 2024-01-30 Taiwan Semiconductor Manufacturing Company Limited Semiconductor die including stress-resistant bonding structures and methods of forming the same
US12575426B2 (en) * 2022-09-27 2026-03-10 Globalfoundries U.S. Inc. Wafer-scale chip structure and method and system for designing the structure

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001135742A (ja) * 1999-11-01 2001-05-18 Toppan Printing Co Ltd 半導体装置の製造方法
JP2001144213A (ja) * 1999-11-16 2001-05-25 Hitachi Ltd 半導体装置の製造方法および半導体装置
JP2007335830A (ja) * 2006-05-19 2007-12-27 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2009111333A (ja) * 2007-10-12 2009-05-21 Panasonic Corp 半導体装置
JP2009231791A (ja) * 2007-09-21 2009-10-08 Casio Comput Co Ltd 半導体装置およびその製造方法
US20090298234A1 (en) * 2008-05-27 2009-12-03 Lee Teak-Hoon Method of fabricating semiconductor chip package, semiconductor wafer, and method of sawing the semiconductor wafer
US7977783B1 (en) * 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
JP2011176069A (ja) * 2010-02-24 2011-09-08 Casio Computer Co Ltd 半導体装置の製造方法
US20120104604A1 (en) * 2010-11-01 2012-05-03 Texas Instruments Incorporated Crack arrest vias for ic devices
US20130026618A1 (en) * 2011-07-27 2013-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for circuit routing by way of under-bump metallization

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181569B1 (en) 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6607941B2 (en) * 2002-01-11 2003-08-19 National Semiconductor Corporation Process and structure improvements to shellcase style packaging technology
TWI226090B (en) 2003-09-26 2005-01-01 Advanced Semiconductor Eng Transparent packaging in wafer level
JP4519571B2 (ja) 2004-08-26 2010-08-04 ルネサスエレクトロニクス株式会社 半導体装置及びその検査方法と検査装置並びに半導体装置の製造方法
US7160756B2 (en) * 2004-10-12 2007-01-09 Agency For Science, Techology And Research Polymer encapsulated dicing lane (PEDL) technology for Cu/low/ultra-low k devices
US7714448B2 (en) * 2004-11-16 2010-05-11 Rohm Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US9034731B2 (en) 2005-02-03 2015-05-19 Stats Chippac Ltd. Integrated, integrated circuit singulation system
KR100652443B1 (ko) 2005-11-17 2006-12-01 삼성전자주식회사 재배선층을 갖는 웨이퍼 레벨 패키지 및 그 형성방법
US7723225B2 (en) * 2006-02-07 2010-05-25 Stats Chippac Ltd. Solder bump confinement system for an integrated circuit package
KR100887479B1 (ko) 2007-10-09 2009-03-10 주식회사 네패스 내균열성 반도체 패키지 및 그 제조 방법
US8048776B2 (en) 2008-02-22 2011-11-01 Stats Chippac, Ltd. Semiconductor device and method of supporting a wafer during backgrinding and reflow of solder bumps
CN101552248B (zh) * 2008-03-31 2013-01-23 兆装微股份有限公司 半导体装置及其制造方法
JP4666028B2 (ja) * 2008-03-31 2011-04-06 カシオ計算機株式会社 半導体装置
US8580657B2 (en) * 2008-09-23 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Protecting sidewalls of semiconductor chips using insulation films
FR2953064B1 (fr) 2009-11-20 2011-12-16 St Microelectronics Tours Sas Procede d'encapsulation de composants electroniques sur tranche
US8287996B2 (en) 2009-12-21 2012-10-16 Intel Corporation Coating for a microelectronic device, treatment comprising same, and method of managing a thermal profile of a microelectronic die
US8048778B1 (en) * 2010-12-10 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of dicing a semiconductor structure
US20130320522A1 (en) * 2012-05-30 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Re-distribution Layer Via Structure and Method of Making Same
US9275924B2 (en) 2012-08-14 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having a recess filled with a molding compound

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001135742A (ja) * 1999-11-01 2001-05-18 Toppan Printing Co Ltd 半導体装置の製造方法
JP2001144213A (ja) * 1999-11-16 2001-05-25 Hitachi Ltd 半導体装置の製造方法および半導体装置
JP2007335830A (ja) * 2006-05-19 2007-12-27 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2009231791A (ja) * 2007-09-21 2009-10-08 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2009111333A (ja) * 2007-10-12 2009-05-21 Panasonic Corp 半導体装置
US20090298234A1 (en) * 2008-05-27 2009-12-03 Lee Teak-Hoon Method of fabricating semiconductor chip package, semiconductor wafer, and method of sawing the semiconductor wafer
US7977783B1 (en) * 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
JP2011176069A (ja) * 2010-02-24 2011-09-08 Casio Computer Co Ltd 半導体装置の製造方法
US20120104604A1 (en) * 2010-11-01 2012-05-03 Texas Instruments Incorporated Crack arrest vias for ic devices
US20130026618A1 (en) * 2011-07-27 2013-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for circuit routing by way of under-bump metallization

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018168316A1 (ja) * 2017-03-13 2018-09-20 三菱電機株式会社 半導体装置および半導体装置の製造方法
JPWO2022249526A1 (https=) * 2021-05-25 2022-12-01
WO2022249526A1 (ja) * 2021-05-25 2022-12-01 ソニーセミコンダクタソリューションズ株式会社 半導体パッケージおよび電子機器

Also Published As

Publication number Publication date
CN105229784A (zh) 2016-01-06
US20140339712A1 (en) 2014-11-20
EP3000128A1 (en) 2016-03-30
US10141202B2 (en) 2018-11-27
EP3000128B1 (en) 2020-07-01
WO2014189704A1 (en) 2014-11-27

Similar Documents

Publication Publication Date Title
JP2016518730A (ja) 上面および側壁保護のためのモールドを備える半導体デバイス
US12074121B2 (en) Metal-free frame design for silicon bridges for semiconductor packages
CA2937552C (en) Integrated device comprising stacked dies on redistribution layers
US9379065B2 (en) Crack stopping structure in wafer level packaging (WLP)
US20150206854A1 (en) PACKAGE ON PACKAGE (PoP) INTEGRATED DEVICE COMPRISING A REDISTRIBUTION LAYER
US10916509B2 (en) Substrate, method of sawing substrate, and semiconductor device
US20150214127A1 (en) Integrated device comprising a substrate with aligning trench and/or cooling cavity
US9171782B2 (en) Stacked redistribution layers on die
JP2017514314A (ja) 無機層内の高密度インターコネクトおよび有機層内の再配線層を備える集積デバイス
US8772951B1 (en) Ultra fine pitch and spacing interconnects for substrate
US9490226B2 (en) Integrated device comprising a heat-dissipation layer providing an electrical path for a ground signal
JP2016518730A5 (https=)
US9466554B2 (en) Integrated device comprising via with side barrier layer traversing encapsulation layer
CN105489581B (zh) 半导体结构及其制作方法
US20140008788A1 (en) Non-circular under bump metallization (ubm) structure, orientation of non-circular ubm structure and trace orientation to inhibit peeling and/or cracking
US20210202430A1 (en) Semiconductor interconnect structures with narrowed portions, and associated systems and methods

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151124

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170427

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170427

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180312

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180424

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180709

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20190225