JP2016500930A - 無機カラーを含む導電性インターコネクト - Google Patents

無機カラーを含む導電性インターコネクト Download PDF

Info

Publication number
JP2016500930A
JP2016500930A JP2015540752A JP2015540752A JP2016500930A JP 2016500930 A JP2016500930 A JP 2016500930A JP 2015540752 A JP2015540752 A JP 2015540752A JP 2015540752 A JP2015540752 A JP 2015540752A JP 2016500930 A JP2016500930 A JP 2016500930A
Authority
JP
Japan
Prior art keywords
conductive
layer
interconnect
conductive material
inorganic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2015540752A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016500930A5 (enExample
Inventor
ヤンヤン・スン
リリー・ジャオ
マイケル・ハン
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2016500930A publication Critical patent/JP2016500930A/ja
Publication of JP2016500930A5 publication Critical patent/JP2016500930A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/50—Devices controlled by mechanical forces, e.g. pressure
    • H10W20/01—
    • H10W90/701—
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/093—Conductive package seal
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0172—Seals
    • B81C2203/019—Seals characterised by the material or arrangement of seals between parts
    • H10W72/012—
    • H10W72/01208—
    • H10W72/01215—
    • H10W72/01235—
    • H10W72/01251—
    • H10W72/01255—
    • H10W72/01257—
    • H10W72/01265—
    • H10W72/019—
    • H10W72/01908—
    • H10W72/072—
    • H10W72/07232—
    • H10W72/07236—
    • H10W72/222—
    • H10W72/241—
    • H10W72/245—
    • H10W72/252—
    • H10W72/255—
    • H10W72/283—
    • H10W72/29—
    • H10W72/9415—
    • H10W72/983—
    • H10W74/00—
    • H10W90/722—
    • H10W90/724—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Micromachines (AREA)
  • Wire Bonding (AREA)
JP2015540752A 2012-11-02 2013-10-30 無機カラーを含む導電性インターコネクト Pending JP2016500930A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261721889P 2012-11-02 2012-11-02
US61/721,889 2012-11-02
US13/764,261 US20140124877A1 (en) 2012-11-02 2013-02-11 Conductive interconnect including an inorganic collar
US13/764,261 2013-02-11
PCT/US2013/067568 WO2014070926A1 (en) 2012-11-02 2013-10-30 A conductive interconnect including an inorganic collar

Publications (2)

Publication Number Publication Date
JP2016500930A true JP2016500930A (ja) 2016-01-14
JP2016500930A5 JP2016500930A5 (enExample) 2016-11-24

Family

ID=50621573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015540752A Pending JP2016500930A (ja) 2012-11-02 2013-10-30 無機カラーを含む導電性インターコネクト

Country Status (6)

Country Link
US (1) US20140124877A1 (enExample)
EP (1) EP2915191B1 (enExample)
JP (1) JP2016500930A (enExample)
KR (1) KR20150082395A (enExample)
CN (1) CN104769711B (enExample)
WO (1) WO2014070926A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI568662B (zh) * 2013-03-08 2017-02-01 先技股份有限公司 微機電裝置
US9698116B2 (en) * 2014-10-31 2017-07-04 Nxp Usa, Inc. Thick-silver layer interface for a semiconductor die and corresponding thermal layer
US9713264B2 (en) * 2014-12-18 2017-07-18 Intel Corporation Zero-misalignment via-pad structures
US10475736B2 (en) 2017-09-28 2019-11-12 Intel Corporation Via architecture for increased density interface
US20210159198A1 (en) * 2019-11-24 2021-05-27 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
CN114649287A (zh) * 2022-05-19 2022-06-21 甬矽半导体(宁波)有限公司 一种芯片制作方法、芯片连接方法以及芯片

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06322318A (ja) * 1991-04-22 1994-11-22 Dow Corning Corp セラミック塗料及びその塗膜形成方法
US20110285011A1 (en) * 2010-05-18 2011-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with l-shaped non-metal sidewall protection structure

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS642339A (en) * 1987-06-24 1989-01-06 Nec Corp Manufacture of semiconductor device
JPH10209163A (ja) * 1997-01-21 1998-08-07 Citizen Watch Co Ltd 半導体装置およびその製造方法
JP3654485B2 (ja) * 1997-12-26 2005-06-02 富士通株式会社 半導体装置の製造方法
KR100804444B1 (ko) * 2000-08-31 2008-02-20 에이제토 엘렉토로닉 마티리알즈 가부시키가이샤 패턴화된 폴리실라잔 막의 형성방법 및 감광성 폴리실라잔도막의 소성방법
US6734568B2 (en) * 2001-08-29 2004-05-11 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20050274871A1 (en) * 2004-06-10 2005-12-15 Jin Li Method and apparatus for collecting photons in a solid state imaging sensor
US20070238222A1 (en) * 2006-03-28 2007-10-11 Harries Richard J Apparatuses and methods to enhance passivation and ILD reliability
JP4768491B2 (ja) * 2006-03-30 2011-09-07 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP4247690B2 (ja) * 2006-06-15 2009-04-02 ソニー株式会社 電子部品及その製造方法
JP2011091087A (ja) * 2009-10-20 2011-05-06 Fujitsu Ltd 半導体装置とその製造方法
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US9018758B2 (en) * 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
WO2012107971A1 (ja) * 2011-02-10 2012-08-16 パナソニック株式会社 半導体装置及びその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06322318A (ja) * 1991-04-22 1994-11-22 Dow Corning Corp セラミック塗料及びその塗膜形成方法
US20110285011A1 (en) * 2010-05-18 2011-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with l-shaped non-metal sidewall protection structure

Also Published As

Publication number Publication date
EP2915191A1 (en) 2015-09-09
KR20150082395A (ko) 2015-07-15
CN104769711B (zh) 2018-06-01
US20140124877A1 (en) 2014-05-08
CN104769711A (zh) 2015-07-08
WO2014070926A1 (en) 2014-05-08
EP2915191B1 (en) 2020-04-15

Similar Documents

Publication Publication Date Title
JP5537341B2 (ja) 半導体装置
JP2016500930A (ja) 無機カラーを含む導電性インターコネクト
TWI720371B (zh) 半導體裝置及其製作方法
CN101950728B (zh) 金属柱凸块结构及其形成方法
KR102412613B1 (ko) 반도체 패키지 및 이의 제조 방법
CN102148201A (zh) 半导体元件、封装结构、及半导体元件的形成方法
CN103066051A (zh) 封装基板及其制作工艺、半导体元件封装结构及制作工艺
CN114586145B (zh) 凸起结构的形成
CN101183668A (zh) 电解电镀形成突起电极的半导体装置及其制造方法
CN103632985A (zh) 制造裸片的金属垫片结构的方法、裸片配置和芯片配置
US9159685B2 (en) Conductive structure and method for forming the same
KR101926713B1 (ko) 반도체 패키지 및 그 제조방법
CN101567355A (zh) 半导体封装基板及其制法
KR100874588B1 (ko) 전기적 특성 평가가 가능한 플립칩 및 이것의 제조 방법
TW201143000A (en) Chip bump structure and method for forming chip bump structure
JP5091962B2 (ja) 半導体装置
KR20210012557A (ko) 반도체 패키지 및 이를 포함하는 반도체 모듈
TW201432870A (zh) 包含無機套環之導電互連
CN103199070A (zh) 具有钝化区段的半导体元件及其制造方法
CN115735270A (zh) 基板键合方法
JP2011091087A (ja) 半導体装置とその製造方法
JP2008244218A (ja) 半導体装置
CN104681530B (zh) 半导体结构及其制造方法
KR102157877B1 (ko) 반도체 패키지
KR20260007198A (ko) 플립-칩 범핑 금속 층 및 범프 구조물

Legal Events

Date Code Title Description
A529 Written submission of copy of amendment under article 34 pct

Free format text: JAPANESE INTERMEDIATE CODE: A529

Effective date: 20150423

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161003

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20161003

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170516

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170529

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170829

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20180205