CN104769711B - 包括无机套环的导电互连 - Google Patents

包括无机套环的导电互连 Download PDF

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Publication number
CN104769711B
CN104769711B CN201380057472.4A CN201380057472A CN104769711B CN 104769711 B CN104769711 B CN 104769711B CN 201380057472 A CN201380057472 A CN 201380057472A CN 104769711 B CN104769711 B CN 104769711B
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conductive
layer
inorganic
interconnection
lantern ring
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CN104769711A (zh
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Y·孙
L·赵
M·韩
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Qualcomm Inc
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Qualcomm Inc
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Abstract

一种导电互连(340、440、540、640)包括导电支承层(330、430、530、630)，在该导电支承层(330、430、530、630)上的导电材料(320、520、620)，以及部分地包围该导电材料(320、520、620)的无机套环(350、450、550、650)。无机套环(350、450、550、650)也被布置在导电支承层(330、430、530、630)的侧壁上。一种制造导电互连(340、440、540、640)的方法包括在籽晶层(304、504)上制造导电材料(320、520、620)，形成有机套环(310、510)以部分地包围该导电材料(320、520、620)，蚀刻导电籽晶层(304、504)以形成导电支承层(330、430、530、630)，以及进行加热以将有机套环(310、510)转变为无机套环(350、450、550、650)，该无机套环(350、450、550、650)部分地包围导电材料(320、520、620)并布置在导电支承层(330、430、530、630)的侧壁上。有机套环(310、510)可通过在导电材料(320、520、620)上沉积光敏旋涂电介质材料并图案化该光敏旋涂电介质材料来形成。导电材料(620)可以是单个导电材料(320)或者可包括由势垒层分隔的第一导电层(332)和第二导电层(324)的堆叠，在这种情况下加热步骤还导致导电材料堆叠中的第二导电层(324)的回流。

Description

包括无机套环的导电互连
相关申请的交叉引用
本申请按照35U.S.C.§119(e)要求于2012年11月2日以Sun等人的名义提交的美国临时专利申请No.61/721,889的权益，其公开内容通过援引全部明确纳入于此。
背景
领域
本公开一般涉及半导体器件组装。本公开尤其涉及导电互连，该导电互连包括用于在籽晶层蚀刻期间保护该导电互连并在芯片附连期间防止焊桥的无机套环。
背景
在倒装芯片封装中，集成电路(IC)(例如，管芯)的有源器件区域在面对封装基板(例如，向下)的表面上。在该布置中，来自IC的互连(诸如柱)可以与封装基板上的接触焊盘电耦合。柱可以是铜、锡焊料或银焊料。铜柱可根据镀覆方法(例如，如图1所示)来制造。
如图1所示，用于制造铜柱120的电镀方法100包括在半导体晶片或管芯(例如，半导体基板)102上沉积导电籽晶层104(例如，金属)的第一工艺。如本文所述的，术语“半导体基板”可指代已切割晶片的基板或可指代尚未切割的晶片的基板。在第二工艺中，在导电籽晶层104上沉积和图案化光阻材料110。接着，电镀工艺形成铜柱120。可使用电镀工艺生长铜层122和焊料层124(例如，银(Ag)、锡(Sn)、铟(In)或镍(Ni))来形成铜柱120。然后剥离光阻材料110。
电镀方法100包括籽晶层蚀刻以移除各柱120之间的导电籽晶层104的各部分以形成凸块下导电层130。该蚀刻可以是在所有方向上移除导电籽晶层104的各向异性蚀刻。移除各柱120之间的导电籽晶层104防止导致错误互连操作的铜柱120的短路。遗憾的是，蚀刻工艺还过度蚀刻铜层122以形成底切126。底切126减少铜柱120在半导体基板102上的接触面积。减少的接触面积可使得铜柱120的连通性以及完整性降级。
在该示例中，底切126在铜柱120的每一侧上可以在三(3)微米的范围内。制造场所(例如，铸造厂)的当前控制极限是在铜柱120的凸块互连的每一侧上小于六微米的底切。当凸块直径是例如小于六十微米时，该底切量是相当大的。以此尺寸，六微米的过度蚀刻可导致铜柱120损耗10％到20％。结果，制造细间距/尺寸设计的铜柱120由于铜过度蚀刻而具有挑战性。在蚀刻后，热处理使得铜柱120的焊料层124回流。结果，表面张力导致圆形的焊料层124。
用于防止对铜柱120的铜层122的底切126的常规解决方案包括改变蚀刻工艺以减少底切126的量。然而，改变蚀刻工艺涉及开发新蚀刻机制的基础工艺改变。另一常规解决方案是增加铜柱120的凸块直径，例如如图2所示。
图2解说了用于将半导体基板(例如，IC管芯/芯片、倒装芯片)202(例如，IC器件)附连到封装基板260或另一半导体基板的芯片附连工艺200。注意，图2示出半导体基板202面朝下，而图1的半导体基板102面朝上取向。在该示例中，铜柱220的焊料凸块224及铜层222的凸块直径增加。然而，凸块直径的这一增加受到凸块间距204的限制。当各焊料凸块224之间(或者焊料凸块224和迹线(未示出)之间)的间隙(例如，凸块间距204)由于增加的凸块直径而减少时，在倒装芯片组装期间用以将铜柱220的焊料凸块224耦合到封装基板260的接触焊盘262的热处理之后产生焊桥226。即，用以耦合接触焊盘262与铜柱220的焊料凸块224的倒装芯片回流导致各焊料凸块224之间的焊桥226。
概述
根据本公开的一方面，描述了包括无机套环的导电互连。导电互连包括导电支承层。导电互连还包括导电支承层上的导电材料。导电互连进一步包括部分地包围导电材料的无机套环。无机套环还被布置在导电支承层的侧壁上。
根据本公开的另一方面，描述了用于制造包括无机套环的导电互连的方法。该方法包括在导电籽晶层上制造导电材料。该方法还包括形成有机套环以部分地包围导电材料。该方法还包括加热导电互连以将有机套环转变为部分地包围导电材料的无机套环。无机套环还通过加热导电互连而被布置在导电支承层的侧壁上。
根据本公开的另一方面，描述了包括无机套环的导电互连。导电互连包括导电支承层上的导电材料。导电互连还包括用于保护导电互连的导电材料和导电支承层的装置。
这已较宽泛地勾勒出本公开的特征和技术优势以便下面的详细描述可以被更好地理解。本公开的其他特征和优点将在下文描述。本领域技术人员应该领会，本公开可容易地被用作修改或设计用于实施与本公开相同的目的的其他结构的基础。本领域技术人员还应认识到，这样的等效构造并不脱离所附权利要求中所阐述的本公开的教导。被认为是本公开的特性的新颖特征在其组织和操作方法两方面连同进一步的目的和优点在结合附图来考虑以下描述时将被更好地理解。然而，要清楚理解的是，提供每一幅附图均仅用于解说和描述目的，且无意作为对本公开的限定的定义。
附图简述
在结合附图理解下面阐述的详细描述时，本公开的特征、本质和优点将变得更加明显，在附图中，相同附图标记始终作相应标识。
图1是解说用于制造铜柱的常规镀覆方法的框图。
图2是解说其中形成焊桥的用于将倒装芯片附连到封装基板的常规组装工艺的框图。
图3是解说根据本公开的一方面的用于制造包括无机套环的导电互连的镀覆方法的框图，并且进一步解说了包括无机套环的导电互连的示例性实施例。
图4是解说根据本公开的一方面的用于使用导电互连来将倒装芯片附连到封装基板的组装工艺的框图，并且进一步解说了包括具有无机套环的导电互连的倒装芯片封装的示例性实施例。
图5是解说根据本公开的另一方面的用于制造包括无机套环的导电互连的镀覆方法的框图，并且进一步解说了包括被无机套环包围的单个导电材料的导电互连的示例性实施例。
图6是解说根据本公开的另一方面的用于使用导电互连将倒装芯片附连到封装基板的组装工艺的框图，并且进一步解说了包括具有无机套环的导电互连的倒装芯片封装的示例性实施例。
图7是解说根据本公开的一个方面的用于制造包括无机套环的导电互连的方法的框图。
图8是解说其中可有利地采用本公开的包括无机套环的导电互连的示例性无线通信系统的框图。
详细描述
以下结合附图阐述的详细描述旨在作为各种配置的描述，而无意表示可实践本文中所描述的概念的仅有的配置。本详细描述包括具体细节以便提供对各种概念的透彻理解。然而，对于本领域技术人员将显而易见的是，没有这些具体细节也可实践这些概念。在一些实例中，以框图形式示出众所周知的结构和组件以避免湮没此类概念。如本文所述的，术语“和/或”的使用旨在代表“可兼性或”，而术语“或”的使用旨在代表“排他性或”。
本申请的各方面提供了用于改进集成电路(IC)器件(例如，倒装芯片器件或微机电系统(MEMS)器件)的组装的解决方案。例如，如图1和2所示，执行用于移除导电籽晶层104的各向异性蚀刻以防止各铜柱120之间的短路。遗憾的是，蚀刻工艺还过度蚀刻柱120的铜层122和导电籽晶层104以形成底切126。此外，底切126减少铜柱120在半导体基板102上的接触面积。减少的接触面积可使得铜柱120的连通性以及完整性降级。
用于防止对铜层122的底切126的常规解决方案包括改变蚀刻工艺以减少底切126的量。然而，改变蚀刻工艺涉及开发出新蚀刻机制的基础工艺改变。另一常规解决方案是增加铜柱的凸块直径，例如如图2所示。然而，增加凸块直径受到凸块间距204的限制。当各焊料凸块224之间的间隙(例如，凸块间距204)由于增加的凸块直径而减少时，在倒装芯片组装期间用以将铜柱220的焊料凸块224耦合到封装260的接触焊盘262的热处理之后产生焊桥226。
本公开的一个方面提供了用于在籽晶层蚀刻期间保护导电互连的无机套环。无机套环还防止在芯片附连期间形成焊桥。图3是解说根据本公开的一个方面的用于制造包括无机套环350的导电互连340的镀覆方法300的框图。
如图3所示，可以使用图1的常规工艺在沉积在半导体基板(晶片或管芯)302的导电籽晶层304上形成导电材料堆叠320。在一种配置中，导电材料堆叠320被用来在剥离光阻材料后形成导电互连。可使用电镀工艺生长第一导电层322和第二导电层324(例如被布置为导电柱)来形成导电材料堆叠320。第一导电层322可包括但不限于铜(Cu)、硒(Se)、镍(Ni)、金(Au)或将不会在热处理(例如，回流)期间熔化的其他类似镀覆金属。第二导电层324可包括但不限于钍(Th)、铟(In)、铋(Bi)、铅(Pb)、锡(Sn)和/或银(Ag)或将在热处理(例如，回流)期间熔化的其他类似镀覆金属或合金。
在本公开的另一方面，可以在第一导电层322和第二导电层324之间沉积势垒层(未示出)。第一导电层322的厚度可以在几微米到几百微米的范围内。第二导电层324的厚度可以在几微米到几百微米的范围内。接着，可以在导电籽晶层304和导电材料堆叠320上涂敷有机旋涂电介质材料306。在一种配置中，有机旋涂电介质材料306是在热处理后从有机材料转变为无机材料的光敏旋涂电介质材料。示例材料是来自安智电子材料(AZElectronic Materials)的光敏旋涂电介质(PSOD)。
如图3进一步所示，有机旋涂电介质材料306使用例如光刻工艺来图案化以形成有机套环310。有机套环310的厚度可以在几百纳米到几微米的范围内。接着，蚀刻导电籽晶层304以形成导电支承层330。该工艺可使用在所有方向上移除导电籽晶层304的各向异性蚀刻来执行，因为导电籽晶层304的过多的剩余部分可导致错误的互连操作。然而，在该实施例中，有机套环310保护导电材料堆叠320中的第一导电层322以及导电支承层330免遭图1所示的过度蚀刻。最后，执行热处理以使得导电材料堆叠320的第二导电层324回流以形成导电互连340。表面张力导致圆形的第二导电层324。替代实施例在图5和6中示出，其中单个导电材料520/620替换导电材料堆叠320。
在一种配置中，热处理导致有机套环310的旋涂电介质材料306从有机材料转变为无机材料，其成分可类似于例如二氧化硅(SiO2)。在该配置中，该无机材料形成部分地包围导电互连340的无机套环350。在本公开的一方面，无机套环350由在热处理期间呈现热交联反应的可固化无机材料(包括硅)制成。结果，用于形成无机套环350的热处理导致旋涂电介质材料306在固化成无机套环350之前流到导电支承层330的侧壁上。
在本公开的一方面，热处理期间的热交联反应导致有机套环310的旋涂电介质材料306流到导电籽晶层304上。在本公开的这一方面，热交联反应是将旋涂电介质材料306的较小分子联接成形成无机套环350的固化的固体物质的大型网络的化学反应。即，热处理可导致旋涂电介质材料306流到导电支承层330的侧壁上。
此外，无机套环350具有良好的热传导性。包括导电互连340的半导体基板302可被组装到集成电路(IC)器件封装中。在该配置中，与导电互连340周围的其他有机材料(诸如，所组装的封装的填料和/或模塑料)相比，无机套环350提供了改进的散热路径。由此，热通过导电互连340的无机套环350容易地散逸。另外，无机套环350能够耐受高温。
图4是解说根据本公开的一方面的用于使用导电互连440来将半导体基板(例如，IC器件，诸如倒装芯片器件或MEMS器件)402附连到封装基板460的组装工艺400的框图。在该配置中，半导体基板402包括由图3所示的工艺形成的且隔开一距离(例如，互连间距406)的导电互连440。代表性地，导电互连440包括在导电支承层430上形成的且被无机套环450包围的第一导电层422和第二导电层424的导电材料堆叠。在回流后，导电互连440的第二导电层424耦合到封装基板460的接触焊盘462。
在本公开的这方面，无机套环450的使用在籽晶层蚀刻期间保护导电互连440中的第一导电层422的成分，以消除或减少对第一导电层422的任何底切。保护第一导电层422的成分可提高极低K(ELK)稳健性并改善导电互连440的互连疲劳寿命。另外，无机套环450防止图2所示的焊桥问题。消除焊桥问题使得能够进一步减少互连间距406以支持器件(诸如微机电系统(MEMS)器件以及倒装芯片器件)的细间距/尺寸设计。此外，消除底切维持导电互连440的第一导电层422的直径以便提供导电互连440至半导体基板402的增加的接触面积。增加的接触面积可改进导电互连440的连通性以及完整性。
图5是解说根据本公开的另一方面的用于制造包括无机套环550的导电互连540的镀覆方法500的框图。导电互连540的示例性实施例由半导体基板502支承。导电互连540包括包围单个导电材料520以及导电支承层530的侧壁的无机套环550。
如图5所示，图1的常规工艺可用于形成光阻图案508。在步骤3中，在光阻图案508内且在沉积在半导体基板(晶片或管芯)502上的导电籽晶层504上电镀单个导电材料520。在步骤4中，光阻图案508被剥离以暴露单个导电材料520和导电籽晶层504。步骤5到7类似于图3中的步骤5到7，但是提供单个导电材料520以代替导电材料堆叠520。如步骤8所示，导电互连540包括单个导电材料520，该单个导电材料在用以形成无机套环550的热处理期间不回流。热处理导致旋涂电介质材料506在固化成无机套环550之前流到导电支承层530的侧壁上，以完成导电互连540的形成，如步骤8所示。
图6是解说根据本公开的一方面的用于使用导电互连640来将半导体基板(例如，IC器件，诸如倒装芯片器件或MEMS器件)602附连到封装基板660的组装工艺600的框图。在该配置中，半导体基板602包括由图5所示的工艺形成的且隔开一距离(例如，互连间距606)的导电互连640。代表性地，导电互连640包括在导电支承层630上形成的且被无机套环650包围的单个导电材料620。在该配置中，导电互连640的单个导电材料620可使用热压接合或用于施加足够量的热和压力以与导电焊盘662耦合的其他类似工艺来直接接合到导电焊盘662。在热压接合后，导电互连640中的单个导电材料620耦合到导电焊盘662以将半导体基板602联接到封装基板660。
图7是解说根据本公开的一个方面的用于制造包括无机套环的导电互连的方法700的框图。在框710中，在导电籽晶层上制造导电材料。例如，如图3所示，在沉积在半导体基板302上的导电籽晶层304上形成导电材料堆叠320。在一种配置中，导电材料堆叠320被用来在剥离光阻材料后形成导电互连。可使用电镀工艺生长第一导电层322(例如，铜(Cu)、硒(Se)、镍(Ni)、金(Au))和第二导电层324(例如，钍(Th)、铟(In)、铋(Bi)、铅(Pb)、锡(Sn)和/或银(Ag))来形成导电材料堆叠320。或者，在沉积在半导体基板502上的导电籽晶层504上制造单个导电材料520，如图5所示。
在框712中，形成有机套环以部分地包围导电材料。例如，如图3所示，可以在导电籽晶层304和导电材料堆叠320上涂敷有机旋涂电介质材料306。使用例如光刻工艺来图案化有机旋涂电介质材料306以形成有机套环310。或者，在导电籽晶层504和单个导电材料520上涂敷有机旋涂电介质材料506。光刻工艺在单个导电材料520周围形成有机套环510，如图5所示。在框714，蚀刻导电籽晶层以形成导电支承层。例如，如图3所示，蚀刻导电籽晶层304以形成导电支承层330。如图5所示，蚀刻导电籽晶层504以形成导电支承层530。
再次参照图7，在框716中，导电互连受到热处理(即，加热)以将有机套环转变为部分地包围导电材料的无机套环。无机套环被布置在导电支承层的侧壁上。在图3所示的配置中，无机套环350由在热处理期间呈现热交联反应的可固化无机材料制成。结果，用于形成无机套环350的热处理导致旋涂电介质材料306在固化成无机套环350之前流到导电支承层330的侧壁上。
因此，图7的方法700可由以上参照图3和4描述的结构和组件来执行。或者，如图6所示，旋涂电介质材料506被涂敷到导电籽晶层504和单个导电材料520。使用例如光刻工艺来图案化有机旋涂电介质材料506以形成有机套环510。然后蚀刻导电籽晶层504以形成导电支承层530。热处理导致旋涂电介质材料506在固化成无机套环550之前流到导电支承层530的侧壁上，如图5所示。该替代方法可由参照图5和6描述的结构和组件来执行。
如所提及的，对于导电互连形成过程期间的导电材料而言，籽晶层蚀刻工艺期间对导电材料的蚀刻损耗是所关注的方面，例如如图3到7所示。方法700可以在籽晶层蚀刻工艺期间保护导电材料堆叠320的第一导电材料522或单个导电材料520。在剥离镀覆光阻材料后，在导电材料堆叠320或单个导电材料520上涂覆有机旋涂电介质材料306/506(例如，光敏旋涂电介质材料)。使用光刻工艺来图案化该电介质材料306/506以形成具有围绕导电材料堆叠320或单个导电材料520的套环结构(例如，有机套环310/510)的有机材料。在籽晶蚀刻期间，有机套环310/510可保护导电材料堆叠320或单个导电材料520免遭过度蚀刻。如图3所示，热处理使导电材料堆叠320中的第二导电层324回流以形成包括无机套环350的导电互连340。如图5所示，导电互连540包括单个导电材料520，该单个导电材料在用以形成无机套环550的热处理期间不回流。
在本公开的这方面，热处理导致旋涂电介质材料306/506从有机材料转变为无机材料，诸如二氧化硅(SiO2)。另外，热处理导致旋涂电介质材料306/506流到导电支承层330/530的侧壁上以形成无机套环350/550。围绕导电材料堆叠320的无机套环350还防止半导体芯片组装期间的焊桥问题。消除焊桥问题使得能够进一步减少互连间距以支持半导体器件的细间距/尺寸设计。此外，消除底切维持导电互连440/540的第一导电层422或单个导电材料520的直径。该配置提供了导电互连440/540到半导体基板402/502的增加的接触面积。增加的接触面积还改进了导电互连440/540的连通性以及完整性。
在一种配置中，导电互连包括导电支承层上的导电材料。导电互连还包括用于保护导电互连的导电材料和导电支承层的装置。该保护装置可部分地包围导电材料并且被布置在导电支承层的侧壁上。在一方面，该保护装置可以是被配置成执行由该保护装置所陈述的功能的无机套环350/450/550/650。在另一方面，前述装置可以是被配置成执行由前述装置所陈述的功能的任何组件或任何结构。
图8示出其中可有利地采用所公开的包括无机套环的导电互连的配置的示例性无线通信系统800。出于解说目的，图8示出了三个远程单元820、830和850以及两个基站840。将认识到，无线通信系统可具有多得多的远程单元和基站。远程单元820、830和850分别包括导电互连825A、825B和825C。图8示出了从基站840到远程单元820、830、和850的前向链路信号880，以及从远程单元820、830、和850到基站840的反向链路信号890。
在图8中，远程单元820被示为移动电话，远程单元830被示为便携式计算机，而远程单元850被示为无线本地环路系统中的位置固定的远程单元。例如，远程单元可以是蜂窝电话、手持式个人通信系统(PCS)单元、机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、便携式数据单元(诸如个人数据助理)、或者位置固定的数据单元(诸如仪表读数装备)。尽管图8解说了可采用根据本公开的教导的导电互连的远程单元，但本公开并不限于所解说的这些示例性单元。例如，根据本公开的配置的导电互连可被合适地用在任何器件中。
尽管已阐述了特定电路系统，但是本领域技术人员应当领会，并非所有所公开的电路系统都是实践所公开的配置所必需的。此外，某些众所周知的电路未被描述，以便保持专注于本公开。类似地，尽管使用相对术语“上”和“下”，但这些术语是非限制性的。例如，如果器件旋转90度，则术语“上”和“下”将指代“最左”和“最右”部。
本领域技术人员将进一步领会，结合本文公开所描述的各种解说性逻辑框、模块、电路、和算法步骤可被实现为电子硬件、计算机软件、或两者的组合。为清楚地解说硬件与软件的这一可互换性，各种解说性组件、块、模块、电路、和步骤在上面是以其功能性的形式作一般化描述的。此类功能性是被实现为硬件还是软件取决于具体应用和施加于整体系统的设计约束。技术人员可针对每种特定应用以不同方式来实现所描述的功能性，但此类实现决策不应被解读为致使脱离本发明的范围。
结合本文公开描述的方法或算法的步骤可直接在硬件中、在由处理器执行的软件模块中、或在这两者的组合中实施。
本文中所描述的方法体系取决于应用可藉由各种组件来实现。例如，这些方法体系可在硬件、固件、软件、或者其任何组合中实现。对于硬件实现，这些处理单元可以在一个或多个专用集成电路(ASIC)、数字信号处理器(DSP)、数字信号处理器件(DSPD)、可编程逻辑器件(PLD)、现场可编程门阵列(FPGA)、处理器、控制器、微控制器、微处理器、电子器件、设计成执行本文中所描述功能的其他电子单元、或者其组合内实现。
对于固件和/或软件实现，这些方法体系可以用执行本文所描述功能的模块(例如，规程、函数等等)来实现。任何有形地实施指令的机器可读介质可被用来实现本文所描述的方法体系。例如，软件代码可被存储在存储器中并由处理器单元来执行。存储器可以在处理器单元内或在处理器单元外部实现。如本文中所使用的，术语“存储器”是指任何类型的长期、短期、易失性、非易失性、或其他存储器，并且不被限定于任何特定类型或数目个存储器、或任何类型的其上存储有存储器的介质。
如果以固件和/或软件实现，则功能可作为一条或多条指令或代码存储在计算机可读介质上。示例包括编码有数据结构的计算机可读介质和编码有计算机程序的计算机可读介质。计算机可读介质包括物理计算机存储介质。存储介质可以是能被计算机访问的任何可用介质。作为示例而非限定，此类计算机可读介质可包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储或其他磁存储设备、或能被用来存储指令或数据结构形式的期望程序代码且能被计算机访问的任何其他介质；如本文中所使用的盘(disk)和碟(disc)包括压缩碟(CD)、激光碟、光碟、数字多用碟(DVD)、软盘和蓝光碟，其中盘常常磁学地再现数据，而碟用激光光学地再现数据。上述的组合应当也被包括在计算机可读介质的范围内。
除了存储在计算机可读介质上，指令和/或数据还可作为包括在通信装置中的传输介质上的信号来提供。例如，通信装置可包括具有指示指令和数据的信号的收发机。这些指令和数据被配置成使一个或多个处理器实现权利要求中叙述的功能。
尽管已详细描述了本公开及其优势，但是应当理解，可在本文中作出各种改变、替代和变更而不会脱离如由所附权利要求所定义的本公开的技术。例如，诸如“上方”和“下方”之类的关系术语是关于基板或电子器件使用的。当然，如果该基板或电子器件被颠倒，则上方变成下方，反之亦然。此外，如果是侧面取向的，则上方和下方可指代基板或电子器件的侧面。此外，本申请的范围无意被限定于说明书中所描述的过程、机器、制造、物质组成、装置、方法和步骤的特定实施例。如本领域的普通技术人员将容易从本公开领会到的，可以利用根据本公开的现存或今后开发的与本文所描述的相应实施例执行基本相同的功能或实现基本相同结果的过程、机器、制造、物质组成、装置、方法或步骤。因此，所附权利要求旨在将这样的过程、机器、制造、物质组成、装置、方法或步骤包括在其范围内。

Claims (21)

1.一种导电互连，包括：
半导体基板上的导电支承层；
所述导电支承层上的导电材料；以及
无机套环，所述无机套环部分地包围所述导电材料，被布置在所述导电支承层的侧壁上，并且直接与所述半导体基板接触，其中所述无机套环被配置成在蚀刻导电籽晶层以形成所述导电支承层期间保护所述导电支承层和所述导电材料免受过度蚀刻，其中所述无机套环由被配置成响应于热处理而变成无机的一种类型的光敏旋涂介电材料制成。
2.如权利要求1所述的导电互连，其特征在于，所述无机套环包括二氧化硅。
3.如权利要求1所述的导电互连，其特征在于，所述无机套环由在热处理后转变为无机材料的一种类型的有机材料制成。
4.如权利要求1所述的导电互连，其特征在于，所述导电互连耦合到封装基板的接触焊盘。
5.如权利要求1所述的导电互连，其特征在于，所述导电材料包括被布置为导电柱的导电材料堆叠。
6.如权利要求1所述的导电互连，其特征在于，所述半导体基板用于微机电系统(MEMS)器件。
7.如权利要求1所述的导电互连，其特征在于，所述半导体基板用于倒装芯片器件。
8.如权利要求1所述的导电互连，其特征在于，所述导电互连被集成到机顶盒、娱乐单元、导航设备、手持式个人通信系统(PCS)单元、便携式数据单元和/或固定位置数据单元中。
9.如权利要求1所述的导电互连，其特征在于，所述导电互连被集成到移动电话、音乐播放器、视频播放器、和/或计算机中。
10.一种制造导电互连的方法，包括：
在半导体基板上沉积导电籽晶层；
在所述导电籽晶层上制造导电材料；
形成有机套环以部分地包围所述导电材料；
蚀刻所述导电籽晶层以形成导电支承层；以及
加热所述导电互连以将所述有机套环转变为部分地包围所述导电材料的无机套环，其中所述无机套环被布置在所述导电支承层的侧壁上并且直接与所述半导体基板接触。
11.如权利要求10所述的方法，其特征在于，形成所述有机套环包括：
在所述导电材料上沉积光敏旋涂电介质材料；以及
图案化所述光敏旋涂电介质材料。
12.如权利要求10所述的方法，其特征在于，形成所述导电籽晶层包括在所述半导体基板上沉积所述导电籽晶层。
13.如权利要求10所述的方法，其特征在于，制造所述导电材料包括：
在所述导电支承层上沉积第一导电层；
在所述第一导电层上沉积第二导电层；以及
在所述第一导电层和所述第二导电层之间沉积势垒层以形成导电材料堆叠。
14.如权利要求13所述的方法，其特征在于，进一步包括在所述加热期间使所述导电材料堆叠的第二导电层回流。
15.如权利要求10所述的方法，其特征在于，进一步包括：将所述导电互连集成到机顶盒、娱乐单元、导航设备、手持式个人通信系统(PCS)单元、便携式数据单元和/或位置固定的数据单元中。
16.如权利要求10所述的方法，其特征在于，进一步包括：将所述导电互连集成到移动电话、音乐播放器、视频播放器、和/或计算机中。
17.一种导电互连，包括：
在半导体基板上形成的导电支承层上的导电材料；以及
用于在蚀刻导电籽晶层以形成所述导电支承层期间保护所述导电材料和所述导电支承层免受过度蚀刻的装置，所述装置包围所述导电材料、被布置在所述导电支承层的侧壁上、并且直接与所述半导体基板接触，其中所述装置由被配置成响应于热处理而变成无机的一种类型的光敏旋涂介电材料制成。
18.如权利要求17所述的导电互连，其特征在于，所述导电材料包括被布置为导电柱的导电材料堆叠。
19.如权利要求18所述的导电互连，其特征在于，所述导电材料堆叠包括含铜(Cu)、硒(Se)、镍(Ni)和/或金(Au)的第一导电层、含钍(Th)、铟(In)、铋(Bi)、铅(Pb)、锡(Sn)和/或银(Ag)的第二导电层，以及在所述第一导电层和所述第二导电层之间的势垒层。
20.如权利要求17所述的导电互连，其特征在于，所述导电互连被集成到机顶盒、娱乐单元、导航设备、手持式个人通信系统(PCS)单元、便携式数据单元和/或固定位置数据单元中。
21.如权利要求17所述的导电互连，其特征在于，所述导电互连被集成到移动电话、音乐播放器、视频播放器、和/或计算机中。
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