JP2016224089A5 - - Google Patents

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Publication number
JP2016224089A5
JP2016224089A5 JP2015107066A JP2015107066A JP2016224089A5 JP 2016224089 A5 JP2016224089 A5 JP 2016224089A5 JP 2015107066 A JP2015107066 A JP 2015107066A JP 2015107066 A JP2015107066 A JP 2015107066A JP 2016224089 A5 JP2016224089 A5 JP 2016224089A5
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JP
Japan
Prior art keywords
image processing
processing circuit
clock
signal
spread
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Application number
JP2015107066A
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English (en)
Japanese (ja)
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JP6351542B2 (ja
JP2016224089A (ja
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Priority to JP2015107066A priority Critical patent/JP6351542B2/ja
Priority claimed from JP2015107066A external-priority patent/JP6351542B2/ja
Priority to US15/156,510 priority patent/US9984613B2/en
Publication of JP2016224089A publication Critical patent/JP2016224089A/ja
Publication of JP2016224089A5 publication Critical patent/JP2016224089A5/ja
Priority to US15/964,233 priority patent/US20180247583A1/en
Application granted granted Critical
Publication of JP6351542B2 publication Critical patent/JP6351542B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2015107066A 2015-05-27 2015-05-27 回路基板、および表示装置 Active JP6351542B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2015107066A JP6351542B2 (ja) 2015-05-27 2015-05-27 回路基板、および表示装置
US15/156,510 US9984613B2 (en) 2015-05-27 2016-05-17 Substrate and display apparatus
US15/964,233 US20180247583A1 (en) 2015-05-27 2018-04-27 Substrate and display apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015107066A JP6351542B2 (ja) 2015-05-27 2015-05-27 回路基板、および表示装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2018106247A Division JP2018132785A (ja) 2018-06-01 2018-06-01 回路基板、および表示装置

Publications (3)

Publication Number Publication Date
JP2016224089A JP2016224089A (ja) 2016-12-28
JP2016224089A5 true JP2016224089A5 (enExample) 2018-04-12
JP6351542B2 JP6351542B2 (ja) 2018-07-04

Family

ID=57397601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015107066A Active JP6351542B2 (ja) 2015-05-27 2015-05-27 回路基板、および表示装置

Country Status (2)

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US (2) US9984613B2 (enExample)
JP (1) JP6351542B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018092884A1 (ja) 2016-11-17 2018-05-24 三菱ケミカル株式会社 （メタ）アクリル系共重合体、塗料組成物、塗装物及び複層塗膜の形成方法
JP2018132785A (ja) * 2018-06-01 2018-08-23 キヤノン株式会社 回路基板、および表示装置
US10892794B1 (en) * 2020-02-06 2021-01-12 Global Unichip Corporation Multi-channel transmission device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000193934A (ja) * 1998-12-28 2000-07-14 Toshiba Corp 表示装置
JP4040357B2 (ja) * 2002-05-10 2008-01-30 シャープ株式会社 クロック伝送装置およびそれを用いる画像形成装置
JP2006058799A (ja) * 2004-08-24 2006-03-02 Fuji Electric Device Technology Co Ltd 表示装置駆動用集積回路
JP2006171080A (ja) * 2004-12-13 2006-06-29 Toshiba Matsushita Display Technology Co Ltd 回路基板および液晶表示装置
JP2008216606A (ja) 2007-03-05 2008-09-18 Sharp Corp 表示装置の駆動方法、表示装置およびテレビジョン受像機
DE102008053670A1 (de) * 2008-10-29 2010-05-12 Texas Instruments Deutschland Gmbh Vorrichtung und Verfahren zur Erzeugung von Taktsignalen für Gleichspannungswandler
WO2011027623A1 (ja) * 2009-09-04 2011-03-10 エヌ・ティ・ティ・アドバンステクノロジ株式会社 情報漏洩防止装置および方法
US8412974B2 (en) * 2009-11-13 2013-04-02 International Business Machines Corporation Global synchronization of parallel processors using clock pulse width modulation
WO2015012002A1 (ja) * 2013-07-23 2015-01-29 株式会社リキッド・デザイン・システムズ 配線長測定装置及び記録媒体

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