SG11201803662SA - Method for synchronising data converters by means of a signal transmitted from one to the next - Google Patents

Method for synchronising data converters by means of a signal transmitted from one to the next

Info

Publication number
SG11201803662SA
SG11201803662SA SG11201803662SA SG11201803662SA SG11201803662SA SG 11201803662S A SG11201803662S A SG 11201803662SA SG 11201803662S A SG11201803662S A SG 11201803662SA SG 11201803662S A SG11201803662S A SG 11201803662SA SG 11201803662S A SG11201803662S A SG 11201803662SA
Authority
SG
Singapore
Prior art keywords
converters
synchronizing
converter
clock
signal transmitted
Prior art date
Application number
SG11201803662SA
Inventor
Etienne Bouin
Rémi Laube
Jérôme Ligozat
Marc Stackler
Original Assignee
Teledyne E2V Semiconductors Sas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teledyne E2V Semiconductors Sas filed Critical Teledyne E2V Semiconductors Sas
Publication of SG11201803662SA publication Critical patent/SG11201803662SA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/00267—Layout of the delay element using circuits having two logic levels using D/A or A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing

Abstract

METHOD FOR SYNCHRONIZING DATA CONVERTERS BY MEANS OF A SIGNAL TRANSMITTED FROM ONE TO THE NEXT 5 In an architecture for processing da ta comprising a control unit and converters CNj to be synchronized to an active front of a common reference clock CLK, the synchronizing method make s provision for the converters to be arranged in at least one series chain, and for a procedure for 10 synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronizati on to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configurati on register REG c ontaining at least 15 one polarity parameter Sel-edge j that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shift j furthermore allows the phase of the sampling clocks of n converting core s of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock 20 frequency, to be synchronized. Figure 1 25
SG11201803662SA 2015-11-10 2016-11-04 Method for synchronising data converters by means of a signal transmitted from one to the next SG11201803662SA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1560739A FR3043477B1 (en) 2015-11-10 2015-11-10 METHOD FOR SYNCHRONIZING DATA CONVERTERS BY A SIGNAL TRANSMITTED FROM CLOSE TO NEAR
PCT/EP2016/076689 WO2017080925A1 (en) 2015-11-10 2016-11-04 Method for synchronising data converters by means of a signal transmitted from one to the next

Publications (1)

Publication Number Publication Date
SG11201803662SA true SG11201803662SA (en) 2018-06-28

Family

ID=55361644

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201803662SA SG11201803662SA (en) 2015-11-10 2016-11-04 Method for synchronising data converters by means of a signal transmitted from one to the next

Country Status (11)

Country Link
US (1) US10320406B2 (en)
EP (1) EP3375092B1 (en)
JP (1) JP6898319B2 (en)
KR (1) KR102559701B1 (en)
CN (1) CN108352829B (en)
AU (1) AU2016354402B2 (en)
CA (1) CA3004791C (en)
FR (1) FR3043477B1 (en)
SG (1) SG11201803662SA (en)
TW (1) TWI690161B (en)
WO (1) WO2017080925A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
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JP7193110B2 (en) * 2018-07-27 2022-12-20 ザインエレクトロニクス株式会社 Multi-lane serializer device
FR3094593B1 (en) * 2019-03-29 2021-02-19 Teledyne E2V Semiconductors Sas Method of synchronizing digital data sent in series
FR3100068B1 (en) * 2019-08-20 2021-07-16 Teledyne E2V Semiconductors Sas Method for synchronizing analog data at the output of a plurality of digital / analog converters
CN110445492B (en) * 2019-09-09 2023-04-07 Oppo广东移动通信有限公司 Cross-clock-domain frequency division clock protection circuit, frequency division circuit, method and terminal equipment
FR3111249B1 (en) 2020-06-09 2023-12-22 Teledyne E2V Semiconductors Sas Method for synchronizing analog-digital or digital-analog type converters, and corresponding system.
CN113381831A (en) * 2021-05-12 2021-09-10 聚融医疗科技(杭州)有限公司 Multi-chip FPGA (field programmable Gate array) receiving and transmitting synchronization method and system and ultrasonic control equipment
FR3140231A1 (en) 2022-09-22 2024-03-29 Teledyne E2V Semiconductors Sas Method for determining the phase shift between a first clock signal received by a first electronic component and a second clock signal received by a second electronic component

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FR2746987A1 (en) 1996-03-29 1997-10-03 Philips Electronics Nv ANALOGUE / DIGITAL CONVERTER WITH HIGH SAMPLING FREQUENCY
JP2985957B1 (en) * 1998-09-11 1999-12-06 松下電器産業株式会社 Phase comparator and digital phase locked loop
JP3657188B2 (en) * 2000-10-31 2005-06-08 Ｎｅｃエレクトロニクス株式会社 Device and its operating method
JP2002232402A (en) * 2001-02-07 2002-08-16 Toyo Commun Equip Co Ltd Automatic phase inversion circuit for clock signal
US6836852B2 (en) * 2001-10-29 2004-12-28 Agilent Technologies, Inc. Method for synchronizing multiple serial data streams using a plurality of clock signals
DE102004050648A1 (en) 2004-10-18 2006-04-20 Rohde & Schwarz Gmbh & Co. Kg Arrangement for the synchronous output of analog signals generated in two or more digital / analog converters
US7328299B2 (en) * 2004-11-23 2008-02-05 Atmel Corporation Interface for compressed data transfer between host system and parallel data processing system
CN101098220B (en) * 2006-06-29 2010-08-18 中兴通讯股份有限公司 Digital phase-locked loop based clock synchronization method and system thereof
CN101546207B (en) * 2008-03-28 2011-08-10 盛群半导体股份有限公司 Clock signal switching circuit
KR20110033101A (en) * 2008-06-06 2011-03-30 엘에스아이 코포레이션 Systems and methods for synchronous, retimed analog to digital conversion
US7728753B2 (en) * 2008-10-13 2010-06-01 National Semiconductor Corporation Continuous synchronization for multiple ADCs
CN102495912B (en) * 2011-10-26 2013-11-20 电子科技大学 Multi-channel high-speed data acquisition system with synchronous correction function
JP2014017590A (en) * 2012-07-06 2014-01-30 Fujitsu Ltd Electronic circuit and communication method
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WO2015162763A1 (en) * 2014-04-24 2015-10-29 三菱電機株式会社 Network system
JP6213538B2 (en) * 2015-09-24 2017-10-18 横河電機株式会社 Signal processing circuit

Also Published As

Publication number Publication date
FR3043477A1 (en) 2017-05-12
CN108352829B (en) 2022-02-25
KR20180079339A (en) 2018-07-10
US20180323794A1 (en) 2018-11-08
TW201740683A (en) 2017-11-16
JP2018537031A (en) 2018-12-13
FR3043477B1 (en) 2017-11-24
EP3375092B1 (en) 2019-09-04
AU2016354402B2 (en) 2020-11-19
WO2017080925A1 (en) 2017-05-18
CA3004791C (en) 2023-12-12
TWI690161B (en) 2020-04-01
US10320406B2 (en) 2019-06-11
CA3004791A1 (en) 2017-05-18
AU2016354402A1 (en) 2018-06-21
JP6898319B2 (en) 2021-07-07
EP3375092A1 (en) 2018-09-19
CN108352829A (en) 2018-07-31
KR102559701B1 (en) 2023-07-25

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