JP2005039829A5 - - Google Patents

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Publication number
JP2005039829A5
JP2005039829A5 JP2004207325A JP2004207325A JP2005039829A5 JP 2005039829 A5 JP2005039829 A5 JP 2005039829A5 JP 2004207325 A JP2004207325 A JP 2004207325A JP 2004207325 A JP2004207325 A JP 2004207325A JP 2005039829 A5 JP2005039829 A5 JP 2005039829A5
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JP
Japan
Prior art keywords
clock
delay
signal processing
signal
delay time
Prior art date
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Pending
Application number
JP2004207325A
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English (en)
Japanese (ja)
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JP2005039829A (ja
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Publication date
Priority claimed from KR1020030047759A external-priority patent/KR100968564B1/ko
Application filed filed Critical
Publication of JP2005039829A publication Critical patent/JP2005039829A/ja
Publication of JP2005039829A5 publication Critical patent/JP2005039829A5/ja
Pending legal-status Critical Current

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JP2004207325A 2003-07-14 2004-07-14 信号処理装置及び方法 Pending JP2005039829A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030047759A KR100968564B1 (ko) 2003-07-14 2003-07-14 신호 처리 장치 및 방법

Publications (2)

Publication Number Publication Date
JP2005039829A JP2005039829A (ja) 2005-02-10
JP2005039829A5 true JP2005039829A5 (enExample) 2007-08-16

Family

ID=34114215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004207325A Pending JP2005039829A (ja) 2003-07-14 2004-07-14 信号処理装置及び方法

Country Status (4)

Country Link
US (1) US20050030275A1 (enExample)
JP (1) JP2005039829A (enExample)
KR (1) KR100968564B1 (enExample)
TW (1) TW200518021A (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101197057B1 (ko) * 2005-12-12 2012-11-06 삼성디스플레이 주식회사 표시 장치
JP4209430B2 (ja) * 2006-05-25 2009-01-14 パナソニック株式会社 ドライバ制御装置
US7685458B2 (en) * 2006-12-12 2010-03-23 Kabushiki Kaisha Toshiba Assigned task information based variable phase delayed clock signals to processor cores to reduce di/dt
CN101689346B (zh) * 2007-03-14 2012-05-02 日本先锋公司 显示装置及其驱动方法
KR101404545B1 (ko) 2007-07-05 2014-06-09 삼성디스플레이 주식회사 표시 장치의 구동 장치 및 구동 방법과 표시 장치
TW200912839A (en) * 2007-09-04 2009-03-16 Chi Mei Optoelectronics Corp Driving device with polarity inversion of data line signal for liquid display panel and driving method thereof
JP2009115936A (ja) * 2007-11-05 2009-05-28 Sharp Corp 駆動制御方法、駆動制御装置及び表示装置
KR101617325B1 (ko) * 2009-06-03 2016-05-19 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
US8619932B2 (en) 2010-09-15 2013-12-31 Mediatek Inc. Signal transmission system with clock signal generator configured for generating clock signal having stepwise/smooth frequency transition and related signal transmission method thereof
KR101882703B1 (ko) * 2016-10-14 2018-07-27 숭실대학교산학협력단 고정된 샘플링 주파수에 의해 주기적으로 동작하는 시스템에서 emi를 저감시키기 위한 방법, 이를 수행하기 위한 기록 매체 및 장치
KR102687614B1 (ko) 2018-06-22 2024-07-24 엘지디스플레이 주식회사 스캔 구동부 및 이를 이용한 표시장치
CN111816111B (zh) * 2020-07-08 2022-08-26 昆山龙腾光电股份有限公司 驱动芯片及显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11249622A (ja) * 1998-03-02 1999-09-17 Advanced Display Inc 液晶表示装置および複数ポートのデータ出力部を有する集積回路
KR100358644B1 (ko) * 1999-01-05 2002-10-30 삼성전자 주식회사 듀얼 시프트 클록 배선을 가지는 액정 표시 장치
JP3409768B2 (ja) * 2000-02-14 2003-05-26 Ｎｅｃエレクトロニクス株式会社 表示装置の回路
JP3739663B2 (ja) * 2000-06-01 2006-01-25 シャープ株式会社 信号転送システム、信号転送装置、表示パネル駆動装置、および表示装置
KR100666320B1 (ko) * 2000-07-18 2007-01-09 삼성전자주식회사 시프트 레지스터 및 그를 채용한 액정표시장치의 구동 회로
US6856373B2 (en) * 2000-08-29 2005-02-15 Fujitsu Display Technologies Corporation Liquid crystal display apparatus and reduction of electromagnetic interference
KR100471054B1 (ko) * 2000-11-18 2005-03-07 삼성전자주식회사 컴퓨터 시스템 및 그의 화상처리방법
KR100769159B1 (ko) * 2000-12-28 2007-10-23 엘지.필립스 엘시디 주식회사 액정 디스플레이 장치 및 그 구동방법

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