JP2016184768A - Wiring board manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which prevents an electrical short circuit between signal wiring and a power supply conductor, or between power supply conductors different from each other in a clearance portion.SOLUTION: A wiring board manufacturing method comprises the steps of: forming on an insulation layer 1 or 2 in a lower layer, a power supply conductor P in a lower layer, on which a plurality of rectangular gassing opening A, 100-300 μm on each side are formed at an arrangement pitch of 300-1000 μm in a matrix shape; laminating on the insulation layer 1 or 2 in the lower layer, an insulation layer 2 in an upper layer so as to cover the power supply conductor P in the lower layer; and forming on the insulation layer 2 in the upper layer by a semi-additive method, circular via lands 9 each having a diameter of 80-150 μm and power supply conductors P in the upper layer, which are arranged to surround the via lands 9 via respective clearances C each having a width of 30-100 μm. The openings A and the clearances C are arranged not to be arranged one above the other.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a method of manufacturing a wiring board for mounting a semiconductor element.

  Generally, current electronic devices are required to be small, thin, lightweight, high performance, high function, high quality, and high reliability, as represented by mobile communication devices. Along with this, semiconductor devices mounted on electronic devices are also required to be small and high density. Therefore, miniaturization / thinning / multi-terminals are also demanded for wiring boards constituting semiconductor devices. In order to realize this, the wiring board such as the signal wiring in the wiring board is narrowed and the interval between the wirings is narrowed, and further, the wiring board has a high density by increasing the number of wirings.

  As a wiring board capable of such high-density wiring, a multilayer wiring board manufactured by adopting a build-up method is known. In the build-up method, first, as shown in FIG. 4 (a), a copper foil is formed on the insulating layer 11 for the core, which is made by impregnating a reinforcing material such as glass cloth or aramid nonwoven fabric with a thermosetting resin. The core wiring conductor 12 made of copper or a copper plating layer is formed. Next, as shown in FIG. 4B, a build-up insulating layer 13 made of a thermosetting resin such as an epoxy resin is laminated thereon and a via hole 14 is formed in the insulating layer 13. Next, as shown in FIG. 4C, a buildup wiring conductor 15 is formed thereon by, for example, a semi-additive method. Further, as shown in FIG. 4 (d), a build-up insulating layer 13 and a build-up wiring conductor layer 15 are alternately laminated thereon as necessary.

  In the semi-additive method, first, as shown in FIG. 5A, a base metal film 15a of about 0.1 to 1 μm is formed on the surface of the insulating layer 13 by, for example, an electroless copper plating method. Next, as shown in FIG. 5B, a plating resist layer 16 having openings 16a corresponding to the pattern of the build-up wiring conductor 15 is formed on the base metal film 15a. Next, as shown in FIG. 5C, the main conductor layer 15b is formed on the base metal film 15a in the opening 16a by, for example, electrolytic copper plating. Finally, as shown in FIG. 5 (d), the plating resist layer 16 is removed and the base metal film 15a exposed from the main conductor layer 15b is removed by etching to form the base metal film 15a and the main conductor layer 15b. This is a method of forming the wiring conductor 15.

  The wiring conductor 12 and the wiring conductor 15 in such a wiring board are divided into a power supply conductor P and a signal wiring S as shown in FIG. Note that there are power supply conductors P that are connected to a ground potential and those that are connected to a power supply potential different from the ground potential. Among these, the power supply conductor P functions to supply a power supply potential and a ground potential to a semiconductor element mounted on the wiring board. These power supply conductors P are composed of a solid pattern that occupies a wide area on the insulating layer 11 or the insulating layer 13. Further, the signal wiring S functions to propagate an electrical signal. The signal wiring S is composed of a thin strip pattern extending on the insulating layer 13. A power supply conductor P is disposed around the signal wiring S on the same insulating layer 13 so as to surround the signal wiring S with a predetermined interval. A power supply conductor P is disposed on the upper and lower insulating layers 11 and the insulating layer 13 of the insulating layer 13 on which the signal wiring S is formed so as to face the signal wiring S. As a result, the signal wiring S is electromagnetically shielded and given a predetermined characteristic impedance.

  The buildup wiring conductors 15 positioned above and below the buildup insulating layer 13 and the buildup wiring conductor 15 and the core wiring conductor 12 are provided in the insulating layer 13. The via holes 14 are connected by via conductors 17 filled therein. The via conductor 17 is formed integrally with the wiring conductor 15 at the same time when the wiring conductor 15 for buildup is formed on the insulating layer 13 for buildup. The via conductor 17 is provided with a circular via land 18 having a diameter of 80 to 150 μm. A clearance C having a width of about 30 to 100 μm is formed between the signal via land 18 and the power supply conductor P surrounding the periphery thereof and between the power supply via land 18 and the other power supply conductor P surrounding them. Is formed.

  Further, the solid pattern of the power supply conductor P is provided with rectangular openings A arranged in a lattice pattern so as to escape the gas generated when the resin of the insulating layer 13 is cured. The openings A arranged in such a grid are arranged substantially uniformly over the entire surface of the power supply conductor P not facing the signal wiring S when the wiring board is viewed in plan. The openings A are squares having a side of about 100 to 300 μm, and are arranged in a lattice pattern at a pitch of 300 to 1000 μm.

  However, in the conventional wiring board, the opening A is arranged so as not to face the signal wiring S when viewed in plan, but the formation position is not particularly taken into consideration for the clearance C of the upper layer. It was. Therefore, depending on the opening A, it may be formed at a position overlapping the clearance C of the upper layer.

  By the way, when the insulating layer 13 for buildup is formed on the wiring conductor 12 or the wiring conductor 15 having the opening A, the insulating layer 13 is formed of the wiring conductor 12 or the wiring conductor 15 as shown in FIG. The part corresponding to the opening A follows a slightly concave and convex shape. Therefore, if an upper layer clearance C is formed at a position recessed following the opening A, the underlying metal film is formed at a position where the plating resist layer 16 corresponds to the opening A as shown in FIG. It may be in a floating state without sufficiently adhering to 15a. When the plating resist layer 16 is in a floating state in this manner, as shown in FIG. 7C, when the main conductor layer 15b is formed on the base metal film 15a in the opening 16a, the main conductor layer 15b A part thereof is formed so as to enter the gap between the plating resist layer 16 and the base metal film 15a. As a result, as shown in FIG. 7D, the main conductor layer 15b remains in the clearance C, which is electrically connected between the signal wiring S and the power supply conductor P or between different power supply conductors P. It will cause a short circuit.

Patent No. 3801180

  An object of the present invention is to provide a wiring board that does not cause an electrical short circuit between a signal wiring and a power supply conductor or between different power supply conductors in a clearance portion.

  In the method for manufacturing a wiring board according to the present invention, a plurality of rectangular gas vent openings having a side length of 100 to 300 μm are formed in a lattice pattern at an arrangement pitch of 300 to 1000 μm on a lower insulating layer. Forming a lower power conductor, laminating an upper insulating layer on the lower insulating layer so as to cover the lower power conductor, and a circular shape having a diameter of 80 to 150 μm on the upper insulating layer And a step of forming, by a semi-additive method, an upper layer power supply conductor disposed so as to surround the via land with a clearance of 30 to 100 μm in width. The opening and the clearance are arranged so as not to face each other vertically.

  According to the method for manufacturing a wiring board of the present invention, the opening formed in the lower power conductor and the clearance formed between the upper via land and the upper power conductor are arranged so as not to overlap each other. Therefore, when forming the upper via land and the power conductor on the upper insulating layer by the semi-additive method, the upper insulating layer where the clearance is to be formed is not recessed, so that there is no gap between the signal wiring and the power conductor. Alternatively, it is possible to provide a wiring board in which different power supply conductors are not electrically short-circuited.

FIG. 1 is a cross-sectional view showing a wiring board manufactured according to an example of an embodiment of a method for manufacturing a wiring board of the present invention. FIG. 2 is a schematic perspective view of a main part of the wiring board shown in FIG. FIG. 3 is a perspective view of a principal part of the wiring board shown in FIG. FIG. 4 is a schematic cross-sectional view of a main part for each step for explaining the build-up method. FIG. 5 is a schematic cross-sectional view of a main part for each step for explaining the semi-additive method. FIG. 6 is a main part schematic perspective view showing a conventional wiring board. FIG. 7 is a schematic cross-sectional view of a main part for each process for explaining a problem in the conventional wiring board.

  Next, an example of an embodiment in the method for manufacturing a wiring board of the present invention will be described. As shown in FIG. 1, the wiring board manufactured according to this example includes a core insulating layer 1 and a buildup insulating layer 2. And the semiconductor element S is mounted in the center part of the upper surface. The lower surface serves as a connection surface for connection to an external electric circuit board. In this example, two layers of build-up insulating layers 2 are stacked on the upper and lower sides of one core insulating layer 1. The core insulating layer 1 may be a laminate of two or more layers. Further, the build-up insulating layers 2 laminated on the upper and lower surfaces of the insulating layer 1 may be one layer or three layers or more.

  The core insulating layer 1 is formed with a plurality of through holes 3 penetrating from the upper surface to the lower surface. A core wiring conductor 4 is formed on the upper and lower surfaces of the core insulating layer 1 and the inner wall of the through hole 3. The wiring conductors 4 deposited on the upper and lower surfaces of the insulating layer 1 are electrically connected through the through hole 3.

  The core insulating layer 1 is made of, for example, a resin-based insulating material in which a glass fabric in which glass fiber bundles are woven vertically and horizontally is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The thickness of the core insulating layer 1 is about 0.3 to 1.5 mm. The diameter of the through hole 3 is about 0.1 to 0.3 mm. The inside of the through hole 3 is filled with a hole filling resin (not shown).

  The core wiring conductor 4 is made of a copper foil or a copper plating layer. The thickness of the wiring conductor 4 is about 5 to 50 μm. The wiring conductor 4 on the upper and lower surfaces of the insulating layer 1 has a copper foil having a thickness of about 3 to 20 μm attached to the entire upper and lower surfaces of the insulating layer 1, and a copper plating layer is deposited on the copper foil as necessary. After that, it is formed by etching into a predetermined pattern using a known subtractive method. The wiring conductor 4 in the through hole 3 is formed by depositing a copper plating film having a thickness of about 3 to 50 μm on the inner surface of the through hole 3 by an electroless plating method and an electrolytic plating method.

  A plurality of via holes 5 are formed in the build-up insulating layer 2. A build-up wiring conductor 6 is attached to the surface of the insulating layer 2. The via hole 5 is filled with a via conductor 7.

  The build-up insulating layer 2 is made of an insulating material in which an inorganic insulating filler such as silicon oxide powder is dispersed in an amount of about 30 to 70% by mass in a thermosetting resin such as an epoxy resin. Each of the insulating layers 2 has a thickness of about 20 to 60 μm. The diameter of the via hole 5 is about 30 to 100 μm. The insulating layer 2 has an insulating film made of an uncured thermosetting resin having a thickness of about 20 to 60 μm attached to the upper and lower surfaces of the insulating plate 1 and thermally cured, and the via hole 5 is drilled by laser processing. Further, it is formed by sequentially stacking the next insulating layers 2 thereon in the same manner. The wiring conductor 6 and the via conductor 7 deposited on the surface of each insulating layer 2 and the via hole 5 are about 5 to 50 μm in the surface of the insulating layer 2 and the via hole 5 every time each insulating layer 2 is formed. It is formed by depositing a copper plating film having a thickness in a predetermined pattern by a known semi-additive method.

  Further, a solder resist layer 8 is deposited on the surfaces of the outermost insulating layer 2 and the wiring conductor 6. The solder resist layer 8 is formed, for example, by adding a filler such as silica or talc to a thermosetting resin such as an acrylic-modified epoxy resin. The thickness of the solder resist layer 8 is about 10 to 50 μm. The solder resist 8 is a non-cured resin paste having photosensitivity, applied to the outermost insulating layer 2 having the wiring conductor 6 by using a roll coater method or a screen printing method, and dried. The film is formed by heat curing after exposure and development.

  By the way, the wiring conductor 4 and the wiring conductor 6 in the wiring board manufactured by this example are divided into the power supply conductor P and the signal wiring S, as shown in FIG. Note that there are power supply conductors P that are connected to a ground potential and those that are connected to a power supply potential different from the ground potential. Among these, the power supply conductor P functions to supply a power supply potential and a ground potential to a semiconductor element mounted on the wiring board. These power supply conductors P are formed of a solid pattern that occupies a wide area on the insulating layer 1 or the insulating layer 2. Further, the signal wiring S functions to propagate an electrical signal. The signal wiring S is composed of a thin strip pattern extending on the insulating layer 2. A power supply conductor P is disposed around the signal wiring S on the same insulating layer 2 so as to surround the signal wiring S with a predetermined interval. A power supply conductor P is disposed on the upper and lower insulating layers 1 and 2 of the insulating layer 2 on which the signal wiring S is formed so as to face the signal wiring S. As a result, the signal wiring S is electromagnetically shielded and given a predetermined characteristic impedance.

  The build-up wiring conductors 6 positioned above and below the build-up insulating layer 2 and the build-up wiring conductor 6 and the core wiring conductor 4 are provided on the insulating layer 2. The via holes 5 are connected by via conductors 7 filled therein. The via conductor 7 is formed integrally with the wiring conductor 6 when the build-up wiring conductor 6 is formed on the build-up insulating layer 2. The via conductor 7 is provided with a circular via land 9 having a diameter of 80 to 150 μm. A clearance C having a width of about 30 to 100 μm is formed between the signal via land 9 and the power supply conductor P surrounding the periphery thereof and between the power supply via land 9 and the other power supply conductor P surrounding them. Is formed.

  Further, the solid pattern of the power supply conductor P is provided with rectangular openings A arranged in a lattice pattern so as to escape the gas generated when the resin of the insulating layer 1 or the insulating layer 2 is cured. The openings A arranged in such a grid are arranged substantially uniformly over the entire surface of the power supply conductor P not facing the signal wiring S when the wiring board is viewed in plan. The openings A are squares having a side of about 100 to 300 μm, and are arranged in a lattice pattern at a pitch of 300 to 1000 μm.

  In the method for manufacturing a wiring board according to the present invention, as shown in FIG. 3, the lower opening A is arranged so as not to oppose the signal wiring S when viewed in plan, and the upper clearance C is also opposed. Arrange so as not to. Thus, since the opening A is arranged so as not to face the clearance C of the upper layer, the clearance C is set when the upper via land 9 and the power supply conductor P are formed on the upper insulating layer 2 by the semi-additive method. The upper insulating layer 2 is not recessed. Thereby, it is possible to provide a wiring board in which the signal wiring S and the power supply conductor P or between the different power supply conductors P are not electrically short-circuited.

1, 2 Insulating layer 9 Via land A Degassing opening C Clearance P Power supply conductor

Claims (1)

  Forming a lower-layer power supply conductor in which a plurality of rectangular gas vent openings each having a side length of 100 to 300 μm are formed in a grid pattern at an array pitch of 300 to 1000 μm on the lower insulating layer; A step of laminating an upper insulating layer on the lower insulating layer so as to cover the lower power supply conductor; a circular via land having a diameter of 80 to 150 μm on the upper insulating layer; and a width around the via land. Forming an upper power supply conductor disposed so as to be surrounded by a clearance of 30 to 100 μm by a semi-additive method, wherein the opening and the clearance are vertically A method of manufacturing a wiring board, wherein the wiring board is disposed so as not to face the wiring board.