JP7133329B2 - wiring board - Google Patents

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JP7133329B2
JP7133329B2 JP2018055794A JP2018055794A JP7133329B2 JP 7133329 B2 JP7133329 B2 JP 7133329B2 JP 2018055794 A JP2018055794 A JP 2018055794A JP 2018055794 A JP2018055794 A JP 2018055794A JP 7133329 B2 JP7133329 B2 JP 7133329B2
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insulating layer
electrode
electrodes
wiring board
solder
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JP2019169596A (en
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孝之 禰占
芳弘 長谷川
正昭 原園
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Kyocera Corp
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Description

本開示は、半導体素子等の電子部品を搭載する配線基板に関するものである。 The present disclosure relates to a wiring board on which electronic components such as semiconductor elements are mounted.

現在、微細な配線導体が絶縁層に高密度に位置する配線基板が開発されている。このような配線基板は、半導体素子が有する接続面積および配置間隔の異なる電極に対応して、接続面積および配置間隔の異なる電極を有している。そして、半導体素子の電極と配線基板の電極とが、例えば互いに対向し合った状態で半田を介して接続している。 Currently, wiring substrates are being developed in which fine wiring conductors are densely located on an insulating layer. Such a wiring board has electrodes with different connection areas and different spacings corresponding to the electrodes with different connection areas and different spacings of the semiconductor element. The electrodes of the semiconductor element and the electrodes of the wiring board are connected to each other through solder, for example, while facing each other.

特許第５８７６０９３号公報Japanese Patent No. 5876093

半導体素子の電極と配線基板の電極とを半田によって接続する場合、電極の半田との接続面積の大きさに応じて半田量を調整する必要がある。接続面積の小さな電極同士の接続において使用する半田量は、接続面積の大きな電極同士の接続において使用する半田量に比べて少ない。このため、互いに対向する接続面積の小さな電極同士の間隔を、接続面積の大きな電極同士の間隔よりも小さくする。このため、例えば配線基板の上方に半導体素子を位置させて電極同士の接続を行うときに、配線基板の小さな接続面積の電極の高さを、大きな接続面積の電極の高さよりも高くすることがある。このような場合、接続面積の小さな（つまり、より高い位置にある）電極上に半田を載置したときに、半田が電極から滑り落ちてしまい半導体素子の電極との接続が不完全になることがある。その結果、半導体素子が安定的に作動しない虞がある。接続面積の比較的小さい電極同士の間隔は、接続面積の比較的大きい電極同士の間隔よりも小さいため、上記の接続不完全性は、電極同士の間隔が小さいときに生じやすい傾向がある。 When the electrodes of the semiconductor element and the electrodes of the wiring board are connected by solder, it is necessary to adjust the amount of solder according to the size of the connection area between the electrodes and the solder. The amount of solder used to connect electrodes with small connection areas is less than the amount of solder used to connect electrodes with large connection areas. For this reason, the interval between electrodes with small connection areas facing each other is made smaller than the interval between electrodes with large connection areas. For this reason, for example, when a semiconductor element is positioned above a wiring board and the electrodes are connected to each other, the height of the electrodes with a small connection area on the wiring board can be made higher than the height of the electrodes with a large connection area. be. In such a case, when solder is placed on an electrode with a small connection area (that is, at a higher position), the solder slides down from the electrode, resulting in an incomplete connection with the electrode of the semiconductor device. There is As a result, the semiconductor element may not operate stably. Since the distance between electrodes with a relatively small connection area is smaller than the distance between electrodes with a relatively large connection area, the above-described imperfect connection tends to occur when the distance between the electrodes is small.

本開示の配線基板は、平面視で互いに隣接する第１領域および第２領域を含んだ上面を有する第１絶縁層と、第１絶縁層の第１領域に重なることなく第１絶縁層の第２領域に位置する第２絶縁層と、第１絶縁層の第１領域に互いに第１間隔で位置している複数の第１電極と、第２絶縁層に互いに第１間隔よりも小さい第２間隔で位置しており、第１電極の上面より小さい面積の上面を有する複数の第２電極と、を有しており、断面視で第２電極の上面は、第１電極の上面よりも高い位置にあるとともに、第２絶縁層は、第２電極のうち側面のみを被覆しており、断面視で第２絶縁層の上面が、第１絶縁層の上面よりも高い位置にあることを特徴とするものである。
A wiring board of the present disclosure includes a first insulating layer having an upper surface including a first region and a second region that are adjacent to each other in a plan view, and a first insulating layer that does not overlap the first region of the first insulating layer. a second insulating layer positioned in two regions; a plurality of first electrodes positioned in a first region of the first insulating layer at a first distance from each other; and a plurality of second electrodes positioned at intervals and having upper surfaces having a smaller area than the upper surfaces of the first electrodes, wherein the upper surfaces of the second electrodes are higher than the upper surfaces of the first electrodes in a cross-sectional view. The second insulating layer covers only the side surface of the second electrode, and the top surface of the second insulating layer is positioned higher than the top surface of the first insulating layer in a cross-sectional view. and

本開示の配線基板によれば、半導体素子が安定して作動することが可能な配線基板を提供することができる。 According to the wiring board of the present disclosure, it is possible to provide a wiring board in which a semiconductor element can stably operate.

図１は、本開示の配線基板の実施形態例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an embodiment of a wiring board of the present disclosure. 図２は、本開示の配線基板の実施形態例の要部を示す拡大断面図である。FIG. 2 is an enlarged cross-sectional view showing a main part of an embodiment of the wiring board of the present disclosure. 図３は、本開示の配線基板の別の実施形態例を示す概略断面図である。FIG. 3 is a schematic cross-sectional view showing another embodiment of the wiring board of the present disclosure. 図４は、本開示の配線基板の別の実施形態例の要部を示す拡大断面図である。FIG. 4 is an enlarged cross-sectional view showing a main part of another embodiment of the wiring board of the present disclosure. 図５は、本開示の配線基板の別の実施形態例の要部を示す拡大断面図である。FIG. 5 is an enlarged cross-sectional view showing a main part of another embodiment of the wiring board of the present disclosure. 図６は、本開示の配線基板の別の実施形態例の要部を示す拡大断面図である。FIG. 6 is an enlarged cross-sectional view showing a main part of another embodiment of the wiring board of the present disclosure. 図７は、本開示の配線基板の別の実施形態例の要部を示す拡大断面図である。FIG. 7 is an enlarged cross-sectional view showing a main part of another embodiment of the wiring board of the present disclosure. 図８は、本開示の配線基板の別の実施形態例の要部を示す拡大断面図である。FIG. 8 is an enlarged cross-sectional view showing a main part of another embodiment of the wiring board of the present disclosure. 図９は、本開示の配線基板の別の実施形態例を示す概略断面図である。FIG. 9 is a schematic cross-sectional view showing another embodiment of the wiring board of the present disclosure.

本開示の配線基板を、図１および図２を基にして説明する。配線基板１は、コア用絶縁層２と、ビルドアップ用絶縁層３と、配線導体４と、を有している。配線基板１の上面には、複数の半導体素子Ｓが搭載される。半導体素子Ｓを搭載する場合は、例えば半導体素子Ｓの電極Ｐに半田５を被着しておき、配線基板１の電極と半導体素子Ｓの電極Ｐとを半田５を介して接続する。 A wiring board according to the present disclosure will be described with reference to FIGS. 1 and 2. FIG. The wiring board 1 has a core insulating layer 2 , a buildup insulating layer 3 , and wiring conductors 4 . A plurality of semiconductor elements S are mounted on the upper surface of the wiring board 1 . When the semiconductor element S is mounted, for example, the electrodes P of the semiconductor element S are coated with solder 5 , and the electrodes of the wiring board 1 and the electrodes P of the semiconductor element S are connected through the solder 5 .

コア用絶縁層２は、例えば補強用のガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等を含浸させた絶縁材料を含んでいる。コア用絶縁層２は、配線基板１における補強用の支持体としての機能を有している。コア用絶縁層２は、上下に貫通する複数のスルーホール６を有している。 The core insulating layer 2 contains an insulating material obtained by impregnating a reinforcing glass cloth with an epoxy resin, a bismaleimide triazine resin, or the like, for example. The core insulating layer 2 functions as a supporting member for reinforcing the wiring board 1 . The core insulating layer 2 has a plurality of through holes 6 penetrating vertically.

コア用絶縁層２の厚みは、例えば２００～１２００μｍに設定されている。スルーホール６の径は、例えば５０～２００μｍに設定されている。配線基板１は、平面視で四角形状の平板状である。また、配線基板１の１辺の長さは２０～８０ｍｍ、厚みが０．３～１．６ｍｍ程度である。 The thickness of the core insulating layer 2 is set to, for example, 200 to 1200 μm. The diameter of the through hole 6 is set to 50 to 200 μm, for example. The wiring board 1 has a rectangular flat plate shape in a plan view. Moreover, the length of one side of the wiring board 1 is 20 to 80 mm, and the thickness is about 0.3 to 1.6 mm.

コア用絶縁層２は、強化用のガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させたプリプレグを複数積層して、加熱下でプレス加工を行うことで平板状に形成される。スルーホール６は、コア用絶縁層２に、ドリル加工、レーザー加工またはブラスト加工等の処理を行うことで形成される。コア用絶縁層２の上下表面の配線導体４同士が、スルーホール６内の配線導体４を介して電気的に接続される。 The insulating layer 2 for the core is formed into a flat plate shape by laminating a plurality of prepregs made by impregnating a reinforcing glass cloth with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, and pressing the laminate under heat. be done. The through-holes 6 are formed in the core insulating layer 2 by performing processing such as drilling, laser processing, or blasting. The wiring conductors 4 on the upper and lower surfaces of the core insulating layer 2 are electrically connected via the wiring conductors 4 in the through holes 6 .

ビルドアップ用絶縁層３は、コア用絶縁層２の上面および下面にそれぞれ３層ずつ積層された状態で位置している。ビルドアップ用絶縁層３は、コア用絶縁層２の上面および下面において、後述する配線導体４を被覆しており、互いに隣接する配線導体４同士の絶縁性を確保する機能を有している。ビルドアップ用絶縁層３は、配線導体４を底面とする複数のビアホール７を有している。 The build-up insulating layers 3 are positioned in a state in which three layers are laminated on each of the upper surface and the lower surface of the core insulating layer 2 . The build-up insulating layer 3 covers the wiring conductors 4 to be described later on the upper and lower surfaces of the core insulating layer 2, and has a function of ensuring insulation between the wiring conductors 4 adjacent to each other. The build-up insulating layer 3 has a plurality of via holes 7 with the wiring conductors 4 as bottom surfaces.

ビルドアップ用絶縁層３は、例えばエポキシ樹脂やフェノール樹脂等に絶縁粒子を分散させた絶縁材料を含んでいる。絶縁粒子は、例えばシリカ（ＳｉＯ２）や硝子やアルミナ等が挙げられる。絶縁粒子は、例えば球状の形状を有しており、平均粒径は、例えば０．１～０．５μｍに設定されている。ビルドアップ用絶縁層３における絶縁粒子の含有割合は、例えば４０～８０ｗｔ％に設定されている。球状の形状は、絶縁粒子を高密度に含有するために有利である。絶縁粒子は、ビルドアップ用絶縁層３において、熱膨張係数を小さくして、配線導体４との熱膨張係数差に起因した熱応力を低減して配線導体４の断線を抑制する等の役割を有している。 The build-up insulating layer 3 contains an insulating material in which insulating particles are dispersed in, for example, epoxy resin or phenol resin. Examples of insulating particles include silica (SiO 2 ), glass, and alumina. The insulating particles have, for example, a spherical shape, and the average particle size is set at, for example, 0.1 to 0.5 μm. The content of insulating particles in the build-up insulating layer 3 is set to, for example, 40 to 80 wt %. A spherical shape is advantageous for containing insulating particles at a high density. The insulating particles reduce the thermal expansion coefficient in the build-up insulating layer 3 to reduce the thermal stress caused by the difference in thermal expansion coefficient from that of the wiring conductor 4, thereby suppressing disconnection of the wiring conductor 4. have.

ビルドアップ用絶縁層３は、第１絶縁層３ａおよび第２絶縁層３ｂを含んでいる。本例において第１絶縁層３ａは、コア用絶縁層２の上面から２層目に位置している。 The buildup insulating layer 3 includes a first insulating layer 3a and a second insulating layer 3b. In this example, the first insulating layer 3 a is positioned second from the upper surface of the core insulating layer 2 .

第１絶縁層３ａの厚みは、例えば１０～４０μｍに設定されている。ビルドアップ用絶縁層３は、後述する第１領域８において配線導体４を底面とする複数の第１ビアホール７ａを有している。第１ビアホール７ａの径は、例えば１５～６０μｍに設定されている。また、ビルドアップ用絶縁層３は、後述する第２領域９において配線導体４を底面とする複数の第２ビアホール７ｂを有している。第２ビアホール７ｂの径は、例えば１０～２０μｍに設定されている。 The thickness of the first insulating layer 3a is set to 10 to 40 μm, for example. The build-up insulating layer 3 has a plurality of first via holes 7a having the wiring conductors 4 as bottom surfaces in a first region 8, which will be described later. The diameter of the first via hole 7a is set to 15 to 60 μm, for example. In addition, the build-up insulating layer 3 has a plurality of second via holes 7b having the wiring conductor 4 as a bottom surface in a second region 9, which will be described later. The diameter of the second via hole 7b is set to 10 to 20 μm, for example.

第１絶縁層３ａは、上面外周部に第１領域８を有している。また、第１絶縁層３ａは、上面中央部に第１領域８に隣接する第２領域９を有している。第１絶縁層３ａは、例えばエポキシ樹脂等の熱硬化性樹脂中に絶縁粒子を分散させた絶縁層用のフィルムを、真空下でコア用絶縁層２の上下面に配線導体４を被覆するように被着して熱硬化することで形成される。 The first insulating layer 3a has a first region 8 on the outer periphery of the upper surface. Further, the first insulating layer 3a has a second region 9 adjacent to the first region 8 at the central portion of the upper surface. The first insulating layer 3a is formed by applying an insulating film in which insulating particles are dispersed in a thermosetting resin such as epoxy resin under vacuum so as to cover the upper and lower surfaces of the core insulating layer 2 with the wiring conductors 4. It is formed by adhering to and thermally curing.

第１領域８には、複数の第１電極１０が例えば一定の間隔で位置している。第１電極１０は、平面視で例えば円形状を有している。第１電極１０の直径は、例えば３５～１００μｍに設定されている。第１電極１０の厚さは、例えば５～３０μｍに設定されている。互いに隣接する第１電極１０同士は、第１間隔Ｌ１で位置している。第１間隔Ｌ１は、例えば７５～１５０μｍに設定されている。なお、第１間隔Ｌ１は、互いに隣接する第１電極の円の中心間の距離を指している。 A plurality of first electrodes 10 are positioned, for example, at regular intervals in the first region 8 . The first electrode 10 has, for example, a circular shape in plan view. The diameter of the first electrode 10 is set to 35 to 100 μm, for example. The thickness of the first electrode 10 is set to 5 to 30 μm, for example. The first electrodes 10 adjacent to each other are positioned at a first interval L1. The first interval L1 is set to 75 to 150 μm, for example. The first interval L1 indicates the distance between the centers of the circles of the first electrodes that are adjacent to each other.

第１電極１０は、半導体素子Ｓの有する電極Ｐのうち、比較的接続面積の大きな電極Ｐと半田５を介して接続される。本例では、１つの半導体素子Ｓが、互いに接続面積が異なる複数の電極Ｐを有している。複数の電極Ｐは、接続面積が比較的大きいものと比較的小さいものとの２種類を含んでいる。一例として、半導体素子Ｓの電極Ｐのうち、接続面積が比較的大きいものは外部基板との接続用であり、接続面積が比較的小さいものは別の半導体素子Ｓとの接続用である。 The first electrode 10 is connected to an electrode P having a relatively large connection area among the electrodes P of the semiconductor element S through solder 5 . In this example, one semiconductor element S has a plurality of electrodes P with different connection areas. The plurality of electrodes P includes two types, one having a relatively large connection area and one having a relatively small connection area. As an example, among the electrodes P of the semiconductor element S, those with a relatively large connection area are for connection with an external substrate, and those with a relatively small connection area are for connection with another semiconductor element S.

第２領域９には、複数の第２電極１１が位置している。第２電極１１は、平面視で例えば円形状を有している。第２電極１１の直径は、第１電極１０の直径よりも小さく、例えば２０～３５μｍに設定されている。つまり、第２電極１１の上面の面積は、第１電極１０の上面の面積よりも小さく設定されている。第２電極１１の厚さは、第１電極１０の厚さよりも大きく、例えば５～１５μｍに設定されている。言い換えれば、第２電極１１の上面は、第１電極１０の上面よりも高い位置にある。互いに隣接する第２電極１１同士は、第２間隔Ｌ２で位置している。第２間隔Ｌ２は、第１間隔Ｌ１よりも小さく、例えば４０～５５μｍに設定されている。なお、第２間隔Ｌ２は、互いに隣接する第２電極１１の円の中心間の距離を指している。 A plurality of second electrodes 11 are positioned in the second region 9 . The second electrode 11 has, for example, a circular shape in plan view. The diameter of the second electrode 11 is smaller than the diameter of the first electrode 10, and is set to 20 to 35 μm, for example. That is, the area of the top surface of the second electrode 11 is set smaller than the area of the top surface of the first electrode 10 . The thickness of the second electrode 11 is larger than the thickness of the first electrode 10, and is set to 5 to 15 μm, for example. In other words, the top surface of the second electrode 11 is positioned higher than the top surface of the first electrode 10 . The second electrodes 11 adjacent to each other are positioned at a second interval L2. The second spacing L2 is smaller than the first spacing L1, and is set to 40 to 55 μm, for example. The second interval L2 indicates the distance between the centers of the circles of the second electrodes 11 adjacent to each other.

また、第２領域９には、第２絶縁層３ｂが位置している。第２電極１１は、側面が第２絶縁層３ｂに被覆されており、上面が第２絶縁層３ｂから露出している。本例においては、第２電極１１の上面の高さと第２絶縁層３ｂの上面の高さとが同じである。第２絶縁層３ｂの厚みは、例えば５～１５μｍに設定されている。 A second insulating layer 3 b is located in the second region 9 . The second electrode 11 has a side surface covered with the second insulating layer 3b and an upper surface exposed from the second insulating layer 3b. In this example, the height of the upper surface of the second electrode 11 and the height of the upper surface of the second insulating layer 3b are the same. The thickness of the second insulating layer 3b is set to 5 to 15 μm, for example.

第２絶縁層３ｂは、例えば次のようにして形成される。まず、第１絶縁層３ａの上面に第１電極１０および第２電極１１を被覆する状態で第２絶縁層用のフィルム樹脂を被着、または液状樹脂を塗布して熱硬化する。次に、例えばサーフェースプレーナ装置により、硬化した第２絶縁層用の樹脂を上面から均等に平面研磨して第２電極１１の上面を露出させる。これにより、第２電極１１の上面と第２絶縁層用の樹脂の上面とが同じ高さに形成される。次に、第２絶縁層３ｂの上面にマスキングを施しておき、第１領域８に位置する硬化した第２絶縁層用の樹脂をドライエッチング処理により除去する。これにより第１領
域８の第１絶縁層３ａ上面に第１電極１０を露出させる。最後に第２絶縁層用の樹脂の上面のマスキングを除去することで、第２絶縁層３ｂが形成される。 The second insulating layer 3b is formed, for example, as follows. First, a film resin for the second insulating layer is applied to the upper surface of the first insulating layer 3a while covering the first electrode 10 and the second electrode 11, or a liquid resin is applied and cured by heat. Next, the hardened resin for the second insulating layer is evenly polished from the upper surface by, for example, a surface planer device to expose the upper surface of the second electrode 11 . Thereby, the upper surface of the second electrode 11 and the upper surface of the resin for the second insulating layer are formed at the same height. Next, the upper surface of the second insulating layer 3b is masked, and the hardened resin for the second insulating layer located in the first region 8 is removed by dry etching. As a result, the first electrode 10 is exposed on the upper surface of the first insulating layer 3a in the first region 8. Next, as shown in FIG. Finally, the second insulating layer 3b is formed by removing the masking on the upper surface of the resin for the second insulating layer.

第２電極１１は、半導体素子Ｓの有する電極Ｐのうち、比較的接続面積の小さな電極と半田５を介して接続される。この場合、半田５の量は、接続面積の大きな電極Ｐに用いられる半田５の量よりも少ないため半田高さが低くなるが、第２電極１１の上面が第１電極１０の上面よりも高い位置にあることから、半導体素子Ｓの電極Ｐと第２電極１１との間隔を小さくすることができるため、少量の半田５でも互いの電極同士を完全に接続することができる。 The second electrode 11 is connected to an electrode having a relatively small connection area among the electrodes P of the semiconductor element S through solder 5 . In this case, the amount of the solder 5 is less than the amount of the solder 5 used for the electrode P with a large connection area, so the solder height is low, but the top surface of the second electrode 11 is higher than the top surface of the first electrode 10. Because of the position, the distance between the electrode P of the semiconductor element S and the second electrode 11 can be reduced, so that the electrodes can be completely connected to each other even with a small amount of solder 5 .

また、第２電極１１は、側面が第２絶縁層３ｂに被覆されており、上面が第２絶縁層３ｂから露出している。このため、半田５は濡れ性の悪い第２絶縁層３ｂの上面には広がりにくく、第２電極１１の上面に留まり易くなるため、半田５が第２電極１１から滑り落ちてしまうことを抑制することができる。第２電極１１の上面の面積が小さく、半田５が安定的に載置しにくい場合に特に有利である。 The second electrode 11 has a side surface covered with the second insulating layer 3b and an upper surface exposed from the second insulating layer 3b. Therefore, the solder 5 is less likely to spread on the upper surface of the second insulating layer 3b with poor wettability and tends to remain on the upper surface of the second electrode 11, thereby suppressing the solder 5 from slipping off the second electrode 11. be able to. This is particularly advantageous when the area of the upper surface of the second electrode 11 is small and it is difficult to place the solder 5 stably.

なお、第１絶縁層３ａおよび第２絶縁層３ｂは、例えばエポキシ樹脂やフェノール樹脂等の同じ種類の絶縁材料を含む構成にしておくと、第１絶縁層３ａと第２絶縁層３ｂとの間で熱伸縮差を抑制することが可能になり、半導体素子Ｓの電極Ｐと第１電極１０、あるいは第２電極１１との接続部の亀裂の発生を抑制する点で有利である。なお、同じ種類とは、基本的には第１絶縁層３ａと第２絶縁層３ｂが同一の樹脂組成物のことを指す。ただし、上記樹脂を主成分とするネットワークポリマーが形成可能な組み合わせであればよい。このようなネットワークポリマーからなるいずれか１つの組み合わせであればよい。 If the first insulating layer 3a and the second insulating layer 3b are made to contain the same kind of insulating material such as epoxy resin or phenol resin, for example, there will be a gap between the first insulating layer 3a and the second insulating layer 3b. It is possible to suppress the difference in thermal expansion and contraction at , which is advantageous in suppressing the occurrence of cracks in the connecting portion between the electrode P of the semiconductor element S and the first electrode 10 or the second electrode 11 . The same type basically means that the first insulating layer 3a and the second insulating layer 3b are made of the same resin composition. However, any combination that can form a network polymer having the resin as a main component may be used. Any one combination of such network polymers may be used.

配線導体４は、コア用絶縁層２の上面および下面、スルーホール６内、ビルドアップ用絶縁層３の表面、およびビアホール７内に位置している。最下層に位置しているビルドアップ用絶縁層３の下面に位置している配線導体４は、外部基板と接続される第３電極１２として機能する。配線導体４は、例えばセミアディティブ法等のめっき工法により形成され、銅等の良導電性金属を含んでいる。 The wiring conductors 4 are located on the top and bottom surfaces of the core insulating layer 2 , inside the through holes 6 , on the surface of the buildup insulating layer 3 , and inside the via holes 7 . The wiring conductor 4 located on the lower surface of the buildup insulating layer 3 located on the bottom layer functions as a third electrode 12 connected to the external substrate. The wiring conductor 4 is formed by, for example, a plating method such as a semi-additive method, and contains a highly conductive metal such as copper.

コア用絶縁層２の上面側において、平面視で第２領域９に位置している配線導体４は、主に第２ビアホール７ｂを介して第２電極１１とつながっている。これにより、隣接して搭載される半導体素子Ｓ同士の間で電気信号の送受信が可能になる。 On the upper surface side of the core insulating layer 2, the wiring conductor 4 located in the second region 9 in plan view is connected to the second electrode 11 mainly through the second via hole 7b. This enables transmission and reception of electrical signals between the semiconductor elements S mounted adjacent to each other.

このような半導体素子Ｓ同士の間の電気信号の送受信が行われる配線導体４の線幅は、例えば２～６μｍであり、厚さは、例えば１～１０μｍに設定されている。 The line width of the wiring conductor 4 for transmitting and receiving electric signals between the semiconductor elements S is, for example, 2 to 6 μm, and the thickness is set to, for example, 1 to 10 μm.

平面視で第１領域８に位置している配線導体４は、主に第１ビアホール７ａおよびスルーホール６を介して第１電極１０と第３電極１２とつながっている。これにより、搭載されるそれぞれの半導体素子Ｓと外部基板との間で電気信号の送受信が可能になる。 The wiring conductor 4 positioned in the first region 8 in plan view is connected to the first electrode 10 and the third electrode 12 mainly through the first via hole 7a and the through hole 6 . This enables transmission and reception of electric signals between each mounted semiconductor element S and the external substrate.

このような半導体素子Ｓと外部基板との間の電気信号の送受信が行われる配線導体４の線幅は、例えば６～２０μｍであり、厚さは、例えば８～２０μｍに設定されている。 The line width of the wiring conductor 4 for transmitting and receiving electric signals between the semiconductor element S and the external substrate is set to, for example, 6 to 20 μm, and the thickness is set to, for example, 8 to 20 μm.

上述のように、本開示の配線基板１は、互いに隣接する第１領域８および第２領域９を含んだ上面を有する第１絶縁層３ａを有している。そして、第１領域８に互いに第１間隔Ｌ１で位置している複数の第１電極１０と、第２領域９に互いに第１間隔Ｌ１よりも小さい第２間隔Ｌ２で位置しており、第１電極１０の上面より小さい面積の上面を有する複数の第２電極１１と、を有している。さらに、断面視で第２電極１１の上面は、第１電極１０の上面よりも高い位置にあるとともに、第２領域９に、第２電極１１の一部を被覆しており、断面視で第１絶縁層３ａの上面よりも高い位置にある上面を有する第２絶縁層３ｂが位置している。第２絶縁層３ｂの上面が第１絶縁層３ａの上面よりも高い（半導体素子Ｓに近い）ため、第２電極１１の上面が第１電極１０の上面よりも高い位置（半導体素子Ｓの電極Ｐに近い位置）にあること等を含む上記構成が容易に実現されている。 As described above, the wiring board 1 of the present disclosure has the first insulating layer 3a having the upper surface including the first region 8 and the second region 9 adjacent to each other. A plurality of first electrodes 10 are positioned in the first region 8 with a first spacing L1, and a plurality of first electrodes 10 are positioned in the second region 9 with a second spacing L2 smaller than the first spacing L1. and a plurality of second electrodes 11 each having a top surface smaller in area than the top surfaces of the electrodes 10 . Furthermore, the upper surface of the second electrode 11 is positioned higher than the upper surface of the first electrode 10 in a cross-sectional view, and covers part of the second electrode 11 in the second region 9 . A second insulating layer 3b is located which has an upper surface which is higher than the upper surface of the first insulating layer 3a. Since the upper surface of the second insulating layer 3b is higher than the upper surface of the first insulating layer 3a (closer to the semiconductor element S), the upper surface of the second electrode 11 is higher than the upper surface of the first electrode 10 (the electrode of the semiconductor element S). P), etc., is easily realized.

第２電極１１は、半導体素子Ｓの有する電極のうち、比較的接続面積の小さな電極Ｐと半田５を介して接続される。この場合、半田５の量は、接続面積の大きな電極Ｐに用いられる半田５の量よりも少ないため半田高さが低くなるが、第２電極１１の上面が第１電極１０の上面よりも高い位置にある。このため、半導体素子Ｓの電極Ｐと第２電極１１との間隔を小さくすることができるため、少量の半田５でも互いの電極同士を完全に接続することができる。 The second electrode 11 is connected to the electrode P having a relatively small connection area among the electrodes of the semiconductor element S through the solder 5 . In this case, the amount of the solder 5 is less than the amount of the solder 5 used for the electrode P with a large connection area, so the solder height is low, but the top surface of the second electrode 11 is higher than the top surface of the first electrode 10. in position. Therefore, since the distance between the electrode P of the semiconductor element S and the second electrode 11 can be reduced, the electrodes can be completely connected to each other even with a small amount of solder 5 .

また、第２電極１１は、側面が第２絶縁層３ｂに被覆されており、上面が第２絶縁層３ｂから露出している。このため、半田５は濡れ性の悪い第２絶縁層３ｂの上面には広がりにくく、第２電極１１の上面に留まり易くなるため、半田５が第２電極１１から滑り落ちてしまうことを抑制することができる。 The second electrode 11 has a side surface covered with the second insulating layer 3b and an upper surface exposed from the second insulating layer 3b. Therefore, the solder 5 is less likely to spread on the upper surface of the second insulating layer 3b with poor wettability and tends to remain on the upper surface of the second electrode 11, thereby suppressing the solder 5 from slipping off the second electrode 11. be able to.

これらのことから、本開示の配線基板によれば、配線基板の電極と半導体素子の電極とを完全に接続することが可能になり、半導体素子を安定的に作動させることが可能な配線基板を提供することができる。 For these reasons, according to the wiring board of the present disclosure, it is possible to completely connect the electrodes of the wiring board and the electrodes of the semiconductor element, and the wiring board is capable of stably operating the semiconductor element. can provide.

なお、本開示は、上述の実施形態の一例に限定されるものではなく、本開示の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば、上述の実施形態の一例においては、配線基板１にソルダーレジストが無い場合を示したが、図３および図４に示すように、配線基板１がソルダーレジスト１３を有していても構わない。この場合、半導体素子Ｓの実装時に配線導体４に加わる熱を緩和して、配線導体４のダメージを低減することが可能になる。また、第１電極１０、第２電極１１、第３電極１２とビルドアップ用絶縁層３との接合性を向上できる点で有利である。 It should be noted that the present disclosure is not limited to the examples of the embodiments described above, and various modifications are possible without departing from the gist of the present disclosure. For example, in the above-described embodiment, the wiring board 1 has no solder resist, but the wiring board 1 may have the solder resist 13 as shown in FIGS. . In this case, the heat applied to the wiring conductors 4 when the semiconductor element S is mounted can be alleviated, and damage to the wiring conductors 4 can be reduced. Moreover, it is advantageous in that the bondability between the first electrode 10, the second electrode 11, the third electrode 12 and the buildup insulating layer 3 can be improved.

ソルダーレジスト１３は、例えば最上層において第１絶縁層３ａの上面から前記第２絶縁層３ｂの上面にかけて位置している。また、最下層においてビルドアップ用絶縁層３の表面に位置している。最上層のソルダーレジスト１３は、第１電極１０の上面中央部を露出する第１開口部１３ａおよび第２電極１１の上面中央部を露出する第２開口１３ｂを有している。また、最下層のソルダーレジスト１３は、第３電極１２の下面中央部を露出する第３開口１３ｃを有している。 The solder resist 13 is located, for example, on the uppermost layer from the upper surface of the first insulating layer 3a to the upper surface of the second insulating layer 3b. Moreover, it is positioned on the surface of the build-up insulating layer 3 as the lowest layer. The uppermost solder resist 13 has a first opening 13 a exposing the center of the upper surface of the first electrode 10 and a second opening 13 b exposing the center of the upper surface of the second electrode 11 . In addition, the lowermost solder resist 13 has a third opening 13 c that exposes the central portion of the lower surface of the third electrode 12 .

ソルダーレジスト１３は、例えばアクリル変性エポキシ樹脂等の感光性を有する熱硬化性樹脂のフィルムを第１絶縁層３ａ、第２絶縁層３ｂおよびビルドアップ用絶縁層３の表面に貼着し、露光および現像により各開口１３ａ、１３ｂ、１３ｃを形成して熱硬化することで形成される。 The solder resist 13 is formed by attaching a photosensitive thermosetting resin film such as an acryl-modified epoxy resin to the surfaces of the first insulating layer 3a, the second insulating layer 3b, and the build-up insulating layer 3, followed by exposure and The openings 13a, 13b, and 13c are formed by development and thermally cured.

また、上述の実施形態の一例においては、第２電極１１の上面と第２絶縁層３ｂの上面とが同じ高さである場合を示したが、図５に示すように、第２電極１１の上面が第２絶縁層３ｂの上面より低くても構わない。この場合、第２電極１１の上面外周部に第２絶縁層３ｂによる壁が位置しているため、半田を第２電極１１上に載置するときの安定向上の点で有利である。さらに、図６に示すように、配線基板１が、第１絶縁層３ａ、第２絶縁層３ｂにかけてソルダーレジスト１３を有していても構わない。この場合も、ソルダーレジスト１３により上記と同様の効果が得られる。 Further, in the above-described embodiment, the upper surface of the second electrode 11 and the upper surface of the second insulating layer 3b are at the same height, but as shown in FIG. The upper surface may be lower than the upper surface of the second insulating layer 3b. In this case, since the wall formed by the second insulating layer 3b is positioned on the outer peripheral portion of the upper surface of the second electrode 11, it is advantageous in terms of improving stability when placing the solder on the second electrode 11. FIG. Furthermore, as shown in FIG. 6, the wiring board 1 may have a solder resist 13 over the first insulating layer 3a and the second insulating layer 3b. In this case as well, the solder resist 13 provides the same effect as described above.

また、図７に示すように、第２電極１１の上面が第２絶縁層３ｂの上面より高くても構
わない。この場合、半田５が第２電極１１の上面に加えて側面の一部にも接着することから半田５と第２電極１１との接続性向上の点で有利である。さらに、図８に示すように、配線基板１が、第１絶縁層３ａ、第２絶縁層３ｂにかけてソルダーレジスト１３を有していても構わない。この場合も、ソルダーレジスト１３により上記と同様の効果が得られる。 Moreover, as shown in FIG. 7, the upper surface of the second electrode 11 may be higher than the upper surface of the second insulating layer 3b. In this case, the solder 5 adheres not only to the upper surface of the second electrode 11 but also to a part of the side surface of the second electrode 11 , which is advantageous in terms of improving connectivity between the solder 5 and the second electrode 11 . Furthermore, as shown in FIG. 8, wiring board 1 may have solder resist 13 over first insulating layer 3a and second insulating layer 3b. In this case as well, the solder resist 13 provides the same effect as described above.

さらに、図９に示すように、半田５が第２電極１１の上面に位置していても構わない。この場合、例えば製造誤差等により半導体素子Ｓの電極Ｐと第２電極１１との間隔が大きくなってしまったときでも、両電極の電気的な接続性確保が容易になるという点で有利である。 Furthermore, as shown in FIG. 9, the solder 5 may be positioned on the upper surface of the second electrode 11. FIG. In this case, even if the distance between the electrode P of the semiconductor element S and the second electrode 11 becomes large due to, for example, a manufacturing error, it is advantageous in that electrical connectivity between the two electrodes can be easily ensured. .

１ 配線基板
３ａ 第１絶縁層
３ｂ 第２絶縁層
８ 第１領域
９ 第２領域
１０ 第１電極
１１ 第２電極
１３ ソルダーレジスト
Ｌ１ 第１間隔
Ｌ２ 第２間隔 1 wiring board 3a first insulating layer 3b second insulating layer 8 first region 9 second region 10 first electrode 11 second electrode 13 solder resist L1 first spacing L2 second spacing

Claims (4)

平面視で互いに隣接する第１領域および第２領域を含んだ上面を有する第１絶縁層と、
前記第１絶縁層の前記第１領域に重なることなく前記第１絶縁層の前記第２領域に位置する第２絶縁層と、
前記第１絶縁層の前記第１領域に互いに第１間隔で位置している複数の第１電極と、
前記第２絶縁層に互いに前記第１間隔よりも小さい第２間隔で位置しており、前記第１電極の上面より小さい面積の上面を有する複数の第２電極と、を有しており、
断面視で前記第２電極の上面は、前記第１電極の上面よりも高い位置にあるとともに、前記第２絶縁層は、前記第２電極のうち側面のみを被覆しており、
断面視で前記第２絶縁層の上面が、前記第１絶縁層の上面よりも高い位置にあることを特徴とする配線基板。 a first insulating layer having an upper surface including a first region and a second region adjacent to each other in plan view ;
a second insulating layer located in the second region of the first insulating layer without overlapping the first region of the first insulating layer;
a plurality of first electrodes positioned at a first distance from each other in the first region of the first insulating layer ;
a plurality of second electrodes positioned on the second insulating layer at a second distance smaller than the first distance from each other and having a top surface with a smaller area than the top surface of the first electrode;
In a cross-sectional view, the upper surface of the second electrode is positioned higher than the upper surface of the first electrode, and the second insulating layer covers only the side surfaces of the second electrode,
A wiring board, wherein the upper surface of the second insulating layer is positioned higher than the upper surface of the first insulating layer in a cross-sectional view. 前記第２電極の上面と前記第２絶縁層の上面とは、断面視で同じ高さであることを特徴とする請求項１に記載の配線基板。 2. The wiring board according to claim 1, wherein the upper surface of said second electrode and the upper surface of said second insulating layer have the same height when viewed in cross section. 前記第１絶縁層の上面から前記第２絶縁層の上面にかけて位置しているとともに、前記第１電極の上面中央部を露出する第１開口部、および前記第２電極の上面中央部を露出する第２開口部を有するソルダーレジストをさらに有していることを特徴とする請求項１または請求項２に記載の配線基板。 A first opening located from the upper surface of the first insulating layer to the upper surface of the second insulating layer and exposing a central portion of the upper surface of the first electrode and a central portion of the upper surface of the second electrode. 3. The wiring board according to claim 1, further comprising a solder resist having a second opening. 前記第１電極および前記第２電極のうち、半田が前記第２電極の上面にのみ位置している請求項１乃至３のいずれかに記載の配線基板。 4. The wiring board according to claim 1, wherein, of the first electrode and the second electrode, solder is positioned only on the upper surface of the second electrode.
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US20030057569A1 (en) 2001-09-26 2003-03-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2003100798A (en) 2001-09-26 2003-04-04 Mitsubishi Electric Corp Semiconductor device
JP2008218505A (en) 2007-02-28 2008-09-18 Sony Corp Substrate and method for manufacturing the same, semiconductor package and method for manufacuting the same, and semiconductor device and method for manufacturing the same
JP2009260255A (en) 2008-03-25 2009-11-05 Panasonic Corp Semiconductor device, multilayer wiring board, and manufacturing method for them
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