JP7334819B2 - Wiring board and semiconductor device having wiring board - Google Patents

Description

TECHNICAL FIELD The present disclosure relates to a wiring substrate that can be used as an interposer, a semiconductor device having the wiring substrate, and methods of manufacturing these.

A semiconductor chip manufactured using a semiconductor substrate such as silicon is mounted on almost all electronic devices and provides various functions to the electronic devices. The semiconductor chip is provided with terminals for inputting power and signals necessary for operation, and is mounted on the main substrate. At this time, a wiring substrate (hereinafter also referred to as an interposer) is provided between the semiconductor chip and the main substrate. An interposer has a substrate and a plurality of wirings as a basic configuration, and the wirings are provided on the substrate in various ways. For example, it is provided as a through wiring formed so as to penetrate the substrate, or as a multi-layer wiring embedded in an insulating film provided on the substrate and arranged to form a plurality of wiring layers. Terminals of the semiconductor chip and wiring on the main substrate are electrically connected through such wiring. For example, Patent Literature 1 discloses an interposer having a multilayer wiring in which a plurality of wirings containing copper are laminated via an insulating film, and a manufacturing method thereof.

International Publication No. 2014/069662

One of the objects of the present disclosure is to provide a wiring board that can be used as an interposer and a manufacturing method thereof. For example, one of the objects of the present disclosure is to provide a wiring substrate that can be applied to a semiconductor device that requires a high operating frequency, such as that used in high-speed communication, a semiconductor device having the wiring substrate, and a manufacturing method thereof. It is to be.

One of the embodiments of the present disclosure is a wiring board. The wiring substrate includes a base film containing an organic compound, a first wiring located on the base film and containing copper, and a first protective film located on the first wiring and in contact with the first wiring. have. The first protective film is a first inorganic compound layer containing silicon nitride, a second inorganic compound layer located on the first inorganic compound layer, in contact with the first inorganic compound layer, and containing silicon oxide; and a third inorganic compound layer located on the second inorganic compound layer, in contact with the second inorganic compound layer, and containing silicon nitride.

One of the embodiments of the present disclosure is a wiring board. The wiring substrate includes a substrate having a first surface and a second surface opposite the first surface, a base film on the substrate, a base film overlying the first surface and embedded in the base film, and comprising copper. a first wiring, a first protective film overlying the first wiring and in contact with the first wiring, a second wiring over the first protective film, and a second wiring over the second wiring; It has a protective film. The first protective film is located on the first inorganic compound layer containing silicon nitride and the first inorganic compound layer, is in contact with the first inorganic compound layer, and contains silicon oxide. The second inorganic compound layer. have The second protective film is a first inorganic compound layer containing silicon nitride, a second inorganic compound layer located on the first inorganic compound layer, in contact with the first inorganic compound layer, and containing silicon oxide; and a third inorganic compound layer located on the second inorganic compound layer, in contact with the second inorganic compound layer, and containing silicon nitride.

1 is a schematic cross-sectional view of a wiring board according to one embodiment; FIG. FIG. 2 is a schematic top view of wiring of a wiring substrate according to one embodiment; FIG. 2 is a schematic top view of wiring of a wiring substrate according to one embodiment; 1 is a schematic cross-sectional view of a wiring board according to one embodiment; FIG. 1 is a schematic cross-sectional view of a wiring board according to one embodiment; FIG. 1 is a schematic cross-sectional view of a wiring board according to one embodiment; FIG. 1 is a schematic cross-sectional view of a wiring board according to one embodiment; FIG. 4A and 4B are schematic cross-sectional views showing a method for manufacturing a wiring board according to one embodiment; 4A and 4B are schematic cross-sectional views showing a method for manufacturing a wiring board according to one embodiment; 4A and 4B are schematic cross-sectional views showing a method for manufacturing a wiring board according to one embodiment; 4A and 4B are schematic cross-sectional views showing a method for manufacturing a wiring board according to one embodiment; 4A and 4B are schematic cross-sectional views showing a method for manufacturing a wiring board according to one embodiment; 4A and 4B are schematic cross-sectional views showing a method for manufacturing a wiring board according to one embodiment; 1 is a schematic cross-sectional view of a semiconductor layer according to one embodiment; FIG. 1 is a schematic cross-sectional view of a semiconductor layer according to one embodiment; FIG. 1 is a schematic cross-sectional view of a semiconductor layer according to one embodiment; FIG.

Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings and the like. However, the present disclosure can be implemented in various aspects without departing from the gist thereof, and should not be construed as being limited to the description of the embodiments illustrated below.

In order to make the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but this is only an example and does not limit the interpretation of the present disclosure. not something to do. In this specification and each figure, elements having the same functions as those described with respect to the previous figures are denoted by the same reference numerals, and redundant description may be omitted.

In this specification and the scope of claims, when expressing a mode in which another structure is placed on top of a structure, unless otherwise specified, when simply using the notation "above" It includes both the case of arranging another structure directly above so as to be in contact with it and the case of arranging another structure above a certain structure via another structure.

In this specification and claims, the expression "a structure is exposed from another structure" means that a part of a structure is not covered by another structure. The portion not covered by the structure also includes a mode covered by another structure.

(First embodiment)
1. Basic Structure A wiring board 100 according to one embodiment of the present disclosure will be described with reference to schematic cross-sectional views of FIGS. 1(A) and 1(B). As shown in FIG. 1A, a wiring board 100 is positioned over a base film 102, first wirings 104 on the base film 102, and first wirings 104, and is in contact with the first wirings 104. 1 protective film 108 .

Base film 102 contains an organic compound. The organic compound to ^be used preferably has ^a low dielectric constant and dielectric loss tangent. An organic compound of 10 ⁻³ or more and 1×10 ⁻² or less can be used as the base film 102 . Such an organic compound is typically a polymer having a polyimide as a basic skeleton (hereinafter simply referred to as polyimide), and the polyimide may be chain-like or intermolecularly crosslinked. The base film 102 may be mixed with epoxy resin, fine particles of silicon oxide, glass fiber, or the like. The base film 102 may have flexibility.

The first wiring 104 can contain metals such as titanium, aluminum, copper, nickel, tungsten, molybdenum, gold, silver, iron, chromium, and alloys thereof, and typically contains copper. The first wiring 104 is arranged partly in the opening provided in the base film 102 and partly covering the upper surface of the base film 102 . The thickness of the portion of the first wiring 104 above the base film 102 can be 0.5 μm or more and 50 μm or less, 1 μm or more and 20 μm or less, or 1 μm or more and 10 μm or less. Although two first wirings 104 are illustrated in FIGS. 1A and 1B, the number of first wirings 104 is not limited.

The planar shape of the first wiring 104 is not restricted and is determined based on the required functions. For example, the first wiring 104 can be provided so as to extend mainly in one direction as shown in FIG. In this case, the width W of the first wiring 104 can be selected in the range of 10 μm to 1000 μm. Alternatively, as shown in FIG. 2B, the first wiring 104 may have a mesh shape. In this case, the width W (that is, the distance between adjacent openings provided in the mesh shape) can be selected within the range of 5 μm or more and 500 μm or less. Alternatively, as shown in FIG. 3, the first wiring 104 may have the same or substantially the same shape as the planar shape of the wiring board 100 . In this case, the width W is selected from a range of greater than 1000 microns and less than or equal to 7 cm.

As shown in FIG. 1A, the first protective film 108 is in contact with the top surface and side surfaces of the first wiring 104 and the top surface of the base film. Also, the first protective film 108 has a three-layer structure. Specifically, the first protective film 108 includes a first inorganic compound layer 108a, a second inorganic compound layer 108b located on the first inorganic compound layer 108a and in contact with the first inorganic compound layer 108a, and a third inorganic compound layer 108c located on the second inorganic compound layer 108b and in contact with the second inorganic compound layer 108b.

The dielectric constant of the second inorganic compound layer 108b is preferably smaller than that of the first inorganic compound layer 108a and the second inorganic compound layer 108b. More specifically, the first inorganic compound layer 108a and the third inorganic compound layer 108c contain silicon nitride or silicon carbide. That is, the first inorganic compound layer 108a and the third inorganic compound layer 108c contain silicon and nitrogen, or silicon and carbon as main constituent elements. On the other hand, the second inorganic compound layer 108b contains silicon oxide or silicon oxynitride. That is, the second inorganic compound layer 108b contains silicon and oxygen as constituent elements, and may further contain nitrogen. When nitrogen is included, its composition is smaller than that of oxygen. These first inorganic compound layer 108a, second inorganic compound layer 108b, and third inorganic compound layer 108c are formed by a chemical vapor deposition (CVD) method (plasma CVD method) in the presence of plasma.

The thicknesses of the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c can be arbitrarily determined. For example, the thickness of the first inorganic compound layer 108a is smaller than the thickness of the second inorganic compound layer 108b and the third inorganic compound layer 108c, for example, 0.05 μm or more and 0.2 μm or less, typically 0.2 μm or less. .1 μm. The thickness of the second inorganic compound layer 108b is larger than the thickness of the first inorganic compound layer 108a and the third inorganic compound layer 108c, and can be 0.5 μm or more and 10 μm or less, or 1 μm or more and 5 μm or less. . The thickness of the third inorganic compound layer 108c can be 0.2 μm or more and 1 μm or less, or 0.3 μm or more and 0.7 μm or less, typically 0.5 μm. That is, when the thicknesses of the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c are respectively T ₁ , T ₂ , and T ₃ , the following relationship is established. One protective film 108 may be configured.
_T1 < _T3 < _T2

As shown in FIG. 1B, the thickness of the second inorganic compound layer 108b may be greater than the thickness of the portion of the first wiring 104 above the base film 102 . In this case, even if the plurality of first wirings 104 are close to each other, the bottom surface of the third inorganic compound layer 108c is located above the top surface of the first wirings 104 between adjacent first wirings 104 . That is, the third inorganic compound layer 108c is not sandwiched between adjacent first wirings 104 in cross section. Therefore, it is possible to prevent a capacitance (parasitic capacitance) from being formed by the first wiring 104 adjacent to the third inorganic compound layer 108c having a relatively high dielectric constant. Further, by making the thickness of the first inorganic compound layer 108a smaller than the thickness of the second inorganic compound layer 108b, a large capacitance is formed by the first wiring 104 adjacent to the first inorganic compound layer 108a. can be prevented at the same time. As a result, it is possible to prevent the generation of parasitic capacitance and the accompanying decrease in signal transmission speed.

As shown in FIGS. 1A and 1B, the first protective film 108 is provided with an opening reaching the first wiring 104 . Thereby, electrical connection is established between the first wiring 104 and another wiring or a semiconductor chip or the like provided on the wiring substrate 100 .

As an optional configuration, the wiring board 100 may have a second protective film 110 on the first protective film 108 . The second protective film 110 may also include a polymer such as polyimide, polyamide, polyester, polycarbonate, polysiloxane, and the like. The material contained in the second protective film 110 and the material contained in the base film 102 may be the same. In this case, due to the difference in impurity concentration, the dielectric constant and dielectric loss tangent of the second protective film 110 may be higher than those of the first protective film 108 .

Further, as an optional configuration, the wiring board 100 may have a lower wiring 112 positioned below the first wiring 104 and electrically connected to the first wiring 104 . The lower wiring 112 is covered with the base film 102 . Similar to the first interconnect 104, the lower interconnect 112 also includes the metals or alloys described above, typically copper. By using the lower wiring 112 and the first wiring 104, the semiconductor chip and the main substrate can be electrically connected.

Seed layers 106 and 114 may be provided in contact with the bottom and side surfaces of the first wiring 104 and the bottom surface of the lower wiring 112, respectively. Seed layers 106, 114 comprise metals such as titanium, nickel, chromium, copper, gold, or alloys thereof, and typically comprise copper. By forming the seed layers 106 and 114, the first wiring 104 and the lower wiring 112 can be formed by electroplating as described later. Although not shown, an additional barrier layer may be provided under each of the seed layers 106 and 114 . More specifically, barrier layers may be provided between the undercoat 118 and the seed layer 114 and between the lower wiring 112 and the seed layer 106, which will be described later. The material contained in the barrier layer is selected from metals such as titanium, tantalum, molybdenum, and tungsten, alloys thereof, and nitrides thereof, and has a higher melting point than the metals contained in the first wiring 104 and the lower wiring 112. It is preferably a conductive material. By providing the barrier layer, the metal contained in the first wiring 104 and the lower wiring 112 can be prevented from diffusing into the base film 102 .

As an additional option, wiring substrate 100 may have substrate 116 below base film 102 . Materials used for the substrate 116 include glass, silicon, gallium arsenide, gallium nitride, ceramics, and composite materials of glass and resin. Examples of resins include epoxy resins, polyimides, polyamides, and polyesters. If substrate 116 is provided, an undercoat 118 may be provided between substrate 116 and base film 102 . The undercoat 118 is a film that has a function of preventing impurities such as metal ions from diffusing from the substrate 116 to the base film 102, and contains, for example, silicon-containing inorganic compounds such as silicon oxide and silicon nitride. The undercoat 118 may have a single layer structure or may be composed of multiple films containing different materials.

When a wiring board is used as an interposer for a semiconductor device that requires a high operating frequency (for example, 1 GHz to 100 GHz) such as a high-frequency element, the insulating film surrounding the wiring of the wiring board has a low density in order to prevent signal transmission loss and delay. Permittivity and dissipation factor are obtained. Even if an insulating film (for example, the base film 102 in the wiring board 100) is formed using a material that satisfies such performance, impurities such as water, oxygen, and metal ions from the outside may cause the insulating film to become contaminated after the wiring board is formed. , and the dielectric constant and dielectric loss tangent of the insulating film gradually increase. As a result, signal transmission loss or delay occurs, which greatly affects the characteristics of the semiconductor chip mounted on the interposer.

On the other hand, in the wiring substrate 100 of this embodiment, the upper surface of the base film 102 covering the first wiring 104 and the lower wiring 112 is covered with the first protective film 108 having a three-layer structure. Here, when the third inorganic compound layer 108c does not exist, the silicon oxide contained in the second inorganic compound layer 108b has relatively high hydrophilicity. It diffuses into the inorganic compound layer 108a. Although the first inorganic compound layer 108a contains silicon nitride, which has a low hydrophilicity and a high blocking property against impurities, as described above, since the thickness is small, the impurities partially permeate. Therefore, impurities penetrate into the base film 102, and the dielectric constant and dielectric loss tangent of the base film 102 increase.

However, in the first protective film 108, a third inorganic compound layer 108c having a thickness greater than that of the first inorganic compound layer 108a and containing silicon nitride is formed on the second inorganic compound layer 108b. Be prepared. Therefore, the speed at which impurities penetrate into the first inorganic compound layer 108a and the base film 102 through the second inorganic compound layer 108b can be significantly reduced, and an increase in the dielectric constant and dielectric loss tangent of the base film 102 can be suppressed. can do. Therefore, it is possible to prevent the transmission loss and delay of the signal of the semiconductor chip mounted on the wiring board 100 .

2. Modifications The structural features described above can also be applied to wiring substrates of various modes. Wiring boards 120, 150, 160, and 170 having different structures from the wiring board 100 will be described below as wiring boards according to the present embodiment.

As shown in FIG. 4, the wiring board 120 has a base film 102 and a plurality of laminated connection wiring layers embedded in the base film 102 . Here, four connection wiring layers including a first connection wiring layer 122, a second connection wiring layer 124, a third connection wiring layer 126, and a fourth connection wiring layer 128 are laminated in the base film 102. Examples are given.

The first connection wiring layer 122 has first connection wirings 130 a and 130 b embedded in the base film 102 . Similarly, the second connection wiring layer 124 has the second connection wiring 132 embedded in the base film 102, and the third connection wiring layer 126 has the third connection wiring 134a embedded in the base film 102. , 134b. The fourth connection wiring layer 128 is provided with the first wirings 104 similarly to the wiring board 100 , and the first protective film 108 is arranged so as to be in contact with the first wirings 104 and the base film 102 . The first wiring 104 is electrically connected to the lower wiring 112 through these connection wirings 130a, 132 and 134a. As with the first wiring 104, in each connection wiring layer, the top surface shapes of the connection wirings 130a, 130b, 132, 134a, and 134b are mainly as shown in FIGS. It may have a shape extending in a one-dimensional direction, may have a mesh shape, or may have substantially the same planar shape as the wiring board 100 . As an optional configuration, seed layers 136a, 136b, 138, 140a, 140b may be provided on the bottom and side surfaces of the connection wirings 130a, 130b, 132, 134a, 134b. A barrier layer may also be formed under each seed layer 136a, 136b, 138, 140a, 140b. Since other configurations are the same as those of the wiring board 100, description thereof is omitted.

Like the wiring substrate 100, the first protective film 108 of the wiring substrate 120 also has the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c. Intrusion of impurities into the base film 102 is effectively suppressed, and an increase in the dielectric constant and dielectric loss tangent of the organic compound contained in the base film 102 can be suppressed.

The wiring board 150 shown in FIG. 5 is a wiring board in that a third protective film 152 having a structure similar to or similar to that of the first protective film 108 is formed on the connection wiring embedded in the base film 102 . different from 120. In the example shown here, the third protective film 152 is provided so as to cover the second connection wiring 132 of the second connection wiring layer 124 . The third protective film 152 is located on the fourth inorganic compound layer 152a, the fourth inorganic compound layer 152a, and is in contact with the fourth inorganic compound layer 152a. It has a sixth inorganic compound layer 152c located on the compound layer 152b and in contact with the fifth inorganic compound layer 152b. The fourth inorganic compound layer 152a, the fifth inorganic compound layer 152b, and the sixth inorganic compound layer 152c are the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108b of the first protective film 108, respectively. 3, and can have the same structure.

By adopting such a structure, even if the number of connection wiring layers increases and the thickness of the base film 102 increases, it is possible to effectively suppress the penetration of impurities into the base film 102. It is possible to prevent deterioration of the characteristics of the semiconductor chip mounted on the wiring board 150 .

Note that the third protective film 152 covering the connection wiring does not necessarily include the sixth inorganic compound layer 152c. This is because the first protective film 108 having a three-layer structure is formed on the first wiring 104 . In this case, the fifth inorganic compound layer 152 b is in contact with the base film 102 .

A wiring board 160 shown in FIG. 6 differs in structure from the wiring board 150 in that the first protective film 108 also covers the side surface of the base film 102 . In this structure, as shown in FIG. 6, the fourth inorganic compound layer 152a and the first inorganic compound layer 108a may be in contact. A first protective film 108 may cover the sides of the substrate 116 . Although not shown, the sides of the base film 102 may not be flush with each other between the connection wiring layers 122 , 124 , 126 and 128 . For example, the side surface of the base film 102 of one connection wiring layer may overlap the top surface of the base film 102 of the connection wiring layer below. By adopting such a structure, it is possible to more effectively prevent the penetration of impurities into the base film 102, so that the increase in the dielectric constant and dielectric loss tangent of the organic compound contained in the base film 102 can be suppressed. It is possible to prevent deterioration of the characteristics of the mounted semiconductor chip.

A wiring board 170 shown in FIG. 7 differs in structure from the wiring board 150 in that the lower wiring 112 is formed as a through wiring penetrating the substrate 116 . That is, the base film 102 and a plurality of connection wiring layers 122, 124, 126, and 128 are formed on one surface (first surface) of the substrate 116, and the lower wiring 112 is part of this first surface. It covers a part of the second surface facing the surface and the side wall of the through hole 172 provided in the substrate 116 . Seed layer 114 similarly covers a portion of the first surface, a portion of the second surface, and sidewalls of through-hole 172 . By using the lower wiring 112 and the first wiring 104, the semiconductor chip and the main substrate can be electrically connected.

As described above, the wiring substrates 150, 160, 170 shown in FIGS. 5 to 7 include one or a plurality of connection wirings selected from a plurality of connection wirings located inside the base film 102. The example has a third protective film 152 in contact with the second connection wiring 132a). That is, metal such as copper included in the connection wiring is in contact with the fourth inorganic compound layer 152a. In this case, when impurities enter the base film 102, the surface of the connection wiring is oxidized, and the adhesion between the connection wiring and the fourth inorganic compound layer 152a is lowered. In addition, since the coefficient of thermal expansion of these connection wirings and the material contained in the fourth inorganic compound layer 152a are significantly different, peeling occurs due to film stress generated between them.

However, as described above, by applying this embodiment, it is possible to effectively prevent impurities from entering the base film 102 . Therefore, the connection wiring is prevented from being oxidized, and peeling of the connection wiring and the third protective film 152 inside the base film 102 can be effectively prevented. Therefore, it is possible not only to suppress the transmission loss and delay of the signal of the semiconductor chip mounted on the wiring board, but also to improve the reliability of the semiconductor device including the semiconductor chip and the wiring board.

(Second embodiment)
In this embodiment, a method for manufacturing the wiring board 170 shown in FIG. 7 will be described with reference to schematic cross-sectional views. Descriptions of configurations similar or identical to those described in the first embodiment may be omitted.

First, a through hole 172 is formed in the substrate 116 (FIG. 8(A)). When a glass substrate is used as the substrate 116, the through holes 172 may be formed by etching such as plasma etching or wet etching, laser irradiation, or mechanical processing such as sandblasting or ultrasonic drilling. The number and size of through-holes 172 can be arbitrarily determined according to the design of wiring board 170 .

Thereafter, the seed layer 114 is formed so as to cover the sidewalls of the through holes 172 and both surfaces (first surface and second surface) of the substrate 116 (FIG. 8B). The seed layer 114 can be formed by a sputtering method, a CVD method, an electroless plating method, a vapor deposition method, or the like. In particular, the seed layer 114 is efficiently formed by applying the sputtering method. Although not shown, prior to the formation of the seed layer 114, a single insulating film containing an organic compound such as polyimide or polyamide, or an inorganic compound such as silicon oxide or silicon nitride is formed on the side walls of the through holes 172 and both surfaces of the substrate 116. A plurality of layers may be formed.

Next, a resist mask 176 is formed on the first and second surfaces of the substrate 116 to protect regions where the lower wiring 112 is not formed (FIG. 8B). The resist mask 176 may be formed by applying and curing a liquid resist, but since the substrate 116 has the through holes 172, a film-like resist is applied to the first surface and the second surface. It can be efficiently formed by pasting, and then performing exposure and development. After that, electric power is supplied to the seed layer 114 to perform electroplating to form a metal film on the seed layer 114 not covered with the resist mask 176, thereby forming the lower wiring 112 (FIG. 8(C)).

After that, the resist mask 176 is removed, and the seed layer 114 exposed from the lower wiring 112 is removed by etching (FIG. 8(D)). As an etchant, an etchant containing an acid such as sulfuric acid can be used.

Subsequently, a portion of the base film 102 is formed. Specifically, the polymer such as polyimide described in the first embodiment, or a solution or suspension of its precursor is applied onto the substrate 116, and then exposed using a photomask, developed, and baked. , form the base film 102 with the opening 178 exposing the lower wiring 112 . Alternatively, the base film 102 may be formed by affixing the above polymer film and performing exposure, development, and baking using a photomask. The thickness of the base film 102 formed at this stage is appropriately adjusted within the range of 0.5 μm to 5 μm.

Next, a seed layer 136 is formed by applying a sputtering method, a CVD method, or the like (FIG. 9A). The thickness of the seed layer 136 is appropriately selected within the range of 5 μm to 20 μm. A seed layer 136 is formed on the base film 102 to partially cover the opening 178 . Before the seed layer 136 is formed, a barrier layer (not shown) may be formed so as to cover the opening 178 and the surface of the base film 102 using a sputtering method or the like.

Next, similarly to the formation of the lower wiring 112, a resist mask is formed and the first connection wiring 130 is formed by electroplating. Remove (FIG. 9(B)). When forming a barrier layer, the barrier layer is removed at the same time as the seed layer 136 . Through the steps up to this point, the first connection wiring layer 122 is formed. A similar process is repeated to form a second connection wiring layer 124 (FIG. 10A).

Next, a third protective film 152 is formed. Specifically, plasma CVD is applied to sequentially form a fourth inorganic compound layer 152a containing silicon nitride and a fifth inorganic compound layer 152b containing silicon oxide (FIG. 10B). After that, the base film 102 having openings overlapping with the second connection wirings 132a is formed on the third protective film 152 (FIG. 11A). The thickness of the base film 102 (the portion of the base film 102 above the third protective film 152) formed at this time is such that the characteristic impedance suitable for the semiconductor chip mounted on the wiring substrate 170 is the first wiring. 104 and the connection wiring, the thickness is appropriately selected from the range of 1 μm to 10 μm.

Next, the third protective film 152 is removed by plasma etching in the opening provided in the uppermost base film 102 to expose the second connection wiring 132a. After that, third connection wirings 134a and 134b and seed layers 140a and 140b are formed using the same method as that for forming the seed layer 136 and the first connection wiring 130a (FIG. 11B). A similar method is repeated to form first wirings 104a and 104b and seed layers 106a and 106b of the fourth connection wiring layer 128 (FIG. 12).

Subsequently, a first protective film 108 is formed (FIG. 13). The first protective film 108 is formed by sequentially forming a first inorganic compound layer 108a, a second inorganic compound layer 108b, and a third inorganic compound layer 108c using a plasma CVD method. After that, similarly to the formation of the base film 102 of the first connection wiring layer 122, after forming the second protective film 110 having an opening overlapping with the first wiring 104a (FIG. 13), the second protective film 110 exposed in this opening is formed. Plasma etching is performed on the protective film 108 of 1 to expose the first wiring 104a. For plasma etching, fluorine-containing alkanes such as CF ₄ and CHF ₄ and alkenes may be used.

Through the above steps, the wiring substrate 170 shown in FIG. 7 can be formed.

(Third embodiment)
In this embodiment, a semiconductor device using the wiring substrates 100, 120, 150, 160, and 170 described in the first embodiment will be described. Here, for the sake of convenience, a semiconductor device using the wiring substrate 170 will be described as a typical example.

A semiconductor device 180 shown in FIG. 14 has a main substrate 182 and a plurality of wiring substrates 170 (wiring substrates 170-1, 170-2, 170-3) laminated thereon. The number of wiring substrates 170 is not limited and is determined according to the performance required of semiconductor device 180 . Various semiconductor chips (memory device, central processing unit) and semiconductor elements (micro-electro-mechanical system (MEMS), etc.), which are not shown, are connected to the main substrate 182 . As described in the first embodiment, the wiring substrate 170 has the lower wirings 112 functioning as through wirings, which contribute to electrical connection in the vertical direction in the semiconductor device 180 . The lower wiring 112 of the lowermost wiring board 170-1 is electrically connected to the terminal 186 provided on the main board 182 via the bump 184-1. The stacked wiring boards 170-1, 170-2 and 170-3 are also electrically connected to each other by bumps 184-2 and 184-3. Bumps 184 include metals such as indium, copper, gold, or alloys such as solder.

As in the semiconductor device 190 shown in FIG. 15, the stacked wiring boards 170 may have different sizes and shapes, and the number of the wiring boards 170 stacked on the main board 182 may also differ. In the example shown in FIG. 15, two wiring boards 170-4 and 170-5 are laminated in a part area, and three wiring boards 170-1, 170-2 and 170-3 are laminated in a part area. It is

A semiconductor device 200 shown in FIG. 16 has a structure in which a plurality of semiconductor chips 202-1 and 202-2 are stacked on a main substrate 182 with wiring substrates 170 interposed therebetween. Terminals 186 are formed on the semiconductor chips 172-1 and 172-2, respectively, and are electrically connected to the lower wiring 112 of the wiring substrate 170 and the first wiring 104 via bumps 184. FIG. Thereby, the semiconductor chips 202-1 and 202-2 are electrically connected to each other. Also, the wire wiring 206 may electrically connect the semiconductor chip 202-2 and the main board 182. FIG. 14 to 16 show that the lower wiring 112 functioning as a through wiring is directly connected to the bump 184, but another wiring such as a lead wiring is provided between the bump 184 and the lower wiring 112. may

In this example, results of a reliability test performed on the wiring board of the first embodiment will be described. The wiring board used was the wiring board 170 (see FIG. 7), and the thicknesses of the fourth inorganic compound layer 152a and the fifth inorganic compound layer 152b were 0.1 μm and 2.0 μm, respectively. The thicknesses of the first inorganic compound layer 108a, the second inorganic compound layer 108b, and the third inorganic compound layer 108c were 0.1 μm, 0.5 μm, and 0.4 μm, respectively.

The fabricated wiring board was allowed to stand under conditions of a temperature of 130° C. and a humidity of 85% for 96 hours, and then the first wiring 104 and the connection wirings 130a, 130b, 132, 134a, and 134b were observed using an optical microscope. As a result, no peeling was observed between the second connection wiring 132 and the fourth inorganic compound layer 152a, regardless of the wiring shape and wiring width.

On the other hand, as a comparative example, when a wiring board having a structure similar to that of the wiring board 170 but not having the first protective film 108 was used, the wirings all had red surfaces regardless of their widths and shapes. Discoloration was confirmed. This suggests that the wiring is oxidized by impurities entering from the outside. Also, between the second connection wiring 132 and the fourth inorganic compound layer 152a, peeling did not occur in a region where the width of the wiring was small (for example, a wiring having a width of 10 μm or less, or a mesh wiring having a width of 5 μm). However, it was confirmed that peeling occurred in other regions.

As shown in this example, it was confirmed that a highly reliable wiring substrate can be provided by applying a protective film having a three-layer structure.

Each of the embodiments described above as embodiments of the present disclosure can be implemented in combination as appropriate as long as they do not contradict each other. In addition, based on each embodiment, addition, deletion, or design change of constituent elements as appropriate by those skilled in the art is also included in the scope of the present disclosure as long as it includes the gist of the present disclosure.

In addition, even if there are other effects that are different from the effects brought about by each of the above-described embodiments, those that are obvious from the description of this specification or those that can be easily predicted by those skilled in the art are of course It is understood that provided by the present disclosure.

100: wiring board, 102: base film, 104: first wiring, 104a: first wiring, 104b: first wiring, 106: seed layer, 106a: seed layer, 106b: seed layer, 108: first 108a: first inorganic compound layer 108b: second inorganic compound layer 108c: third inorganic compound layer 110: second protective film 112: lower wiring 114: seed layer 116 : substrate, 118: undercoat, 120: wiring substrate, 122: first connection wiring layer, 124: second connection wiring layer, 126: third connection wiring layer, 128: fourth connection wiring layer, 130 : first connection wiring 130a: first connection wiring 130b: first connection wiring 132: second connection wiring 132a: second connection wiring 134: third connection wiring 134a: third connection wiring 3 connection wiring, 134b: third connection wiring, 136: seed layer, 136a: seed layer, 136b: seed layer, 138: seed layer, 140a: seed layer, 140b: seed layer, 150: wiring board, 152: Third protective film 152a: fourth inorganic compound layer 152b: fifth inorganic compound layer 152c: sixth inorganic compound layer 160: wiring substrate 170: wiring substrate 172: through hole 176: Resist mask 178: Opening 180: Semiconductor device 182: Main substrate 184: Bump 186: Terminal 188: Bump 190: Semiconductor device 200: Semiconductor device 202: Semiconductor chip 206: Wire wiring

Claims (19)

a base film containing an organic compound,
at least one first wiring containing copper located on the base film; and a first protective film located on the at least one first wiring and in contact with the at least one first wiring. have
The first protective film is
a first inorganic compound layer containing silicon nitride;
a second inorganic compound layer located on the first inorganic compound layer, in contact with the first inorganic compound layer, and containing silicon oxide; and located on the second inorganic compound layer, the second inorganic compound layer, In contact with the inorganic compound layer of 2, including a third inorganic compound layer containing silicon nitride,
The wiring substrate, wherein the thickness of the third inorganic compound layer is larger than the thickness of the first inorganic compound layer and smaller than the thickness of the second inorganic compound layer. The dielectric loss tangent of the organic compound is 1×10 ^-Four more than 1 x 10 ^-2 2. The wiring board according to claim 1, wherein: further comprising a second protective film located on the first protective film and in contact with the first protective film;
2. The wiring substrate according to claim 1, wherein said second protective film contains said organic compound. 2. The wiring board according to claim 1, wherein said organic compound is polyimide. further comprising a second wiring under the at least one first wiring;
the at least one first wiring and the second wiring are electrically connected to each other;
2. The wiring board according to claim 1, wherein said second wiring is covered with said base film. the second wiring is embedded in the base film and covered with a third protective film;
The third protective film is
a fourth inorganic compound layer in contact with the second wiring and containing silicon nitride; and
6. The wiring substrate according to claim 5, located on said fourth inorganic compound layer, in contact with said fourth inorganic compound layer, and containing silicon oxide. the at least one first wiring includes a plurality of first wirings;
2. The wiring substrate according to claim 1, wherein the bottom surface of said third inorganic compound layer is located above the top surface of said at least one first wiring between said adjacent first wirings. 2. The wiring board according to claim 1, wherein said thickness of said second inorganic compound layer is greater than the thickness of a portion of said first wiring above said base film. 2. The wiring board according to claim 1, further comprising a substrate under said base film. The wiring board according to claim 1;
A semiconductor device having a semiconductor chip electrically connected to the wiring substrate. A substrate having a first surface and a second surface opposite the first surface;
a base film on said substrate;
a first trace overlying the first surface and embedded in the base film and comprising copper;
a first protective film located on the first wiring and in contact with the first wiring;
at least one second wiring on the first protective film and the base film; and
a second protective film on the at least one second wiring;
The first protective film is
a first inorganic compound layer containing silicon nitride, and
A second inorganic compound layer located on the first inorganic compound layer, in contact with the first inorganic compound layer, and containing silicon oxide;
The second protective film is
a third inorganic compound layer containing silicon nitride;
A fourth inorganic compound layer located on the third inorganic compound layer, in contact with the third inorganic compound layer, and containing silicon oxide; and
A fifth inorganic compound layer located on the fourth inorganic compound layer, in contact with the fourth inorganic compound layer, and containing silicon nitride;
The wiring board, wherein the thickness of the fifth inorganic compound layer is larger than the thickness of the third inorganic compound layer and smaller than the thickness of the fourth inorganic compound layer. 12. The wiring board according to claim 11, wherein said first wiring is electrically connected to said at least one second wiring. The first wiring is electrically connected to the at least one second wiring via at least one connection wiring,
12. The wiring board according to claim 11, wherein said connection wiring is embedded in said base film. The base film is 1×10 ^-Four more than 1 x 10 ^-2 12. The wiring board according to claim 11, comprising a polyimide having a dielectric loss tangent of: the at least one second wiring includes a plurality of second wirings;
12. The wiring substrate according to claim 11, wherein the bottom surface of said fifth inorganic compound layer is located above the top surface of said at least one second wiring between said adjacent second wirings. 12. The wiring board according to claim 11, wherein the thickness of the fourth inorganic compound layer is greater than the thickness of the portion of the at least one second wiring above the base film. the substrate has a through hole,
a lower wiring covering a side wall of the through hole and at least a part of the second surface of the through hole;
12. The wiring board according to claim 11, wherein said first wiring is electrically connected to said lower wiring. The wiring substrate according to claim 12; and
A semiconductor device having a semiconductor chip electrically connected to the wiring board. 19. The semiconductor device of Claim 18, wherein the semiconductor device is configured to operate as a radio frequency device.

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