JP7172105B2 - Wiring substrate, semiconductor device having wiring substrate, and method for manufacturing semiconductor device - Google Patents

Description

TECHNICAL FIELD The present disclosure relates to a wiring substrate that can be used as an interposer, a semiconductor device having the wiring substrate, and methods of manufacturing these.

A semiconductor chip manufactured using a semiconductor substrate such as silicon is mounted on almost all electronic devices and provides various functions to the electronic devices. A semiconductor chip is provided with terminals for inputting power and signals necessary for operation, and is mounted on a main board such as a printed wiring board. A method called fan-out wafer level packaging (FOWLP) is known as one of the methods for mounting semiconductor chips. In this mounting method, a wiring board (hereinafter also referred to as an interposer) provided with a wiring layer formed over an area larger than that of the semiconductor chip is used, and the semiconductor chip is mounted on the main board via the interposer. For example, Patent Document 1 discloses a semiconductor device to which FOWLP is applied and a manufacturing method thereof.

JP 2017-085028 A

Chien-Fu Tseng, Chung-Shi Liu, Chi-Hsi Wu, Douglas Yu, InFO (Wafer Level Integrated Fan-Out ) Technology (InFO (Wafer Level Integrated Fan-Out) Technology), 2016 IEEE 66th Electronic Components and Technology Conference, USA, June 2016, pp1-6

One object of the present disclosure is to provide a wiring board applicable to FOWLP, a semiconductor device including the same, and a manufacturing method thereof. For example, one of the objects of the present disclosure is to provide a wiring substrate that can be applied to a semiconductor device that requires a high operating frequency, such as that used in high-speed communication, a semiconductor device having the wiring substrate, and a manufacturing method thereof. It is to be.

One of the embodiments of the present disclosure is a wiring board. The wiring substrate includes first to n-th wirings electrically connected to each other, an insulating film embedding the first to n-th wirings, a wiring substrate positioned on the insulating film, being in contact with the insulating film, and containing at least silicon nitride and oxide. It has a first protective film containing any one of silicon and a connection pad located on the first protective film and electrically connected to the nth wiring. The first to nth wirings are stacked such that the (k+1)th wiring selected from the first to nth wirings is positioned on the kth wiring. n is a natural number greater than 1, and k is a natural number smaller than n.

One embodiment of the present disclosure is a method of making a semiconductor device. This method sequentially repeats forming a wiring on a substrate, forming an insulating film on the wiring, and forming an opening for exposing the wiring in the insulating film, thereby embedding the wiring in the insulating film and providing an electric connection to each other. sequentially forming first to n-th wirings which are electrically connected to each other; forming a first protective film on the insulating film; Forming a connection pad electrically connected to the nth wire and isolating the substrate from the first wire. The first protective film contains at least one of silicon nitride and silicon oxide.

1A and 1B are schematic top and bottom views of a wiring board and a semiconductor device according to one embodiment; FIG. 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device according to one embodiment; FIG. 2 is a schematic top view of wiring of a wiring substrate according to one embodiment; FIG. 2 is a schematic top view of wiring of a wiring substrate according to one embodiment; 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device according to one embodiment; 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device according to one embodiment; 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device according to one embodiment; 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device according to one embodiment; 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device according to one embodiment; 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device according to one embodiment; 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device according to one embodiment; 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device according to one embodiment; 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device according to one embodiment; 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device according to one embodiment; 4A to 4C are schematic cross-sectional views showing a method for manufacturing a wiring substrate and a semiconductor device according to one embodiment; 4A to 4C are schematic cross-sectional views showing a method for manufacturing a wiring substrate and a semiconductor device according to one embodiment; 4A to 4C are schematic cross-sectional views showing a method for manufacturing a wiring substrate and a semiconductor device according to one embodiment; 4A to 4C are schematic cross-sectional views showing a method for manufacturing a wiring substrate and a semiconductor device according to one embodiment; 4A to 4C are schematic cross-sectional views showing a method for manufacturing a wiring substrate and a semiconductor device according to one embodiment; 4A to 4C are schematic cross-sectional views showing a method for manufacturing a wiring substrate and a semiconductor device according to one embodiment; 1A and 1B are schematic cross-sectional views of a wiring substrate and a semiconductor device used in Examples.

Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings and the like. However, the present disclosure can be implemented in various aspects without departing from the gist thereof, and should not be construed as being limited to the description of the embodiments illustrated below.

In order to make the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but this is only an example and does not limit the interpretation of the present disclosure. not something to do. In this specification and each figure, elements having the same functions as those described with respect to the previous figures are denoted by the same reference numerals, and redundant description may be omitted.

In this specification and the scope of claims, when expressing a mode in which another structure is placed on top of a structure, unless otherwise specified, when simply using the notation "above" It includes both the case of arranging another structure directly above so as to be in contact with it and the case of arranging another structure above a certain structure via another structure.

In this specification and claims, the expression "a structure is exposed from another structure" means that a part of a structure is not covered by another structure. The portion not covered by the structure also includes a mode covered by another structure.

In this specification and drawings, when a plurality of constituent elements are individually indicated, they are indicated using a hyphen and a natural number after the symbol. Only symbols are used when not distinguishing each of a plurality of constituent elements and describing the entirety or an arbitrarily selected constituent among them.

(First embodiment)
1. Basic Structure Schematic top and bottom views of a wiring board 110 according to one embodiment of the present disclosure and a semiconductor device 100 having the wiring board 110 are shown in FIGS. A cross-sectional view is shown in FIG. As shown in FIG. 2A, semiconductor device 100 includes wiring board 110 and semiconductor chip 200 electrically connected to wiring board 110 . As an optional configuration, semiconductor device 100 may include main substrate 140 . The main substrate 140 has connection pads 142 through which the wiring substrate 110 and the main substrate 140 are electrically connected.

The wiring board 110 has a plurality of wirings (first wiring 112-1 to n-th wiring 112-n, where n is a natural number greater than 1) 112 which are laminated and electrically connected to each other. Each of the wirings 112 is wholly or partly embedded within an insulating film (also called a base film) 102 . The number of layers (that is, n) of the wiring 112 is not restricted, and can be arbitrarily determined in consideration of the number of terminals of the semiconductor chip 200, the number of connection pads 142 of the main substrate 140, and the like. FIG. 2A shows an example in which n is 5, and the wiring substrate 110 includes first to fifth wirings (112-1, 112-2, 112-3, 112-4, 112-1, 112-2, 112-3, 112-4, 112-5). The first wiring 112-1 is positioned at the bottom and the nth wiring 112-5 is positioned at the top. That is, the wiring 112 is stacked such that the (k+1)th wiring selected from the first to nth wirings is positioned on the kth wiring (k is a natural number smaller than n). Further, as shown in FIG. 2A, the wiring 112 is arranged so that the layout area becomes smaller as the value of n increases. That is, the area of the region in which the kth wiring is arranged is larger than the area of the region in which the (k+1)th wiring is arranged. With this structure, the terminals of the wiring substrate 110 for connection to the main substrate 140, that is, the first wirings 112-1 can be arranged at positions not overlapping the semiconductor chip 200 as well. As shown in FIG. 2A, it is preferable that at least a part of the (k+1)-th wiring be configured to be thinner as it approaches the k-th wiring.

The wiring substrate 110 is further provided with a first protective film 114 on and in contact with the n-th wiring 112-n and the (first insulating film) insulating film 102 . The first protective film 114 is composed of one or more films and contains at least one of silicon nitride and silicon oxide. The first protective film 114 has a function of preventing impurities such as water and oxygen from entering the insulating film 102 from the outside.

Part of the side surface and the upper surface of the n-th wiring 112-n are exposed from the insulating film 102. As shown in FIG. The thickness of the portion of the n-th wiring 112-n above the insulating film 102 can be 0.5 μm to 10 μm, 1 μm to 5 μm, or 1 μm to 3 μm. A part of the upper surface and side surfaces of the n-th wiring 112-n are covered with the first protective film 114, the other part of the upper surface is exposed from the first protective film 114, and the n-th wiring 112-n is electrically connected to a connection pad 116 provided on the . As with the wiring 112, the connection pad 116 is preferably configured such that at least a portion thereof becomes thinner as it approaches the nth wiring 112-n.

A semiconductor chip 200 is electrically connected to the connection pads 116 via bumps 202, which have an arbitrary configuration. If the bumps 202 are not used, the terminals of the semiconductor chip 200 and the connection pads 116 may be connected by solid phase bonding, for example. Semiconductor chip 200 can have any configuration and functionality, such as central processing unit (CPU), application specific integrated circuit (ASIC), graphics processing unit (GPU), field-programmable gate array (FPGA), and other logic. It is selected from memory such as LSI, DRAM, and flash memory. In the examples shown in FIGS. 1A and 2A, logic LSI 200-1 and memory 200-2 are arranged on wiring board 110. In FIG. These semiconductor chips 200 are sealed with a resin (mold resin) 204 such as epoxy resin, acrylic resin, novolak resin, phenol resin, benzocyclobutene resin, or the like.

On the other hand, the bottom surface of the first wiring 112 - 1 is exposed from the insulating film 102 and electrically connected to the bump 120 at the bottom surface. The wiring board 110 can be connected to the connection pads 142 of the main board 140 via the bumps 120 , so that the semiconductor chip 200 can be mounted on the main board 140 . A known printed wiring board (printed board) or the like can be used as the main board 140 .

As understood from FIGS. 1B and 2A, the area where the first wiring 112-1 is arranged is larger than the area occupied by the semiconductor chip 200. FIG. Therefore, the terminals can be extended to the outside of the semiconductor chip 200, and not only can they be connected to a large number of connection pads 142 provided on the main substrate 140, but also the main substrate 140 can be connected even if the semiconductor chip 200 is miniaturized. can be easily electrically connected to

Each configuration will be described below.

2. Insulating Film The insulating film 102 contains an organic compound. The organic compound used preferably has a low dielectric ^constant and a low dielectric loss ^tangent . An organic compound of 10 ⁻³ to 1×10 ⁻² can be used as the insulating film 102 . Such an organic compound is typically a polymer having a polyimide as a basic skeleton (hereinafter simply referred to as polyimide), and the polyimide may be chain-like or intermolecularly crosslinked. The insulating film 102 may have flexibility.

3. Wiring FIG. 2B shows a schematic cross-sectional view of part of the wiring 112 . As will be described later, the wiring 112 can be formed using an electrolytic plating method. In this case, each wiring 112 has a seed layer 136 and a plated layer 137 on the seed layer 136, as shown in FIG. 2B. Seed layer 136 includes metals such as titanium, nickel, chromium, copper, gold, or alloys thereof, and typically includes copper. The plating layer 137 can contain metals such as titanium, aluminum, copper, nickel, tungsten, molybdenum, gold, silver, iron, chromium, and alloys thereof, and typically contains copper. Although not shown, additional barrier layers may be provided under each seed layer 136 . The material contained in the barrier layer is selected from metals such as titanium, tantalum, molybdenum and tungsten, their alloys, or nitrides thereof, and is conductive with a higher melting point than the metal contained in the seed layer 136 and the plating layer 137. Materials are preferred. By providing the barrier layer, the metal contained in the wiring 112 can be prevented from diffusing into the insulating film 102 .

The planar shape of the wiring 112 is not restricted and is determined based on the required functions. For example, the wiring 112 can be provided so as to extend mainly in one direction as shown in FIG. In this case, the width W of the wiring 112 can be selected within the range of 10 μm to 1000 μm. Alternatively, as shown in FIG. 3B, the wiring 112 may have a mesh shape. In this case, the width W (that is, the distance between adjacent openings provided in the mesh shape) can be selected within the range of 5 μm or more and 500 μm or less. Alternatively, as shown in FIG. 4, the wire 112 may be rectangular with a width W selected from the range greater than 1000 μm and less than or equal to 7 cm. In this case, the wiring 112 may have the same or substantially the same planar shape as the wiring substrate 110 .

4. Protective Film As described above, the first protective film 114 includes one of silicon nitride and silicon oxide. The first protective film 114 is preferably formed by chemical vapor deposition (plasma CVD) in the presence of plasma. Accordingly, the dense first protective film 114 can be formed on the insulating film 102, and a high blocking property against impurities can be imparted.

5. MODIFIED EXAMPLE As shown in FIG. 5, the wiring board 110 may be provided with not only the first protective film 114 but also the second protective film 118 under the insulating film 102 . The second protective film 118 also contains one of silicon nitride and silicon oxide, and is preferably formed by plasma CVD. In this case, part of the bottom surface of the first wiring 112-1 and the bottom surface of the insulating film 102 are in contact with the second protective film 118, and the other part of the bottom surface of the first wiring 112-1 is the second protective film. It is exposed from film 118 and electrically connected to bump 120 .

There is no restriction on the vertical relationship between the n-th wiring 112-n and the first protective film 114. FIG. For example, as shown in FIG. 6A, which is a cross-sectional view of the (n−1)th wiring 112-(n−1) and the nth wiring 112-n, the nth wiring 112-n is connected to the first wiring 112-n. It may be provided on the protective film 114 so as to be in contact with the first protective film 114 . In this case, the first protective film 114 is positioned between the (n−1)th wiring 112-(n−1) and the nth wiring 112-n. The first protective film 114 is provided on the insulating film 102 and may cover the sidewall of the opening exposing the top surface of the (n-1)th wiring 112-(n-1) (FIG. 6A). Alternatively, as shown in FIG. 6B, the sidewall may be in contact with the nth wiring 112-n. Alternatively, as shown in FIG. 6C, the first protective film 114 and the nth wiring 112-n are formed on the insulating film 102 so that the side surface of the first protective film 114 is in contact with the nth wiring 112-n. may be configured.

The coefficient of thermal expansion of metal such as copper used for the wiring 112 is larger than that of the material included in the first protective film 114 . For example, the coefficient of thermal expansion of copper is 16 ppm or more, and the coefficient of thermal expansion of silicon nitride or silicon oxide is 3 ppm or less. Therefore, in the structure shown in FIG. 5, that is, when the first protective film 114 is provided over the n-th wiring 112-n, the first protective film 114 is in contact with the n-th wiring 112-n and , cracks are likely to occur at the bent portion (for example, region 114a in FIG. 5). However, by adopting the structures shown in FIGS. 6A to 6C, the damage to the first protective film 114 due to the thermal expansion of the n-th protective film is reduced, thereby suppressing the occurrence of cracks. can do.

Alternatively, as shown in FIG. 7A, a second insulating film 104 may be provided over the first protective film 114 . Second insulating film 104 can include materials that can be used in insulating film 102 . The impurity concentration in the second insulating film 104 may be higher than that in the insulating film 102, so the dielectric constant and dielectric loss tangent of the second insulating film 104 may be higher than those in the insulating film 102. . The second insulating film 104 is provided with an opening that exposes the nth wiring 112-n, and the wiring substrate 110 is electrically connected to the connection pad 116, the bump 202, or the semiconductor chip 200 through this opening. Also, as shown in FIG. 7B, the side surface of the first protective film 114 may form the side wall of this opening. That is, the sidewall of the opening of the second insulating film 104 and the side surface of the first protective film 114 can be positioned on the same plane. By using such a structure, the bumps 202 can be stably held in the openings, so that stable electrical connection with the semiconductor chip 200 can be achieved without using the connection pads 116. Reliability can be improved.

As shown in FIG. 7C, it is possible to stably hold the bump 202 by providing the first protective film 114 with inclined side surfaces without providing the second insulating film 104 . .

A similar configuration can be applied to the second protective film 118 as well. For example, as shown in FIG. 8A, the second protective film 118 may be provided over the first wiring 112-1 so as to be in contact with the first wiring 112-1. In this case, the second protective film 118 is positioned between the first wiring 112-1 and the second wiring 112-2. The second protective film 118 is provided with an opening that exposes the upper surface of the first wiring 112-1, and the first wiring 112-1 and the second wiring 112-2 are electrically connected in this opening. . Further, a third insulating film 106 may be provided under the first wiring 112-1 and the insulating film 102 as shown in FIG. 8B. The third insulating film 106 is also provided with an opening that exposes the lower surface of the first wiring 112-1. Like the second insulating film 104 , the third insulating film 106 can also include materials that can be used in the insulating film 102 and may have higher dielectric constants and loss tangents than those of the insulating film 102 .

In such a structure, as compared with the structure shown in FIG. 5, the area of the interface between the first wiring 112-1 and the second protective film 118 can be increased. It can lengthen the entry path. Therefore, it is possible to prevent an increase in the dielectric constant and dielectric loss tangent of the insulating film 102 due to water entering from the outside.

Alternatively, the third insulating film 106 may be provided under the first wiring 112-1 and the insulating film 102 as shown in FIG. 9A. The second protective film 118 may be exposed in an opening provided in the third insulating film 106, or as shown in FIG. The third insulating film 106 and the second protective film 118 may be configured such that the side surfaces of the film 118 are coplanar. Similar to the structure shown in FIGS. 7A to 7C, by applying such a structure, the bumps 120 can be stably held, and stable electrical connection with the main substrate 140 can be achieved. It becomes possible. As a result, reliability of the semiconductor device 100 can be improved.

The first protective film 114 and the second protective film 118 may have a multilayer structure. For example, as shown in FIG. 10A, the first protective film 114 is positioned on the first inorganic film 114-1 and the first inorganic film 114-1, and the first inorganic film 114-1 and the first protective film 114-1. It has a three-layer structure including a contacting second inorganic film 114-2 and a third inorganic film 114-3 positioned on the second inorganic film 114-2 and contacting the second inorganic film 114-2. be able to.

The dielectric constant of the second inorganic film 114-2 is preferably smaller than that of the first inorganic film 114-1 and the third inorganic film 114-3. More specifically, the first inorganic film 114-1 and the third inorganic film 114-3 contain silicon nitride or silicon carbide. That is, the first inorganic film 114-1 and the third inorganic film 114-3 contain silicon and nitrogen, or silicon and carbon as main constituent elements. On the other hand, the second inorganic film 114-2 contains silicon oxide or silicon oxynitride. That is, the second inorganic film 114-2 contains silicon and oxygen as constituent elements, and may further contain nitrogen. When nitrogen is included, its composition is smaller than that of oxygen. These first inorganic film 114-1, second inorganic film 114-2 and third inorganic film 114-3 are formed by plasma CVD.

The thickness of the first inorganic film 114-1 may be smaller than the thickness of the second inorganic film 114-2 or the third inorganic film 114-3. In practice, it can be 0.2 μm. The thickness of the second inorganic film 114-2 may be greater than the thicknesses of the first inorganic film 114-1 and the third inorganic film 114-3, and may be 0.5 μm to 10 μm, or 1 μm to 5 μm. can be: The thickness of the third inorganic film 114-3 can be 0.2 μm or more and 1 μm or less, or 0.3 μm or more and 0.7 μm or less, typically 0.5 μm. That is, when the thicknesses of the first inorganic film 114-1, the second inorganic film 114-2, and the third inorganic film 114-3 are respectively T ₁ , T ₂ , and T ₃ , the following relationship holds. The first protective film 114 can be configured as follows.
_T1 < _T3 < _T2

FIG. 10B shows a schematic cross-sectional view of the n-th wiring 112-n and the first protective film 114 having a three-layer structure. The thickness of the second inorganic film 114-2 may be smaller than the thickness of the portion where the n-th wiring 112-n is exposed from the insulating film 102, or as shown in FIG. may be greater than the thickness of In this case, even if a plurality of n-th wirings 112-n are close to each other, the bottom surface of the third inorganic film 114-3 is the top surface of the n-th wiring 112-n between the adjacent n-th wirings 112-n. located above. That is, in cross section, the third inorganic film 114-3 is not sandwiched between adjacent n-th wirings 112-n. Therefore, it is possible to prevent a capacitance (parasitic capacitance) from being formed by the n-th wiring 112-n adjacent to the third inorganic film 114-3 having a relatively high dielectric constant. Further, by making the thickness of the first inorganic film 114-1 smaller than the thickness of the second inorganic film 114-2, a large At the same time, the formation of capacitance can also be prevented. As a result, it is possible to prevent the generation of parasitic capacitance and the accompanying decrease in signal transmission speed.

It is also possible to apply such a three-layer structure to the second protective film 118 . Specifically, as shown in FIG. 11, the second protective film 118 is positioned under the insulating film 102 and is in contact with the insulating film 102. The fourth inorganic film 118-1, the fourth inorganic film 118-1 A fifth inorganic film 118-2 located below and in contact with the fourth inorganic film 118-1, and a fifth inorganic film 118-2 located below and in contact with the fifth inorganic film 118-2. It can have a three-layer structure including a sixth inorganic film 118-3. The fourth inorganic film 118-1, the fifth inorganic film 118-2, and the sixth inorganic film 118-3 are the first inorganic film 114-1, the second inorganic film 114-2, and the third inorganic film 114-2, respectively. Corresponding to the film 114-3, the relationship of composition and thickness, and the formation method are the same as those of the first inorganic film 114-1, the second inorganic film 114-2, and the third inorganic film 114-3. is.

As shown in FIG. 12, the first protective film 114 may be formed to cover the side surfaces of the insulating film 102 . In this case, the second protective film 118 can be provided so as to be in contact with the first protective film 114 . By adopting such a structure, it is possible to effectively prevent impurities from entering the insulating film 102 .

As shown in FIG. 13, the wiring substrate 110 further includes a third wiring 112 located on at least one wiring 112 selected from the first to (n−1)th wirings 112 and in contact with the selected wiring 112. It may have a protective film 122 . A third protective film 122 exists within the insulating film 102 . The third protective film 122 may also have either a single layer structure or a laminated structure. When having a laminated structure, the third protective film 122 includes, for example, silicon nitride, and is located on the seventh inorganic film 122-1 in contact with the selected wiring 112 and the seventh inorganic film 122-1. and an eighth inorganic film 122-2 containing silicon oxide. These inorganic films 122 also correspond to the first inorganic film 114-1 and the second inorganic film 114-2, respectively. 2 of the inorganic film 114-2. Although not shown, the third protective film 122 further includes a ninth inorganic film containing silicon nitride located on the eighth inorganic film 122-2 and in contact with the eighth inorganic film 122-2. may

When the first protective film 114 covers the side surfaces of the insulating film 102, the first inorganic film 114-1 is in contact with the side surfaces of the seventh inorganic film 122-1 and the eighth inorganic film 122-2. A protective film 114 may be provided (see FIG. 14).

By forming the third protective film 122 having such a structure, even if the number of stacked wirings 112 increases and the thickness of the insulating film 102 increases, it is possible to prevent impurities from entering the insulating film 102 . can be effectively suppressed.

2A, 5, 10A, and 11 to 14, the bumps 120 connected to the first wiring 112-1 are connected to the main substrate 140, There is no other substrate such as a package substrate between the wiring 112-1 or the insulating film 102 and the main substrate 140. FIG. Therefore, the wiring board 110 of this embodiment can be used as a thin interposer or a flexible interposer, which contributes to making the semiconductor device 100 thinner.

Moreover, the wiring substrate 110 can be used as an interposer for a semiconductor device such as a high-frequency element that requires a high operating frequency. When a wiring board is used for a high-frequency device, the insulating film surrounding the wiring of the wiring board is required to have a low dielectric constant and a low dielectric loss tangent in order to prevent signal transmission loss and delay. Even if an insulating film (for example, the insulating film 102 in the wiring substrate 110) is formed using a material that satisfies such performance, impurities such as water, oxygen, and metal ions from the outside may cause the insulating film to become contaminated after the wiring substrate is formed. , and the dielectric constant and dielectric loss tangent of the insulating film gradually increase. As a result, signal transmission loss or delay occurs, which greatly affects the characteristics of the semiconductor chip mounted on the interposer.

However, as described above, in the wiring board 110 of the present embodiment, the first protective film 114 and the second protective film 118 in contact with the insulating film 102 or at least one of the plurality of wirings 112 within the insulating film 102 is covered. A third protective film 122 and the like are provided. As a result, it is possible to effectively suppress an increase in the dielectric constant and dielectric loss tangent of the insulating film 102 due to the intrusion of impurities, thereby preventing signal transmission loss and delay in the semiconductor chip mounted on the wiring board 110 . becomes possible.

Moreover, if these protective films further have the above-described three-layer structure, the penetration of impurities can be suppressed more effectively, and the reliability of the semiconductor device 100 can be greatly improved as described below. Since the silicon oxide contained in the second inorganic film 114-2 is relatively hydrophilic, when impurities such as water enter from the outside, the impurities diffuse into the first inorganic film 114-1. Although the first inorganic film 114-1 contains silicon nitride, which has low hydrophilicity and high blocking property against impurities, if the thickness is formed small, impurities may partially permeate. When impurities enter the insulating film 102, the surface of the wiring 112 is oxidized by water, oxygen contained therein, metal ions, etc. As a result, the adhesion between the third protective film 122 and the wiring 112 covered by it is reduced. decreases. Since the wiring 112 and the seventh inorganic film 122-1 included in the third protective film 122 have significantly different coefficients of thermal expansion, film stress generated therebetween results in peeling.

However, the first protective film 114 includes a third inorganic film containing silicon nitride on the second inorganic film 114-2 so as to have a greater thickness than the first inorganic film 114-1. 114-3 can be provided. Therefore, the speed at which impurities enter the first inorganic film 114-1 and the insulating film 102 through the second inorganic film 114-2 can be greatly reduced, and the wiring 112 and the seventh inorganic film 122-1 can be prevented from entering. It can effectively prevent delamination. Therefore, it is possible to prevent the occurrence of defects caused by peeling, and as a result, the reliability of the semiconductor device 100 can be improved.

(Second embodiment)
In this embodiment, a method for manufacturing the wiring board 110 shown in FIG. 11 and the semiconductor device 100 including the wiring board 110 will be described. Descriptions of configurations similar or similar to those of the first embodiment may be omitted.

First, a peeling layer 132 is formed over a supporting substrate 130, and a bonding layer 134 is further formed thereover (FIG. 15A). As the supporting substrate 130, a substrate containing glass, quartz, or the like may be used. The separation layer 132 can be formed using a CVD method or a sputtering method using a film containing a metal such as tungsten or molybdenum. Alternatively, the peeling layer 132 may be formed using a photosensitive organic peeling material having an acrylic resin or silicone resin as a basic structure, or an organic peeling material that can be mechanically peeled. The bonding layer 134 can be formed, for example, using a polysiloxane-based high molecular compound by applying a spin coating method, a dip coating method, or the like.

Next, a second protective film 118 is formed (FIG. 15B). Specifically, on the bonding layer 134, a sixth inorganic film 118-3 containing silicon nitride, a fifth inorganic film 118-2 containing silicon oxide, and a fourth inorganic film 118-1 containing silicon nitride are formed. are sequentially formed using plasma CVD. As described above, the fourth inorganic film 118-1, the fifth inorganic film 118-2, and the sixth inorganic film 118-3 are the first inorganic film 114-1 and the second inorganic film 114-3, respectively. 2, corresponding to the third inorganic film 114-3. Therefore, the thickness of the sixth inorganic film 118-3 can be set to 0.2 μm or more and 1 μm or less, or 0.3 μm or more and 0.7 μm or less, typically 0.5 μm. The thickness of the fifth inorganic film 118-2 can be set to 0.5 μm or more and 10 μm or less, or 1 μm or more and 5 μm or less. The thickness of the sixth inorganic film 118-3 can be set to 0.05 μm or more and 0.2 μm or less, typically 0.1 μm.

Next, a seed layer 136 is formed on the second protective film 118 by applying a sputtering method, a CVD method, an electroless plating method, a vapor deposition method, or the like. Particularly, by applying the sputtering method, the seed layer 136 can be efficiently formed. Although not shown, a barrier layer may be formed before the seed layer 136 is provided. After that, a resist mask 138 is formed in a region where the first wiring 112-1 is not formed (FIG. 15C)). The resist mask 138 may be formed by applying and curing a liquid resist, but may also be formed by applying a film-like resist onto the seed layer 136 and then performing exposure and development. After that, electric power is supplied to the seed layer 136 to perform electroplating to form a metal film on the seed layer 136 not covered with the resist mask 138, thereby forming the first wiring 112-1. Thereafter, the resist mask 138 is removed by ashing or the like, and the seed layer 136 and the barrier layer not covered with the first wiring 112-1 are removed by etching. As an etchant, an etchant containing an acid such as sulfuric acid can be used. Thus, a first wiring 112-1 is formed (FIG. 16A).

Subsequently, part of the insulating film 102 is formed to cover the first wiring 112-1. Specifically, the solution or suspension of the photosensitive polymer having the basic skeleton of polyimide as described in the first embodiment, or a solution or suspension of its precursor is applied onto the support substrate 130, and then exposed and developed using a photomask. , baking is performed to form a part of the insulating film 102 having the opening 144 exposing the first wiring 112-1. Alternatively, part of the insulating film 102 may be formed by attaching the polymer film, and performing exposure, development, and baking using a photomask. The thickness of the insulating film 102 formed at this stage is appropriately adjusted within the range of 0.5 μm to 5 μm. As shown in FIG. 16B, opening 144 is preferably formed to have a forward tapered structure. That is, it is preferable that at least a part of the (k+1)-th wiring be formed so as to become thinner as it approaches the k-th wiring.

Subsequently, similar to the formation of the first wiring 112-1, a barrier layer and a seed layer 136 are formed in the opening and the upper surface of the insulating film 102, a resist mask is formed, and then electroplating, removal of the resist mask, and barrier layer 136 are performed. A second wiring 112-2 is formed by partially removing the film and the seed layer 136 (FIG. 16(C)). By repeating this process, the second wiring 112-2 to the n-th wiring 112-n are formed (FIG. 17A). For the sake of clarity, FIG. 16C does not show the seed layer 136 of the second wiring 112-2, and FIGS. 17A to 20 do not show the seed layer 136 at all.

Next, a first protective film 114 is formed (FIG. 17B). The first protective film 114 is formed by sequentially forming a first inorganic film 114-1, a second inorganic film 114-2, and a third inorganic film 114-3 using plasma CVD. After that, using plasma etching, an opening overlapping with the nth wiring 112-n is provided in the first protective film 114 to expose the nth wiring 112-n (FIG. 18A). Plasma etching may be performed using, for example, fluorine-containing alkanes such as CF ₄ and CHF ₄ and alkenes. This opening also preferably has a forward tapered structure.

After that, using the same technique as that for forming the first to n-th wirings 112, connection pads 116 are formed so as to cover the openings (FIG. 18B). When the opening is formed to have a forward tapered structure, part of the connection pad becomes narrower as it approaches the n-th wiring 112-n.

After that, the semiconductor chip 200 is electrically connected to the connection pads 116 using bumps 202 containing a conductive material such as solder. Solder balls formed by, for example, a capillary flow method, a thermal compression bonding method, or the like are formed as bumps 202 to electrically connect the semiconductor chip 200 and the wiring board 110 . After that, the semiconductor chip 200 is sealed using the resin 204 described above (FIG. 19).

Subsequently, light irradiation is performed from the support substrate 130 side using a light source such as a flash lamp or laser to reduce the adhesive strength at the interface between the release layer 132 and the support substrate 130 or at the interface between the release layer 132 and the bonding layer 134 ( See Figure 19). After that, the support substrate 130 is peeled off using physical force. Furthermore, the bonding layer 134 is dissolved using a chemical solution such as an alkaline aqueous solution to expose the second protective film 118 . After that, the second protective film 118 is etched to form an opening for exposing the first wiring 112-1 (FIG. 20). Although not shown, this opening may also be formed to have a forward tapered structure. That is, the opening may be formed so that the area of the opening becomes smaller as it approaches the first wiring 112-1. Similar to the connection between the semiconductor chip 200 and the connection pads 116, solder balls formed by a capillary reflow method, a thermal compression bonding method, or the like are used as the bumps 120, and the connection pads 142 formed on the main substrate 140 and the first connection pads 142 are connected. An electrical connection is made with the wiring 112-1 (FIG. 11). Through the above steps, the wiring board 150 and the semiconductor device 100 including the wiring board 150 can be manufactured.

Generally, in the FOWLP method, first, a semiconductor chip is placed on a support substrate and sealed with resin. After that, the support substrate is peeled off to form a pseudo wafer. Subsequently, a wiring board is formed on the pseudo wafer by laminating wiring on the terminals of the semiconductor chip exposed by peeling. However, although precise wiring patterning is required to form a wiring substrate, wiring patterning is not necessarily easy when using a pseudo wafer because the patterning accuracy is greatly affected by the properties of the resin.

On the other hand, according to the manufacturing method described in the present embodiment, wiring patterning can be performed using the support substrate 130 having high flatness and rigidity, so precise wiring patterning is possible. Therefore, by applying this embodiment, it is possible to manufacture a semiconductor device including a wiring board and a semiconductor chip mounted thereon with a high yield. Furthermore, as described in the first embodiment, the obtained semiconductor device 100 has high reliability and can operate at high speed, so that it can be used as a high-reliability high-frequency device.

In this example, results of a reliability test performed on the wiring board 110 of this embodiment will be described. FIG. 21 shows a schematic cross-sectional view of a wiring substrate 150 as Example 1 in this example. The wiring board 150 differs from the wiring board 110 shown in FIG. 13 in that four layers of wirings 112 (first to fourth wirings 112) are laminated.

The wiring board 150 was produced by the method described in the second embodiment. Specifically, a sixth inorganic film 118-3, a fifth inorganic film 118-2, and a fourth inorganic film 118-1 are formed on the bonding layer 134 shown in FIG. A barrier layer containing titanium (thickness 0.05 μm) and a seed layer 136 containing copper (thickness 0.2 μm) are formed by sputtering. were formed sequentially. After that, according to the method described in the second embodiment, first to fourth wirings 112 each having a thickness of 3 μm were formed. The thicknesses of the first inorganic film 114-1, the second inorganic film 114-2, and the third inorganic film 114-3 were 0.4 μm, 0.5 μm, and 0.1 μm, respectively. The bumps 120 were formed by growing SnAgCu by electroless plating and then reflowing to connect with the connection pads 142 of the main substrate 140 . Although not shown, a wiring substrate having the first protective film 114 but not the second protective film 118 and a wiring substrate having the second protective film 118 but not the first protective film 114 are examples of the respective embodiments. 2 and 3.

The fabricated wiring board 150 was allowed to stand under conditions of a temperature of 130° C. and a humidity of 85% for 96 hours, and then cross-sectional observation was performed using a scanning electron microscope. The first wiring 112-1 to the third wiring 112-3 have various shapes and widths as shown in FIGS. Although the surfaces of the first wiring 112-1 and the third wiring 112-3 are slightly oxidized in the second and third embodiments, respectively, the oxidation hardly occurs regardless of the shape and width. was confirmed. In Example 1, no variation in the dielectric loss of the insulating film 102 was observed, and in Examples 2 and 3, only practically negligible variation was observed. Moreover, in any of Examples 1 to 3, no peeling was observed between the second wiring 112-2 and the third protective film 122 provided thereon.

On the other hand, when a wiring substrate (comparative example 1) having a structure similar to that of the wiring substrate 150 but not having the first protective film 114 and the second protective film 118 is used, regardless of the width and shape, the wiring 112 was confirmed to be oxidized. Moreover, the dielectric loss of the insulating film 102 fluctuated (increased), and a significant drop in transmission characteristics was confirmed. Furthermore, it was confirmed that peeling occurred between the second wiring 112-2 and the third protective film 122 regardless of the width and shape of the wiring 112. FIG.

Thus, it was confirmed that a highly reliable wiring board can be provided by applying the above-described embodiments.

Each of the embodiments described above as embodiments of the present disclosure can be implemented in combination as appropriate as long as they do not contradict each other. In addition, based on each embodiment, addition, deletion, or design change of constituent elements as appropriate by those skilled in the art is also included in the scope of the present disclosure as long as it includes the gist of the present disclosure.

In addition, even if there are other effects that are different from the effects brought about by each of the above-described embodiments, those that are obvious from the description of this specification or those that can be easily predicted by those skilled in the art are of course It is understood that provided by the present disclosure.

100: semiconductor device, 102: insulating film, 104: second insulating film, 106: third insulating film, 110: wiring substrate, 112: wiring, 112-1: first wiring, 112-2: second wiring, 112-3: third wiring, 112-4: fourth wiring, 112-5: fifth wiring, 112-n: nth wiring, 114: first protective film, 114-1 : first inorganic film, 114-2: second inorganic film, 114-3: third inorganic film, 116: connection pad, 118: second protective film, 118-1: fourth inorganic film, 118-2: fifth inorganic film, 118-3: sixth inorganic film, 120: bump, 122: third protective film, 122-1: seventh inorganic film, 122-2: eighth inorganic Film, 130: Support substrate, 132: Separation layer, 134: Bonding layer, 136: Seed layer, 137: Plating layer, 138: Resist mask, 140: Main substrate, 142: Connection pad, 144: Opening, 150: Wiring substrate , 200: semiconductor chip, 200-1: logic LSI, 200-2: memory, 202: bump, 204: resin

Claims (38)

first to n-th wirings electrically connected to each other;
an insulating film that embeds the first to n-th wirings;
a first protective film located on the insulating film, in contact with the insulating film, and containing at least one of silicon nitride and silicon oxide; and has a connection pad electrically connected to the wiring of
the first to n-th wirings are stacked such that the (k+1)th wiring selected from the first to n-th wirings is positioned on the k-th wiring;
The first protective film is
a first inorganic film comprising silicon nitride;
a second inorganic film containing silicon oxide over the first inorganic film, and a third inorganic film containing silicon nitride over the second inorganic film;
the thickness of the second inorganic film is greater than the thickness of the portion where the n-th wiring is exposed from the insulating film;
A wiring board, wherein n is a natural number greater than 1 and k is a natural number smaller than n. 2. The wiring board according to claim 1, wherein each of said first to n-th wirings contains copper. 2. The wiring substrate according to claim 1, wherein said insulating film has a dielectric loss tangent of 1×10 ⁻³ or more and 1×10 ⁻² or less. 2. The wiring board according to claim 1, wherein the thickness of said third inorganic film is larger than the thickness of said first inorganic film and smaller than the thickness of said second inorganic film. 2. The wiring board according to claim 1, wherein said first protective film is positioned on said first to n-th wirings. 2. The wiring substrate according to claim 1, wherein said nth wiring is positioned on said first protective film. 2. The wiring substrate according to claim 1, further comprising a second insulating film on said first protective film and said nth wiring. 2. The wiring board according to claim 1, further comprising a second protective film containing at least one of silicon nitride and silicon oxide under said insulating film. The second protective film is
a fourth inorganic film comprising silicon nitride;
9. The wiring substrate according to claim 8, further comprising a fifth inorganic film containing silicon oxide under said fourth inorganic film, and a sixth inorganic film containing silicon nitride under said fifth inorganic film. 10. The wiring board according to claim 9, wherein the thickness of said sixth inorganic film is greater than the thickness of said fourth inorganic film and smaller than the thickness of said fifth inorganic film. 9. The wiring substrate according to claim 8, wherein said second protective film is positioned under said first wiring. 9. The wiring substrate according to claim 8, wherein at least part of said second protective film is sandwiched between said first wiring and said second wiring. 9. The wiring board according to claim 8, further comprising a third insulating film under said insulating film and said second protective film. 2. The wiring substrate according to claim 1, wherein said first protective film covers side surfaces of said insulating film. 2. The wiring substrate according to claim 1, further comprising a third protective film located on at least one of said first to (n-1)th wirings and in contact with said at least one wiring. The third protective film is
16. The wiring board according to claim 15, comprising a seventh inorganic film containing silicon nitride, and an eighth inorganic film containing silicon oxide on said seventh inorganic film. 2. A semiconductor device comprising: the wiring board according to claim 1; and a semiconductor chip electrically connected to said n-th wiring. 18. The semiconductor device according to claim 17, further comprising a main substrate electrically connected to said first wiring. 18. The semiconductor device of Claim 17, wherein the semiconductor device is configured to operate as a radio frequency device. By sequentially repeating forming a wiring on a substrate, forming an insulating film on the wiring, and forming an opening exposing the wiring in the insulating film, the wiring is buried in the insulating film and electrically connected to each other. sequentially forming first to n-th wirings that are physically connected;
forming a first protective film on the insulating film;
forming a connection pad on the nth wiring electrically connected to the nth wiring; and separating the substrate from the first wiring;
The first protective film is
a first inorganic film comprising silicon nitride;
a second inorganic film containing silicon oxide over the first inorganic film, and a third inorganic film containing silicon nitride over the second inorganic film;
The method of manufacturing a semiconductor device, wherein the thickness of the second inorganic film is larger than the thickness of the portion where the n-th wiring is exposed from the insulating film . 21. The method of claim 20, wherein the first through nth interconnects are formed by electrolytic plating of copper. 21. The method according to claim 20, wherein said insulating film has a dielectric loss tangent of 1*10< ^-3 > to 1*10 ^<-2 >. Formation of the first protective film includes:
forming the first inorganic film by a plasma CVD method;
forming the second inorganic film on the first inorganic film by a plasma CVD method;
22. The method according to claim 21, comprising forming said third inorganic film on said second inorganic film by a plasma CVD method. 24. The method according to claim 23, wherein the first protective film is formed so that the thickness of the third inorganic film is larger than the thickness of the first inorganic film and smaller than the thickness of the second inorganic film. described method. 21. The method of claim 20, wherein said first passivation film is formed over said nth wire. 21. The method according to claim 20, wherein said first protective film is formed so as to be located between said (n-1)th wiring and said nth wiring. 21. The method of claim 20, further comprising forming a second insulating film over said first protective film and said nth wire. further comprising forming a second protective film on the substrate before forming the insulating film;
21. The method of Claim 20, wherein the second protective film comprises at least one of silicon nitride and silicon oxide. Formation of the second protective film includes:
forming a fourth inorganic film containing silicon nitride by a plasma CVD method;
forming a fifth inorganic film containing silicon oxide on the fourth inorganic film by a plasma CVD method;
29. The method of claim 28, comprising forming a sixth inorganic film containing silicon nitride on the fifth inorganic film by plasma CVD. 30. The second protective film according to claim 29, wherein the thickness of the sixth inorganic film is larger than the thickness of the fourth inorganic film and smaller than the thickness of the fifth inorganic film. described method. 29. The method of claim 28, wherein the second protective film is formed after forming the first wiring and before forming the second wiring. 29. The method of claim 28, wherein said second protective film is formed prior to forming said first interconnect. 29. The method of claim 28, further comprising forming a third insulating film under the second protective film after separating the substrate. 21. The method according to claim 20, wherein said first protective film is formed to cover side surfaces of said insulating film. further comprising forming a third protective film on at least one of the first to (n-1)th wirings in contact with the at least one wiring;
21. The method of Claim 20, wherein the third protective film comprises at least one of silicon nitride and silicon oxide. Formation of the third protective film includes:
forming a seventh inorganic film containing silicon nitride by a plasma CVD method;
36. The method of claim 35, comprising forming an eighth inorganic film containing silicon oxide on the seventh inorganic film by plasma CVD. 21. The method of claim 20, further comprising connecting a semiconductor chip to said nth wire before separating said substrate. 21. The method of claim 20, further comprising connecting a main board to said first wiring.

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