JP2019186352A - Wiring board, semiconductor device having wiring board, and manufacturing method of semiconductor device - Google Patents

Abstract

To provide a wiring board applicable to FOWLP, and to provide a semiconductor device including the same, and a manufacturing method thereof.SOLUTION: A wiring board 110 has first through n-th wiring 112-1 through 112n interconnected electrically, an insulator film 102 for embedding the first through n-th wiring, a first protection film 114 located on the first through n-th wiring and the insulator film, in contact with therewith, and containing at least any one of silicon nitride and silicon oxide, and a connection pad 116 located on the first protection film, and electrically connected with the n-th wiring. The first through n-th wiring are laminated so that the (k+1)th wiring, selected from the first through n-th wiring, is located on the k-th wiring, where n is a natural number larger than 1, and k is a natural number smaller than 1.SELECTED DRAWING: Figure 13

Description

  The present disclosure relates to a wiring board that can be used as an interposer, a semiconductor device having the wiring board, and a method for manufacturing the same.

  A semiconductor chip manufactured using a semiconductor substrate such as silicon is mounted on almost all electronic devices and provides various functions to the electronic devices. The semiconductor chip is provided with terminals for inputting power and signals necessary for operation, and is mounted on a main board such as a printed wiring board. As one of semiconductor chip mounting methods, a method called fan-out type wafer level packaging (FOWLP) is known. In this mounting method, a wiring substrate (hereinafter also referred to as an interposer) provided with a wiring layer formed over a larger area than the semiconductor chip is used, and the semiconductor chip is mounted on the main substrate via the interposer. For example, Patent Document 1 discloses a semiconductor device to which FOWLP is applied and a manufacturing method thereof.

JP 2017-085028 A

Chien-Fu Tseng, Chung-Shi Liu, Chi-Hsi Wu, Douglas Yu, InFO (wafer level integrated fan-out) Technology (InFO (Wafer Level Integrated Fan-Out) Technology), 2016 IEEE 66th Electronic Components and Technology Conference (2016 IEEE 66th Electronic Components and Technology 6th, United States 6

  One of the problems of the present disclosure is to provide a wiring board applicable to FOWLP, a semiconductor device including the wiring board, and a manufacturing method thereof. For example, one of the problems of the present disclosure is to provide a wiring board that can be applied to a semiconductor device that requires a high operating frequency, such as that used in high-speed communication, a semiconductor device having the wiring board, and a method for manufacturing the same. It is to be.

  One embodiment of the present disclosure is a wiring board. The wiring board is located on the insulating film, in contact with the insulating film, and is at least silicon nitride and oxidized. A first protective film containing any one of silicon and a connection pad located on the first protective film and electrically connected to the nth wiring are provided. The first to nth wirings are stacked such that the (k + 1) th wiring selected from the first to nth wirings is positioned on the kth wiring. n is a natural number larger than 1, and k is a natural number smaller than n.

  One embodiment of the present disclosure is a method of manufacturing a semiconductor device. In this method, a wiring is formed on a substrate, an insulating film is formed on the wiring, and an opening that exposes the wiring is formed in order, thereby being embedded in the insulating film and electrically connected to each other. Sequentially forming first to nth wirings to be connected to each other, forming a first protective film on the insulating film, and via an opening exposing the nth wiring on the nth wiring Forming a connection pad electrically connected to the nth wiring and separating the substrate from the first wiring. The first protective film includes at least one of silicon nitride and silicon oxide.

1A and 1B are a schematic top view and bottom view of a wiring board and a semiconductor device according to one embodiment. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device according to one embodiment. The typical top view of the wiring of the wiring board concerning one of the embodiments. The typical top view of the wiring of the wiring board concerning one of the embodiments. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device according to one embodiment. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device according to one embodiment. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device according to one embodiment. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device according to one embodiment. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device according to one embodiment. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device according to one embodiment. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device according to one embodiment. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device according to one embodiment. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device according to one embodiment. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device according to one embodiment. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a wiring board and a semiconductor device according to one embodiment. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a wiring board and a semiconductor device according to one embodiment. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a wiring board and a semiconductor device according to one embodiment. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a wiring board and a semiconductor device according to one embodiment. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a wiring board and a semiconductor device according to one embodiment. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a wiring board and a semiconductor device according to one embodiment. 1 is a schematic cross-sectional view of a wiring board and a semiconductor device used in examples.

  Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings. However, the present disclosure can be implemented in various modes without departing from the gist thereof, and is not construed as being limited to the description of the embodiments exemplified below.

  In order to clarify the description, the drawings may be schematically represented with respect to the width, thickness, shape, and the like of each part as compared to actual aspects, but are merely examples and limit the interpretation of the present disclosure. Not what you want. In the present specification and each drawing, elements having the same functions as those described with reference to the previous drawings may be denoted by the same reference numerals, and redundant description may be omitted.

  In the present specification and claims, in expressing a mode of disposing another structure on a certain structure, when simply describing “on top”, unless otherwise specified, It includes both the case where another structure is disposed immediately above and a case where another structure is disposed via another structure above a certain structure.

  In the present specification and claims, the expression “a structure is exposed from another structure” means an aspect in which a part of a structure is not covered by another structure. The part which is not covered with the structure includes an aspect covered with another structure.

  In this specification and the drawings, when a plurality of components are distinguished from each other, they are expressed using a hyphen and a natural number after the reference numeral. When noting each of a plurality of constituent elements as a whole, or expressing a constituent element arbitrarily selected from them, only the reference numerals are used.

(First embodiment)
1. Basic Structure A schematic top view and bottom view of a wiring board 110 and a semiconductor device 100 having the wiring board 110 according to one embodiment of the present disclosure are shown schematically in FIGS. 1A and 1B, respectively. A cross-sectional view is shown in FIG. As shown in FIG. 2A, the semiconductor device 100 includes a wiring board 110 and a semiconductor chip 200 that is electrically connected to the wiring board 110. As an arbitrary configuration, the semiconductor device 100 may include a main substrate 140. The main board 140 has connection pads 142, and the wiring board 110 and the main board 140 are electrically connected via the connection pads 142.

  The wiring substrate 110 includes a plurality of wirings (first wiring 112-1 to n-th wiring 112-n, where n is a natural number greater than 1) 112 that are stacked on each other and electrically connected to each other. Each of the wirings 112 is entirely or partially embedded in an insulating film (also referred to as a base film) 102. The number of layers of the wiring 112 (that is, n) is not limited, and can be arbitrarily determined in consideration of the number of terminals of the semiconductor chip 200 and the number of connection pads 142 of the main substrate 140. 2A shows an example in which n is 5, and the wiring board 110 includes a plurality of wirings 112 as first to fifth wirings (112-1, 112-2, 112-3, 112-4, 112-5). The first wiring 112-1 is positioned at the bottom, and the nth wiring 112-5 is positioned at the top. That is, the wiring 112 is stacked so that the (k + 1) th wiring selected from the first to nth wiring is positioned on the kth wiring (k is a natural number smaller than n). As shown in FIG. 2A, the wiring 112 is arranged so that the arrangement area becomes smaller as n becomes larger. That is, the area of the region where the kth wiring is arranged is larger than the area of the region where the (k + 1) th wiring is arranged. With this structure, the terminal of the wiring board 110 for connection to the main board 140, that is, the first wiring 112-1 can be arranged at a position that does not overlap the semiconductor chip 200. As shown in FIG. 2A, it is preferable that at least a part of the (k + 1) -th wiring is configured to become thinner as it approaches the k-th wiring.

  The wiring substrate 110 is further provided with a first protective film 114 in contact with the n-th wiring 112-n and the (first insulating film) insulating film 102. The first protective film 114 is composed of one or a plurality of films, and includes at least one of silicon nitride and silicon oxide. The first protective film 114 has a function of preventing impurities such as water and oxygen from entering the insulating film 102 from the outside.

  A part of the side surface and the upper surface of the n-th wiring 112-n are exposed from the insulating film 102. The thickness of the n-th wiring 112-n above the insulating film 102 can be 0.5 μm to 10 μm, 1 μm to 5 μm, or 1 μm to 3 μm. A part of the upper surface and the side surface of the n-th wiring 112-n are covered with the first protective film 114, and another part of the upper surface is exposed from the first protective film 114, so that the n-th wiring 112-n. It is electrically connected to the connection pad 116 provided on the top. Similar to the wiring 112, the connection pad 116 is preferably configured so that at least a part thereof becomes thinner toward the nth wiring 112-n.

  The semiconductor chip 200 is electrically connected to the connection pads 116 via bumps 202 having an arbitrary configuration. When the bump 202 is not used, for example, the terminal of the semiconductor chip 200 and the connection pad 116 may be connected by solid phase bonding. The semiconductor chip 200 can have an arbitrary configuration and function. For example, logic such as a central processing unit (CPU), an application specific integrated circuit (ASIC), a graphic processing unit (GPU), and a field-programmable gate array (FPGA). It is selected from memories such as LSI, DRAM, and flash memory. In the example shown in FIGS. 1A and 2A, an example in which the logic LSI 200-1 and the memory 200-2 are arranged on the wiring board 110 is shown. These semiconductor chips 200 are sealed with a resin (mold resin) 204 such as an epoxy resin, an acrylic resin, a novolac resin, a phenol resin, or a benzocyclobutene resin.

  On the other hand, the bottom surface of the first wiring 112-1 is exposed from the insulating film 102, and the bottom surface is electrically connected to the bump 120. The wiring board 110 can be connected to the connection pads 142 of the main board 140 via the bumps 120, whereby the semiconductor chip 200 can be mounted on the main board 140. As the main board 140, a known printed wiring board (printed board) can be used.

  As understood from FIGS. 1B and 2A, the area where the first wiring 112-1 is arranged is larger than the area occupied by the semiconductor chip 200. For this reason, the terminals can be extended to the outside of the semiconductor chip 200, and not only can the connection with the large number of connection pads 142 provided on the main substrate 140 be made, but the main substrate 140 can be formed even if the semiconductor chip 200 is miniaturized. It is possible to easily make electrical connection.

  Hereinafter, individual configurations will be described.

2. Insulating Film The insulating film 102 contains an organic compound. The organic compound used preferably has a low dielectric constant and dielectric loss tangent. For example, the dielectric constant is 2.0 or more and 4.0 or less, and the dielectric loss tangent is 1 × 10 ⁻⁴ or more and 1 × 10 ⁻² or less, or 1 ×. An organic compound of 10 ⁻³ or more and 1 × 10 ⁻² or less can be used as the insulating film 102. Such an organic compound is typically a polymer having polyimide as a basic skeleton (hereinafter simply referred to as polyimide), and the polyimide may be chain-like or cross-linked between molecules. The insulating film 102 may have flexibility.

3. Wiring FIG. 2B is a schematic cross-sectional view of part of the wiring 112. As will be described later, the wiring 112 can be formed using an electrolytic plating method. In this case, as illustrated in FIG. 2B, each wiring 112 includes a seed layer 136 and a plating layer 137 over the seed layer 136. The seed layer 136 includes a metal such as titanium, nickel, chromium, copper, gold, or an alloy thereof, and typically includes copper. The plating layer 137 can include a metal such as titanium, aluminum, copper, nickel, tungsten, molybdenum, gold, silver, iron, chromium, or an alloy thereof, and typically includes copper. Although not shown, a barrier layer may be further provided under each seed layer 136. The material included in the barrier layer is selected from metals such as titanium, tantalum, molybdenum, tungsten, alloys thereof, or nitrides thereof, and has a higher melting point than the metal included in the seed layer 136 and the plating layer 137. A material is preferred. By providing the barrier layer, the metal contained in the wiring 112 can be prevented from diffusing into the insulating film 102.

  The planar shape of the wiring 112 is not limited and is determined based on the required function. For example, the wiring 112 can be provided so as to extend mainly in one direction as illustrated in FIG. In this case, the width W of the wiring 112 can be selected in the range of 10 μm to 1000 μm. Alternatively, as illustrated in FIG. 3B, the wiring 112 may have a mesh shape. In this case, the width W (that is, the distance between adjacent openings provided in the mesh shape) can be selected in the range of 5 μm to 500 μm. Alternatively, as shown in FIG. 4, the wiring 112 may be a rectangle having a width W selected from a range larger than 1000 μm and 7 cm or less. In this case, the wiring 112 may have the same or almost the same shape as the planar shape of the wiring board 110.

4). Protective Film As described above, the first protective film 114 includes one of silicon nitride and silicon oxide. The first protective film 114 is preferably formed by a chemical vapor deposition method (plasma CVD method) in the presence of plasma. Accordingly, the dense first protective film 114 can be formed over the insulating film 102, and high blocking properties can be imparted to impurities.

5. Modified Example As shown in FIG. 5, the wiring substrate 110 may be provided with not only the first protective film 114 but also the second protective film 118 under the insulating film 102. The second protective film 118 also includes any one of silicon nitride and silicon oxide, and is preferably formed by a plasma CVD method. In this case, part of the bottom surface of the first wiring 112-1 and the lower surface of the insulating film 102 are in contact with the second protective film 118, and the other part of the bottom surface of the first wiring 112-1 is the second protection. It is exposed from the film 118 and is electrically connected to the bump 120.

  There is no restriction on the vertical relationship between the n-th wiring 112-n and the first protective film 114. For example, as illustrated in FIG. 6A which is a cross-sectional view of the (n-1) th wiring 112- (n-1) and the nth wiring 112-n, the nth wiring 112-n is connected to the first wiring 112-n. A protective film 114 may be provided so as to be in contact with the first protective film 114. In this case, the first protective film 114 is located between the (n−1) th wiring 112- (n−1) and the nth wiring 112-n. The first protective film 114 may be provided on the insulating film 102 and may cover the side wall of the opening exposing the upper surface of the (n-1) th wiring 112- (n-1) (FIG. 6A). Alternatively, as illustrated in FIG. 6B, the sidewall may be in contact with the n-th wiring 112-n. Alternatively, as illustrated in FIG. 6C, the first protective film 114 and the nth wiring 112-n are arranged such that the side surface of the first protective film 114 is in contact with the nth wiring 112-n over the insulating film 102. May be configured.

  The coefficient of thermal expansion of a metal such as copper used for the wiring 112 is larger than that of the material included in the first protective film 114. For example, the thermal expansion coefficient of copper is 16 ppm or more, and the thermal expansion coefficient of silicon nitride or silicon oxide is 3 ppm or less. Therefore, when the first protective film 114 is provided over the structure shown in FIG. 5, that is, the n-th wiring 112-n, the first protective film 114 is in contact with the n-th wiring 112-n, and In addition, cracks are likely to occur in the bent portion (for example, the region 114a in FIG. 5). However, by adopting the structure shown in FIG. 6A to FIG. 6C, damage to the first protective film 114 due to thermal expansion of the n-th protective film is reduced, so that generation of cracks is suppressed. can do.

  Alternatively, as shown in FIG. 7A, a second insulating film 104 may be provided over the first protective film 114. The second insulating film 104 can include a material that can be used for the insulating film 102. The impurity concentration in the second insulating film 104 may be higher than that of the insulating film 102. For this reason, the dielectric constant and dielectric loss tangent of the second insulating film 104 may be higher than those of the insulating film 102. . The second insulating film 104 is provided with an opening exposing the n-th wiring 112-n, and the wiring substrate 110 and the connection pad 116, the bump 202, or the semiconductor chip 200 are electrically connected in this opening. Further, as shown in FIG. 7B, the side surface of the first protective film 114 may form the side wall of the opening. That is, the side wall of the opening of the second insulating film 104 and the side surface of the first protective film 114 can be located on the same plane. By using such a structure, the bump 202 can be stably held in the opening. Therefore, stable electrical connection with the semiconductor chip 200 is possible without using the connection pad 116, and the semiconductor device 100 Reliability can be improved.

  Note that as shown in FIG. 7C, the bump 202 can be stably held by providing the first protective film 114 without providing the second insulating film 104 and by providing an inclined side surface. .

  A similar structure can be applied to the second protective film 118. For example, as illustrated in FIG. 8A, the second protective film 118 may be provided over the first wiring 112-1 so as to be in contact with the first wiring 112-1. In this case, the second protective film 118 is located between the first wiring 112-1 and the second wiring 112-2. The second protective film 118 is provided with an opening exposing the upper surface of the first wiring 112-1, and the first wiring 112-1 and the second wiring 112-2 are electrically connected in this opening. . Further, as illustrated in FIG. 8B, a third insulating film 106 may be provided below the first wiring 112-1 and the insulating film 102. The third insulating film 106 is also provided with an opening exposing the lower surface of the first wiring 112-1. Similar to the second insulating film 104, the third insulating film 106 can also contain a material that can be used for the insulating film 102, and the dielectric constant and dielectric loss tangent thereof may be higher than those of the insulating film 102.

  In such a structure, the area of the interface between the first wiring 112-1 and the second protective film 118 can be increased as compared with the structure shown in FIG. The intrusion route can be lengthened. For this reason, it is possible to prevent the dielectric constant and dielectric loss tangent of the insulating film 102 from increasing due to water entering from outside.

  Alternatively, as illustrated in FIG. 9A, the third insulating film 106 may be provided below the first wiring 112-1 and the insulating film 102. The second protective film 118 may be exposed in the opening provided in the third insulating film 106 or, as shown in FIG. 9B, the side wall of the opening of the third insulating film 106 and the second protective film. You may comprise the 3rd insulating film 106 and the 2nd protective film 118 so that the side surface of the film | membrane 118 may be located on the same plane. Similar to the structure shown in FIGS. 7A to 7C, by applying such a structure, the bump 120 can be stably held, and a stable electrical connection with the main board 140 can be achieved. It becomes possible. As a result, the reliability of the semiconductor device 100 can be improved.

  The first protective film 114 and the second protective film 118 may have a multilayer structure. For example, as shown in FIG. 10A, the first protective film 114 is positioned on the first inorganic film 114-1 and the first inorganic film 114-1, and the first inorganic film 114-1 A three-layer structure including a second inorganic film 114-2 in contact with the second inorganic film 114-2 and a third inorganic film 114-3 in contact with the second inorganic film 114-2. be able to.

  The dielectric constant of the second inorganic film 114-2 is preferably smaller than that of the first inorganic film 114-1 or the third inorganic film 114-3. More specifically, the first inorganic film 114-1 and the third inorganic film 114-3 contain silicon nitride or silicon carbide (silicon carbide). That is, the first inorganic film 114-1 and the third inorganic film 114-3 contain silicon and nitrogen or silicon and carbon as main constituent elements. On the other hand, the second inorganic film 114-2 contains silicon oxide or silicon oxynitride. That is, the second inorganic film 114-2 may contain silicon and oxygen as constituent elements, and may further contain nitrogen. When nitrogen is included, the composition is smaller than that of oxygen. The first inorganic film 114-1, the second inorganic film 114-2, and the third inorganic film 114-3 are formed by a plasma CVD method.

The thickness of the first inorganic film 114-1 may be smaller than the thickness of the second inorganic film 114-2 or the third inorganic film 114-3, for example, 0.05 μm or more and 0.3 μm or less, Specifically, it can be 0.2 μm. The thickness of the second inorganic film 114-2 may be larger than the thickness of the first inorganic film 114-1 or the third inorganic film 114-3, and is 0.5 μm or more and 10 μm or less, or 1 μm or more and 5 μm. It can be as follows. The thickness of the third inorganic film 114-3 can be 0.2 μm or more and 1 μm or less, or 0.3 μm or more and 0.7 μm or less, typically 0.5 μm. That is, when the thicknesses of the first inorganic film 114-1, the second inorganic film 114-2, and the third inorganic film 114-3 are T ₁ , T ₂ , and T ₃ , respectively, the following relationship is established. Thus, the first protective film 114 can be configured.
T ₁ <T ₃ <T ₂

  FIG. 10B is a schematic cross-sectional view of the n-th wiring 112-n and the first protective film 114 having a three-layer structure. The thickness of the second inorganic film 114-2 may be smaller than the thickness of the portion where the n-th wiring 112-n is exposed from the insulating film 102, or as shown in FIG. It may be larger than the thickness. In this case, the bottom surface of the third inorganic film 114-3 is the top surface of the n-th wiring 112-n between the adjacent n-th wirings 112-n even when the plurality of n-th wirings 112-n are close to each other. Located above. That is, in the cross section, the third inorganic film 114-3 is not sandwiched between the adjacent nth wirings 112-n. For this reason, it is possible to prevent a capacitance (parasitic capacitance) from being formed by the third inorganic film 114-3 having a relatively high dielectric constant and the nth wiring 112-n adjacent thereto. Further, by making the thickness of the first inorganic film 114-1 smaller than the thickness of the second inorganic film 114-2, the thickness is increased by the nth wiring 112-n adjacent to the first inorganic film 114-1. The formation of a capacitor can be prevented at the same time. As a result, the generation of parasitic capacitance and the accompanying decrease in signal transmission speed can be prevented.

  Such a three-layer structure can also be applied to the second protective film 118. Specifically, as illustrated in FIG. 11, the second protective film 118 is located below the insulating film 102 and is in contact with the insulating film 102, a fourth inorganic film 118-1 and a fourth inorganic film 118-1. 5th inorganic film 118-2 in contact with the fourth inorganic film 118-1 and 5th inorganic film 118-2, and in contact with the fifth inorganic film 118-2 It can have a three-layer structure including the sixth inorganic film 118-3. The fourth inorganic film 118-1, the fifth inorganic film 118-2, and the sixth inorganic film 118-3 are the first inorganic film 114-1, the second inorganic film 114-2, and the third inorganic film, respectively. Corresponding to the film 114-3, the relationship between the composition and thickness, and the formation method are the same as those of the first inorganic film 114-1, the second inorganic film 114-2, and the third inorganic film 114-3. It is.

  As shown in FIG. 12, the first protective film 114 may be formed so as to cover the side surface of the insulating film 102. In this case, the second protective film 118 can be provided in contact with the first protective film 114. By adopting such a structure, impurities can be prevented from entering the insulating film 102 more effectively.

  As shown in FIG. 13, the wiring board 110 is further located on at least one wiring 112 selected from the first to (n−1) th wirings 112 and is in contact with the selected wiring 112. A protective film 122 may be provided. The third protective film 122 exists in the insulating film 102. The third protective film 122 may also have any structure of a single layer structure and a laminated structure. In the case of the stacked structure, the third protective film 122 includes, for example, silicon nitride, and is positioned on the seventh inorganic film 122-1 and the seventh inorganic film 122-1, which are in contact with the selected wiring 112. And an eighth inorganic film 122-2 containing silicon oxide can be provided. These inorganic films 122 also correspond to the first inorganic film 114-1 and the second inorganic film 114-2, respectively. The same as those of the second inorganic film 114-2. Although not shown, the third protective film 122 further includes a ninth inorganic film that is located on the eighth inorganic film 122-2, is in contact with the eighth inorganic film 122-2, and contains silicon nitride. May be.

  When the first protective film 114 covers the side surface of the insulating film 102, the first inorganic film 114-1 is in contact with the side surfaces of the seventh inorganic film 122-1 and the eighth inorganic film 122-2. A protective film 114 may be provided (see FIG. 14).

  By forming the third protective film 122 having such a structure, even if the number of stacked layers of the wirings 112 is increased and the thickness of the insulating film 102 is increased, it is effective that impurities enter the insulating film 102. Can be suppressed.

  As can be understood from FIGS. 2A, 5, 10 A, and FIGS. 11 to 14, the bump 120 connected to the first wiring 112-1 is connected to the main substrate 140, and There is no other substrate such as a package substrate between the one wiring 112-1 or the insulating film 102 and the main substrate 140. For this reason, the wiring board 110 of this embodiment can be used as a thin interposer or a flexible interposer, which contributes to the thinning of the semiconductor device 100.

  Further, the wiring board 110 can be used as an interposer for a semiconductor device that requires a high operating frequency such as a high-frequency element. When a wiring board is used for a high-frequency element, a low dielectric constant and a dielectric loss tangent are required for an insulating film surrounding the wiring of the wiring board in order to prevent signal transmission loss and delay. Even when an insulating film (for example, the insulating film 102 in the wiring substrate 110) is formed using a material that satisfies such performance, impurities such as water, oxygen, and metal ions are externally formed after the wiring substrate is formed. The dielectric constant and dielectric loss tangent of the insulating film gradually increase. As a result, signal transmission loss and delay occur, which greatly affects the characteristics of the semiconductor chip mounted on the interposer.

  However, as described above, in the wiring substrate 110 of the present embodiment, the first protective film 114 and the second protective film 118 that are in contact with the insulating film 102 or at least one of the plurality of wirings 112 is covered in the insulating film 102. A third protective film 122 and the like are provided. Thereby, an increase in the dielectric constant and dielectric loss tangent of the insulating film 102 due to the intrusion of impurities can be effectively suppressed, and signal transmission loss and delay of the semiconductor chip mounted on the wiring board 110 can be prevented. Is possible.

  Further, when these protective films further have the above-described three-layer structure, the intrusion of impurities can be more effectively suppressed, and the reliability of the semiconductor device 100 can be greatly improved as described below. Since silicon oxide contained in the second inorganic film 114-2 has relatively high hydrophilicity, when an impurity such as water enters from the outside, the impurity diffuses into the first inorganic film 114-1. Although the first inorganic film 114-1 contains silicon nitride having low hydrophilicity and high blocking property against impurities, when the thickness is formed small, some impurities may permeate. When impurities that enter the insulating film 102 enter, the surface of the wiring 112 is oxidized by water, oxygen or metal ions contained therein, and as a result, the adhesion between the third protective film 122 and the wiring 112 covered by the third protective film 122. Decreases. Since the coefficient of thermal expansion of the seventh inorganic film 122-1 included in the wiring 112 and the third protective film 122 is greatly different, peeling occurs due to the film stress generated between them.

  However, the first protective film 114 includes a third inorganic film containing silicon nitride on the second inorganic film 114-2 so as to have a thickness larger than that of the first inorganic film 114-1. 114-3 can be provided. Therefore, the rate at which impurities enter the first inorganic film 114-1 and the insulating film 102 through the second inorganic film 114-2 can be significantly reduced, and the wiring 112 and the seventh inorganic film 122-1. Separation can be effectively prevented. For this reason, it becomes possible to prevent the occurrence of defects due to peeling, and as a result, the reliability of the semiconductor device 100 can be improved.

(Second Embodiment)
In the present embodiment, a method for manufacturing the wiring substrate 110 shown in FIG. 11 and the semiconductor device 100 including the wiring substrate 110 will be described. A description of a configuration similar to or similar to that of the first embodiment may be omitted.

  First, the peeling layer 132 is formed over the supporting substrate 130, and the bonding layer 134 is further formed thereover (FIG. 15A). As the support substrate 130, a substrate containing glass, quartz, or the like may be used. For the peeling layer 132, a film containing a metal such as tungsten or molybdenum can be formed by a CVD method or a sputtering method, for example. Alternatively, the release layer 132 may be formed using a photosensitive organic release material having an acrylic resin or silicone resin as a basic structure, or an organic release material capable of mechanical peeling. The bonding layer 134 can be formed by using, for example, a polysiloxane-based polymer compound and applying a spin coating method, a dip coating method, or the like.

  Next, a second protective film 118 is formed (FIG. 15B). Specifically, on the bonding layer 134, a sixth inorganic film 118-3 containing silicon nitride, a fifth inorganic film 118-2 containing silicon oxide, and a fourth inorganic film 118-1 containing silicon nitride. Are sequentially formed using a plasma CVD method. As described above, the fourth inorganic film 118-1, the fifth inorganic film 118-2, and the sixth inorganic film 118-3 are the first inorganic film 114-1 and the second inorganic film 114-, respectively. 2 and corresponds to the third inorganic film 114-3. Therefore, the thickness of the sixth inorganic film 118-3 can be set to 0.2 μm to 1 μm, or 0.3 μm to 0.7 μm, typically 0.5 μm. The thickness of the fifth inorganic film 118-2 can be set to 0.5 μm to 10 μm, or 1 μm to 5 μm. The thickness of the sixth inorganic film 118-3 can be set to 0.05 μm or more and 0.2 μm or less, typically 0.1 μm.

  Next, a seed layer 136 is formed on the second protective film 118 by applying a sputtering method, a CVD method, electroless plating, an evaporation method, or the like. In particular, the seed layer 136 is efficiently formed by applying the sputtering method. Although not shown, a barrier layer may be formed before the seed layer 136 is provided. After that, a resist mask 138 is formed in a region where the first wiring 112-1 is not formed (FIG. 15C). The resist mask 138 may be formed by applying and curing a liquid resist. Alternatively, the resist mask 138 may be formed by attaching a film-like resist on the seed layer 136 and then performing exposure and development. Thereafter, power is supplied to the seed layer 136 to perform electrolytic plating, and a metal film is formed on the seed layer 136 that is not covered with the resist mask 138, whereby the first wiring 112-1 is formed. Thereafter, the resist mask 138 is removed by ashing or the like, and the seed layer 136 and the barrier layer not covered with the first wiring 112-1 are removed by etching. As the etchant, an etchant containing an acid such as sulfuric acid can be used. Thus, the first wiring 112-1 is formed (FIG. 16A).

  Subsequently, part of the insulating film 102 is formed so as to cover the first wiring 112-1. Specifically, the photosensitive polymer having polyimide as the basic skeleton described in the first embodiment, or a solution or suspension of a precursor thereof is applied on the support substrate 130, and then exposure and development using a photomask are performed. By baking, part of the insulating film 102 having the opening 144 exposing the first wiring 112-1 is formed. Alternatively, part of the insulating film 102 may be formed by attaching the polymer film and performing exposure, development, and baking using a photomask. The thickness of the insulating film 102 formed at this stage is appropriately adjusted in the range of 0.5 μm to 5 μm. As shown in FIG. 16B, the opening 144 is preferably formed to have a forward tapered structure. That is, it is preferable that the (k + 1) th wiring is formed so that at least a part thereof becomes thinner as it approaches the kth wiring.

  Subsequently, similarly to the formation of the first wiring 112-1, a barrier layer and a seed layer 136 are formed on the opening and upper surface of the insulating film 102, a resist mask is formed, and then electrolytic plating, removal of the resist mask, and the barrier layer are performed. In addition, the second wiring 112-2 is formed by partially removing the seed layer 136 (FIG. 16C). By repeating this process, the second wiring 112-2 to the n-th wiring 112-n are formed (FIG. 17A). For the sake of clarity, the seed layer 136 of the second wiring 112-2 is not shown in FIG. 16C, and all the seed layers 136 are not shown in FIGS. 17A to 20.

Next, a first protective film 114 is formed (FIG. 17B). The first protective film 114 is formed by sequentially forming a first inorganic film 114-1, a second inorganic film 114-2, and a third inorganic film 114-3 using a plasma CVD method. After that, an opening overlapping with the n-th wiring 112-n is provided in the first protective film 114 by using plasma etching, so that the n-th wiring 112-n is exposed (FIG. 18A). The plasma etching may be performed using, for example, a fluorine-containing alkane or alkene such as CF ₄ or CHF ₄ . This opening also preferably has a forward tapered structure.

  After that, the connection pad 116 is formed so as to cover the opening by using the same method as the formation of the first to n-th wirings 112 (FIG. 18B). When the opening is formed so as to have a forward taper structure, a part of the connection pad becomes thinner as it approaches the n-th wiring 112-n.

  Thereafter, the semiconductor chip 200 is electrically connected to the connection pads 116 using the bumps 202 including a conductive material such as solder. For example, solder balls formed using a capillary flow method or a thermal compression bonding method are formed as the bumps 202, whereby the semiconductor chip 200 and the wiring substrate 110 are electrically connected. Thereafter, the semiconductor chip 200 is sealed using the resin 204 described above (FIG. 19).

  Subsequently, light is irradiated from the support substrate 130 side using a light source such as a flash lamp or a laser to reduce the adhesive force at the interface between the release layer 132 and the support substrate 130 or at the interface between the release layer 132 and the bonding layer 134 ( (See FIG. 19). Thereafter, the support substrate 130 is peeled off using physical force. Further, the bonding layer 134 is dissolved using a chemical solution such as an alkaline aqueous solution to expose the second protective film 118. After that, etching is performed on the second protective film 118 to form an opening for exposing the first wiring 112-1 (FIG. 20). Although not shown, this opening may also be formed to have a forward tapered structure. That is, the opening may be formed so that the opening area becomes smaller as the first wiring 112-1 is approached. Similar to the connection between the semiconductor chip 200 and the connection pads 116, solder balls formed using a capillary flow method, a thermal compression bonding method, or the like are used as the bumps 120, and the connection pads 142 formed on the main substrate 140 and the first pads are formed. Electrical connection with the wiring 112-1 is performed (FIG. 11). Through the above steps, the wiring substrate 150 and the semiconductor device 100 including the wiring substrate 150 can be manufactured.

  Usually, in the FOWLP method, a semiconductor chip is first placed on a support substrate and sealed with resin. Thereafter, the support substrate is peeled off to form a pseudo wafer. Subsequently, the wiring substrate is formed on the pseudo wafer by laminating the wiring on the terminal of the semiconductor chip exposed by peeling. However, although precise wiring patterning is required to form a wiring board, when a pseudo wafer is used, the patterning accuracy greatly depends on the characteristics of the resin, and therefore wiring patterning is not always easy.

  On the other hand, in the manufacturing method described in this embodiment, since the wiring patterning can be performed using the support substrate 130 having high flatness and rigidity, precise wiring patterning is possible. Therefore, by applying this embodiment, it becomes possible to manufacture a semiconductor device including a wiring board and a semiconductor chip mounted thereon with a high yield. Further, as described in the first embodiment, since the obtained semiconductor device 100 has high reliability and can operate at high speed, it can be used as a highly reliable high-frequency device.

  In this example, the results of a reliability test performed on the wiring board 110 of this embodiment will be described. In FIG. 21, the cross-sectional schematic diagram of the wiring board 150 as Example 1 in a present Example is shown. The wiring board 150 is different from the wiring board 110 shown in FIG. 13 in that the wiring 112 is laminated in four layers (first to fourth wirings 112).

  The wiring board 150 was produced by the method described in the second embodiment. Specifically, the sixth inorganic film 118-3, the fifth inorganic film 118-2, and the fourth inorganic film 118-1 are each formed on the bonding layer 134 illustrated in FIG. After forming a thickness of 0.4 μm, 0.5 μm and 0.1 μm, a barrier layer containing titanium (thickness 0.05 μm) and a seed layer 136 containing copper (thickness 0.2 μm) are formed by sputtering. Were formed sequentially. Thereafter, according to the method described in the second embodiment, first to fourth wirings 112 each having a thickness of 3 μm were formed. The thicknesses of the first inorganic film 114-1, the second inorganic film 114-2, and the third inorganic film 114-3 were 0.4 μm, 0.5 μm, and 0.1 μm, respectively. The bump 120 was grown by electroless plating of SnAgCu and then reflowed to connect to the connection pad 142 of the main substrate 140. Although not shown, a wiring board having the first protective film 114 but not having the second protective film 118 and a wiring board having the second protective film 118 but not having the first protective film 114 are examples. 2 and 3 were produced.

  The produced wiring board 150 was allowed to stand for 96 hours under conditions of a temperature of 130 ° C. and a humidity of 85%, and then a cross-sectional observation was performed using a scanning electron microscope. The first wiring 112-1 to the third wiring 112-3 have various shapes and widths as shown in FIG. 3A, FIG. 3B, or FIG. In the second and third embodiments, the surfaces of the first wiring 112-1 and the third wiring 112-3 are slightly oxidized, but oxidation hardly occurs regardless of the shape and width. Was confirmed. In Example 1, the variation of the dielectric loss of the insulating film 102 was not confirmed, and in Examples 2 and 3, the variation was negligible for practical use. Further, in any of Example 1 to Example 3, no peeling was observed between the second wiring 112-2 and the third protective film 122 provided thereon.

  On the other hand, when a wiring board (Comparative Example 1) having the same structure as that of the wiring board 150 but not having the first protective film 114 and the second protective film 118 is used, the wiring can be used regardless of the width and shape. It was confirmed that 112 was oxidized. In addition, the dielectric loss of the insulating film 102 fluctuated (increased), and it was confirmed that the transmission characteristics were greatly reduced. Further, it was confirmed that separation occurred between the second wiring 112-2 and the third protective film 122 regardless of the width and shape of the wiring 112.

  Thus, it was confirmed that a highly reliable wiring board can be provided by applying the above-described embodiment.

  The embodiments described above as the embodiments of the present disclosure can be implemented in appropriate combination as long as they do not contradict each other. In addition, components that are appropriately added, deleted, or changed in design by those skilled in the art based on each embodiment are also included in the scope of the present disclosure as long as they include the gist of the present disclosure.

  Of course, other operational effects that are different from the operational effects provided by each of the above-described embodiments are obvious from the description of the present specification or can be easily predicted by those skilled in the art. It is understood that this disclosure provides.

  100: Semiconductor device, 102: Insulating film, 104: Second insulating film, 106: Third insulating film, 110: Wiring substrate, 112: Wiring, 112-1: First wiring, 112-2: Second 112-3: third wiring, 112-4: fourth wiring, 112-5: fifth wiring, 112-n: nth wiring, 114: first protective film, 114-1 : First inorganic film, 114-2: second inorganic film, 114-3: third inorganic film, 116: connection pad, 118: second protective film, 118-1: fourth inorganic film, 118-2: Fifth inorganic film, 118-3: Sixth inorganic film, 120: Bump, 122: Third protective film, 122-1: Seventh inorganic film, 122-2: Eighth inorganic film Membrane, 130: support substrate, 132: release layer, 134: bonding layer, 136: seed layer, 137: plating layer, 138: resist Mask, 140: main substrate, 142: connection pad, 144: opening, 150: wiring substrate, 200: semiconductor chip, 200-1: logic LSI, 200-2: memory, 202: bump, 204: resin

Claims (39)

First to nth wirings electrically connected to each other;
An insulating film for embedding the first to nth wirings;
A first protective film located on the insulating film, in contact with the insulating film and including at least one of silicon nitride and silicon oxide; and located on the first protective film, the nth A connection pad electrically connected to the wiring of
The first to nth wirings are stacked such that a (k + 1) th wiring selected from the first to nth wirings is positioned on the kth wiring,
A wiring board in which n is a natural number larger than 1 and k is a natural number smaller than n.   The wiring board according to claim 1, wherein each of the first to nth wirings includes copper. The wiring board according to claim 1, wherein the insulating film has a dielectric loss tangent of 1 × 10 ⁻³ or more and 1 × 10 ⁻² or less. The first protective film includes:
A first inorganic film comprising silicon nitride;
The wiring board according to claim 1, further comprising: a second inorganic film containing silicon oxide on the first inorganic film; and a third inorganic film containing silicon nitride on the second inorganic film.   The wiring board according to claim 4, wherein a thickness of the third inorganic film is larger than a thickness of the first inorganic film and smaller than a thickness of the second inorganic film.   The wiring board according to claim 1, wherein the first protective film is located on the first to nth wirings.   The wiring board according to claim 1, wherein the nth wiring is located on the first protective film.   The wiring board according to claim 1, further comprising a second insulating film on the first protective film and the n-th wiring.   The wiring board according to claim 1, further comprising a second protective film containing at least one of silicon nitride and silicon oxide under the insulating film. The second protective film is
A fourth inorganic film containing silicon nitride;
The wiring board according to claim 9, further comprising: a fifth inorganic film containing silicon oxide under the fourth inorganic film; and a sixth inorganic film containing silicon nitride under the fifth inorganic film.   The wiring board according to claim 10, wherein a thickness of the sixth inorganic film is larger than a thickness of the fourth inorganic film and smaller than a thickness of the fifth inorganic film.   The wiring board according to claim 9, wherein the second protective film is located under the first wiring.   The wiring board according to claim 9, wherein at least a part of the second protective film is sandwiched between the first wiring and the second wiring.   The wiring board according to claim 9, further comprising a third insulating film under the insulating film and the second protective film.   The wiring substrate according to claim 1, wherein the first protective film covers a side surface of the insulating film.   2. The wiring board according to claim 1, further comprising a third protective film positioned on at least one of the first to (n−1) th wirings and in contact with the at least one wiring. The third protective film is
The wiring board according to claim 16, comprising a seventh inorganic film containing silicon nitride, and an eighth inorganic film containing silicon oxide on the seventh inorganic film. A semiconductor device comprising: the wiring substrate according to claim 1; and a semiconductor chip electrically connected to the n-th wiring.   The semiconductor device according to claim 18, further comprising a main substrate electrically connected to the first wiring.   The semiconductor device of claim 18, wherein the semiconductor device is configured to operate as a high frequency device. By sequentially forming a wiring on the substrate, forming an insulating film on the wiring, and forming an opening exposing the wiring in the insulating film, the wiring is embedded in the insulating film and electrically connected to each other. Sequentially forming first to nth wirings connected to each other,
Forming a first protective film on the insulating film;
Forming a connection pad electrically connected to the nth wiring on the nth wiring; and separating the substrate from the first wiring;
The method for manufacturing a semiconductor device, wherein the first protective film includes at least one of silicon nitride and silicon oxide.   The method according to claim 21, wherein the first to nth wirings are formed by electrolytic plating of copper. The method according to claim 21, wherein the insulating film has a dielectric loss tangent of 1 × 10 ⁻³ or more and 1 × 10 ⁻² or less. The first protective film is formed by:
Forming a first inorganic film containing silicon nitride by a plasma CVD method;
Forming a second inorganic film containing silicon oxide on the first inorganic film by a plasma CVD method;
The method according to claim 21, comprising forming a third inorganic film containing silicon nitride on the second inorganic film by a plasma CVD method.   The first protective film is formed so that a thickness of the third inorganic film is larger than that of the first inorganic film and smaller than a thickness of the second inorganic film. The method described.   The method according to claim 21, wherein the first protective film is formed on the n-th wiring.   The method according to claim 21, wherein the first protective film is formed to be positioned between the (n-1) th wiring and the nth wiring.   The method according to claim 21, further comprising forming a second insulating film on the first protective film and the nth wiring. Forming a second protective film on the substrate before forming the insulating film;
The method according to claim 21, wherein the second protective film includes at least one of silicon nitride and silicon oxide. The formation of the second protective film is as follows:
Forming a fourth inorganic film containing silicon nitride by a plasma CVD method;
Forming a fifth inorganic film containing silicon oxide on the fourth inorganic film by a plasma CVD method;
30. The method according to claim 29, comprising forming a sixth inorganic film containing silicon nitride on the fifth inorganic film by a plasma CVD method.   The second protective film is formed so that a thickness of the sixth inorganic film is larger than that of the fourth inorganic film and smaller than a thickness of the fifth inorganic film. The method described.   30. The method according to claim 29, wherein the second protective film is formed after forming the first wiring and before forming the second wiring.   30. The method according to claim 29, wherein the second protective film is formed before forming the first wiring.   30. The method of claim 29, further comprising forming a third insulating film under the second protective film after separating the substrate.   The method of claim 21, wherein the first protective film is formed to cover a side surface of the insulating film. Forming a third protective film in contact with the at least one wiring on at least one of the first to (n-1) th wiring;
The method according to claim 21, wherein the third protective film includes at least one of silicon nitride and silicon oxide. The formation of the third protective film is as follows:
Forming a seventh inorganic film containing silicon nitride by a plasma CVD method;
The method according to claim 36, comprising forming an eighth inorganic film containing silicon oxide on the seventh inorganic film by a plasma CVD method.   The method of claim 21, further comprising connecting a semiconductor chip to the nth wiring before separating the substrate.   The method of claim 21, further comprising connecting a main substrate to the first wiring.

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