JP2016207763A - Component build-in wiring board and manufacturing method therefor - Google Patents

Component build-in wiring board and manufacturing method therefor Download PDF

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JP2016207763A
JP2016207763A JP2015085733A JP2015085733A JP2016207763A JP 2016207763 A JP2016207763 A JP 2016207763A JP 2015085733 A JP2015085733 A JP 2015085733A JP 2015085733 A JP2015085733 A JP 2015085733A JP 2016207763 A JP2016207763 A JP 2016207763A
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hole
electronic component
terminal
insulating plate
main surface
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敬三 櫻井
Keizo Sakurai
敬三 櫻井
石岡　卓
Taku Ishioka
卓 石岡
淳男 川越
Atsuo Kawagoe
淳男 川越
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

Abstract

PROBLEM TO BE SOLVED: To provide a component built-in wiring board excellent in electrical connection reliability of a built-in electronic component electrode and a wiring conductor.SOLUTION: A component built-in wiring board 10 includes an insulation plate 1a having a through hole 7 for housing an electronic component 3, the electronic component 3 housed in the through hole 7, having a terminal 3a only on one principal surface of the insulation plate 1a, and a height smaller than the thickness of the insulation plate 1a, a filling resin 8 filling the space other than the electronic component 3 in the through hole 7, where one principal surface and the other principal surface of the insulation plate 1a are flat polished surface, an insulation layer 1b laminated on one principal surface of the insulation plate 1a in close contact with the polished surface of the filling resin 8, and having a via hole 6 where the terminal 3a is the bottom face, and a wiring conductor 4 formed in the via hole 6 so as to be connected with the terminal 3a. In the electronic component 3, the terminal 3a is located in the through hole 7 while being recessed below the polished surface of one principal surface.SELECTED DRAWING: Figure 1

Description

本発明は、電子部品を内蔵する部品内蔵配線基板およびその製造方法に関するものである。   The present invention relates to a component built-in wiring board that incorporates an electronic component and a method of manufacturing the same.

従来、電子部品を内蔵する部品内蔵配線基板は、以下のようにして製造されていた。まず、電子部品を収容するための貫通孔を有する絶縁板と電子部品とを準備する。電子部品は、高さが絶縁板の厚みよりも小さく、一方の主面のみに複数の端子を有する。次に絶縁板の下面に仮付シートを密着させる。次に貫通孔内の仮付シート上に端子が下側になるように電子部品を載置する。次に貫通孔内の電子部品以外の空間を充填樹脂により充填する。次に絶縁板の下面から仮付シートを除去する。次に絶縁板の上下面からはみ出す充填樹脂を研磨して平坦化する。次に絶縁板の上下面に絶縁層を積層する。次に端子側の絶縁層に端子を底面とするビアホールを形成する。次に絶縁層の表面およびビアホール内に端子に接続する配線導体を形成する。   Conventionally, a component-embedded wiring board incorporating an electronic component has been manufactured as follows. First, an insulating plate having a through hole for accommodating an electronic component and an electronic component are prepared. The electronic component has a height smaller than the thickness of the insulating plate and has a plurality of terminals only on one main surface. Next, the temporary sheet is brought into close contact with the lower surface of the insulating plate. Next, the electronic component is placed on the temporary sheet in the through hole so that the terminal is on the lower side. Next, the space other than the electronic component in the through hole is filled with the filling resin. Next, the temporary sheet is removed from the lower surface of the insulating plate. Next, the filling resin protruding from the upper and lower surfaces of the insulating plate is polished and flattened. Next, an insulating layer is laminated on the upper and lower surfaces of the insulating plate. Next, a via hole whose bottom is the terminal is formed in the insulating layer on the terminal side. Next, a wiring conductor connected to the terminal is formed on the surface of the insulating layer and in the via hole.

特開２００３−３３２４８２号公報JP 2003-332482 A

ところで、この従来の部品内蔵配線基板においては、絶縁板の上下面からはみ出す充填樹脂を研磨する際に、電子部品の端子が同時に研磨される。このとき、端子が過剰に研磨される場合がある。端子が過剰に研磨された場合、端子の接続面が損傷してビアホールを介した配線導体との接続信頼性が損なわれてしまう。本発明は、このような従来の問題点に鑑み案出させたものであり、その課題は、電子部品の端子と配線導体との電気的な接続信頼性に優れる配線基板を提供することにある。   By the way, in this conventional component built-in wiring board, when the filling resin protruding from the upper and lower surfaces of the insulating plate is polished, the terminals of the electronic component are simultaneously polished. At this time, the terminal may be excessively polished. When the terminal is excessively polished, the connection surface of the terminal is damaged and connection reliability with the wiring conductor through the via hole is impaired. The present invention has been devised in view of such conventional problems, and an object of the present invention is to provide a wiring board having excellent electrical connection reliability between terminals of electronic components and wiring conductors. .

本発明の部品内蔵配線基板は、電子部品を収容するための貫通孔を有する絶縁板と、前記貫通孔内に収容されており、前記絶縁板の一方の主面側のみに端子を有するとともに高さが前記絶縁板の厚みよりも小さい電子部品と、前記貫通孔内の前記電子部品以外の空間を充填するとともに前記絶縁板の前記一方の主面側の表面および他方の主面側の表面が平坦な研磨面である充填樹脂と、前記絶縁板の前記一方の主面に前記研磨面と密着するように積層されており、前記端子を底面とするビアホールを有する絶縁層と、前記ビアホール内に前記端子に接続するように形成された配線導体と、を具備して成る部品内蔵配線基板であって、前記電子部品は、前記端子が前記一方の主面側の前記研磨面よりも前記貫通孔内に凹んで位置していることを特徴とするものである。   The wiring board with a built-in component according to the present invention includes an insulating plate having a through-hole for housing an electronic component, and is accommodated in the through-hole, and has a terminal on only one main surface side of the insulating plate and a high height. An electronic component having a thickness smaller than the thickness of the insulating plate, a space other than the electronic component in the through hole, and a surface on the one main surface side and a surface on the other main surface side of the insulating plate Filling resin which is a flat polishing surface, laminated on the one main surface of the insulating plate so as to be in close contact with the polishing surface, an insulating layer having a via hole with the terminal as a bottom surface, and the via hole A wiring board with a built-in component comprising a wiring conductor formed so as to be connected to the terminal, wherein the electronic component has the through hole rather than the polishing surface on the one main surface side. That it ’s recessed inside. It is an butterfly.

また、本発明の部品内蔵配線基板の製造方法は、平板状の絶縁板を準備する工程と、該絶縁板に電子部品を収容するための貫通孔を形成する工程と、前記絶縁板の一方の主面に、前記貫通孔を塞ぐ平坦な仮付シートを仮付けする工程と、前記貫通孔内の前記仮付シート上に、高さが前記絶縁板の厚みよりも小さいとともに、前記絶縁板の他方の主面側のみに端子を有する電子部品を、前記端子が前記絶縁板の前記他方の主面よりも前記貫通孔内に凹んで位置するように載置する工程と、前記貫通孔内の前記電子部品以外の空間を充填樹脂で充填するとともに該充填樹脂を硬化させる工程と、前記仮付シートを除去した後、前記一方の主面側の前記充填樹脂の表面を前記電子部品の一部とともに研磨して平坦な研磨面とするとともに、前記他方の主面側の前記充填樹脂の表面を前記端子に到達しない深さまで研磨して平坦な研磨面とする工程と、前記一方の主面および前記他方の主面に、前記研磨面に密着するように絶縁層をそれぞれ積層する工程と、前記他方の主面側の前記絶縁層に、前記端子を底面とするビアホールを形成するとともに、該ビアホール内に、前記端子と接続する配線導体を形成する工程と、を行うことを特徴とするものである。   The method of manufacturing a component-embedded wiring board according to the present invention includes a step of preparing a flat insulating plate, a step of forming a through hole for accommodating an electronic component in the insulating plate, and one of the insulating plates. A step of temporarily attaching a flat temporary sheet covering the through hole to the main surface, and a height smaller than the thickness of the insulating plate on the temporary sheet in the through hole; Placing an electronic component having a terminal only on the other main surface side so that the terminal is recessed in the through hole from the other main surface of the insulating plate; After filling the space other than the electronic component with a filling resin and curing the filling resin, and removing the temporary sheet, the surface of the filling resin on the one main surface side is part of the electronic component And polished to a flat polished surface, and the other Polishing the surface of the filling resin on the main surface side to a depth that does not reach the terminal to make a flat polishing surface, so that the one main surface and the other main surface are in close contact with the polishing surface A step of laminating insulating layers; and a step of forming a via hole with the terminal as a bottom surface in the insulating layer on the other main surface side, and forming a wiring conductor connected to the terminal in the via hole; , Is characterized by performing.

本発明の部品内蔵配線基板およびその製造方法によれば、絶縁板の貫通孔内に収容された電子部品は、端子が充填樹脂の研磨面よりも貫通孔内に凹んで位置することから、充填樹脂が研磨される際に端子が研磨により損傷を受けることがない。したがって、電子部品の端子と配線導体との電気的な接続信頼性に優れる配線基板を提供することができる。   According to the component built-in wiring board and the manufacturing method thereof of the present invention, the electronic component accommodated in the through hole of the insulating plate is filled because the terminal is located in the through hole rather than the polished surface of the filling resin. The terminal is not damaged by polishing when the resin is polished. Therefore, it is possible to provide a wiring board having excellent electrical connection reliability between the terminals of the electronic component and the wiring conductor.

図１は、本発明の部品内蔵配線基板の一実施形態例を示す概略断面図である。FIG. 1 is a schematic sectional view showing an embodiment of a component built-in wiring board according to the present invention. 図２は、本発明の部品内蔵配線基板の製造方法の一実施形態例を説明するための工程毎の概略断面図である。FIG. 2 is a schematic cross-sectional view for each step for explaining an embodiment of the method for manufacturing a component built-in wiring board according to the present invention. 図２は、本発明の部品内蔵配線基板の製造方法の一実施形態例を説明するための工程毎の概略断面図である。FIG. 2 is a schematic cross-sectional view for each step for explaining an embodiment of the method for manufacturing a component built-in wiring board according to the present invention. 図２は、本発明の部品内蔵配線基板の製造方法の一実施形態例を説明するための工程毎の概略断面図である。FIG. 2 is a schematic cross-sectional view for each step for explaining an embodiment of the method for manufacturing a component built-in wiring board according to the present invention. 図５は、本発明の部品内蔵配線基板の他の実施形態例を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing another embodiment of the component built-in wiring board of the present invention. 図６は、本発明の部品内蔵配線基板の製造方法の他の実施形態例を説明するための工程毎の概略断面図である。FIG. 6 is a schematic cross-sectional view for each process for explaining another embodiment of the method for manufacturing the component built-in wiring board of the present invention.

次に、本発明の部品内蔵配線基板の一実施形態例について図１を基に説明する。図１に示すように、本例の部品内蔵配線基板１０は、コア基板１と、ビルドアップ用の絶縁層２と、電子部品３と、配線導体４と、ソルダーレジスト層５とを備えている。   Next, an embodiment of the component built-in wiring board according to the present invention will be described with reference to FIG. As shown in FIG. 1, the component built-in wiring board 10 of this example includes a core substrate 1, a buildup insulating layer 2, an electronic component 3, a wiring conductor 4, and a solder resist layer 5. .

コア基板１は、絶縁板１ａの上下面に絶縁層１ｂが積層されて成る。絶縁板１ａおよび絶縁層１ｂは、例えばガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成る。絶縁板１ａの厚みは、２０〜１０００μｍである。絶縁層１ｂの厚みは２０〜２００μｍである。コア基板１は、その上面から下面にかけて貫通する複数のスルーホール６を有している。スルーホール６の直径は、５０〜２００μｍ程度である。また、絶縁板１ａには、電子部品３を収容するための貫通孔７が形成されている。貫通孔７の大きさは、電子部品３と貫通孔７の内壁との間に１０〜５００μｍ程度の隙間ができる大きさとなっている。   The core substrate 1 is formed by laminating insulating layers 1b on upper and lower surfaces of an insulating plate 1a. The insulating plate 1a and the insulating layer 1b are made of an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The thickness of the insulating plate 1a is 20 to 1000 μm. The thickness of the insulating layer 1b is 20 to 200 μm. The core substrate 1 has a plurality of through holes 6 penetrating from the upper surface to the lower surface. The diameter of the through hole 6 is about 50 to 200 μm. Further, a through hole 7 for accommodating the electronic component 3 is formed in the insulating plate 1a. The size of the through hole 7 is such that a gap of about 10 to 500 μm is formed between the electronic component 3 and the inner wall of the through hole 7.

コア基板１の上下面およびスルーホール６内には、配線導体４の一部が被着されている。なお、配線導体４が被着されたスルーホール６の内部は、孔埋め樹脂で充填されている。   A part of the wiring conductor 4 is attached to the upper and lower surfaces of the core substrate 1 and the through hole 6. In addition, the inside of the through hole 6 to which the wiring conductor 4 is attached is filled with a hole filling resin.

また、貫通孔７の内部には電子部品３が収容されている。電子部品３は、例えばエポキシ樹脂等のモールド樹脂で封止された樹脂モールド半導体素子や樹脂モールド電子部品モジュールである。電子部品３は、幅および長さがそれぞれ１〜５０ｍｍ、高さが０．２〜４ｍｍ程度の概ね直方体形状であり、その上面のみに複数の端子３ａを有している。端子３ａを含む電子部品３の高さは、絶縁板１の厚みよりも０．０３ｍｍ以上小さい。   The electronic component 3 is accommodated in the through hole 7. The electronic component 3 is, for example, a resin molded semiconductor element or a resin molded electronic component module sealed with a mold resin such as an epoxy resin. The electronic component 3 has a substantially rectangular parallelepiped shape with a width and length of about 1 to 50 mm and a height of about 0.2 to 4 mm, respectively, and has a plurality of terminals 3a only on the upper surface thereof. The height of the electronic component 3 including the terminal 3a is smaller than the thickness of the insulating plate 1 by 0.03 mm or more.

さらに、貫通孔７内の電子部品３以外の空間は、充填樹脂８により充填されている。充填樹脂８は、エポキシ樹脂等の熱硬化性樹脂にシリカ等の無機絶縁物フィラーを含有させた電気絶縁材料から成る。充填樹脂８は、貫通孔７内の電子部品３以外の空間にペースト状の充填樹脂を充填するとともに熱硬化させることにより形成される。充填樹脂８の上下面は、研磨処理により平坦化された研磨面となっている。   Further, the space other than the electronic component 3 in the through hole 7 is filled with the filling resin 8. The filling resin 8 is made of an electrically insulating material in which an inorganic insulating filler such as silica is contained in a thermosetting resin such as an epoxy resin. The filling resin 8 is formed by filling a space other than the electronic component 3 in the through-hole 7 with a paste-like filling resin and thermosetting. The upper and lower surfaces of the filling resin 8 are polished surfaces flattened by a polishing process.

絶縁層２は、絶縁板１ａや絶縁層１ｂと同様に、ガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成る。あるいは、ガラスクロスを含まない熱硬化性樹脂材料から成る。絶縁層２の厚みは、１０〜５０μｍ程度である。絶縁層２には、各絶縁層２を貫通する複数のビアホール９が形成されている。絶縁層２の表面およびビアホール９の内部には、配線導体４の一部が被着されている。   The insulating layer 2 is made of an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, like the insulating plate 1a and the insulating layer 1b. Or it consists of a thermosetting resin material which does not contain glass cloth. The insulating layer 2 has a thickness of about 10 to 50 μm. A plurality of via holes 9 penetrating each insulating layer 2 are formed in the insulating layer 2. A part of the wiring conductor 4 is deposited on the surface of the insulating layer 2 and inside the via hole 9.

配線導体４は、銅箔や銅めっき等の良導電性材料からなる。配線導体４の厚みは５〜５０μｍ程度である。上面側の最表層の配線導体４の一部は、半導体素子Ｓの電極Ｔと接続するための半導体素子接続パッド４ａを形成している。また、下面側の最表層の配線導体４の一部は、外部の電気回路基板に接続するための外部接続パッド４ｂを形成している。これらの半導体素子接続パッド４ａと外部接続パッド４ｂとの間は、ビアホール９およびスルーホール６を介して所定のもの同士が電気的に接続されている。   The wiring conductor 4 is made of a highly conductive material such as copper foil or copper plating. The thickness of the wiring conductor 4 is about 5 to 50 μm. A part of the uppermost wiring conductor 4 on the upper surface side forms a semiconductor element connection pad 4 a for connection to the electrode T of the semiconductor element S. A part of the outermost wiring conductor 4 on the lower surface side forms an external connection pad 4b for connection to an external electric circuit board. These semiconductor element connection pads 4 a and external connection pads 4 b are electrically connected to each other through via holes 9 and through holes 6.

さらに、配線導体４の一部は、電子部品３の端子３ａの直上に設けられたビアホール９を介して電子部品３の端子３ａに接続されている。これにより電子部品３の端子３ａが所定の半導体素子接続パッド４ａおよび外部接続パッド４ｂに電気的に接続されている。なお、端子３ａの直上に設けられたビアホール９は、絶縁層２のみならず充填樹脂８も貫通して端子３ａに達している。   Further, a part of the wiring conductor 4 is connected to the terminal 3 a of the electronic component 3 through a via hole 9 provided immediately above the terminal 3 a of the electronic component 3. Thereby, the terminal 3a of the electronic component 3 is electrically connected to the predetermined semiconductor element connection pad 4a and the external connection pad 4b. The via hole 9 provided immediately above the terminal 3a penetrates not only the insulating layer 2 but also the filling resin 8 and reaches the terminal 3a.

ソルダーレジスト層５は、アクリル変性エポキシ樹脂等の感光性の熱硬化性樹脂に絶縁フィラーを含有させた電気絶縁材料から成る。ソルダーレジスト層５の厚みは、１０〜３０μｍ程度である。   The solder resist layer 5 is made of an electrically insulating material in which an insulating filler is contained in a photosensitive thermosetting resin such as an acrylic-modified epoxy resin. The thickness of the solder resist layer 5 is about 10 to 30 μm.

ところで、本例の部品内蔵配線基板１０においては、貫通孔７内に収容された電子部品３は、下面が充填樹脂８の下面と同一高さの研磨面となっている。さらに電子部品３は、端子３ａが充填樹脂８の上面よりも貫通孔８内に凹んで位置している。   By the way, in the component built-in wiring board 10 of this example, the lower surface of the electronic component 3 accommodated in the through hole 7 is a polished surface having the same height as the lower surface of the filling resin 8. Further, in the electronic component 3, the terminal 3 a is positioned so as to be recessed in the through hole 8 from the upper surface of the filling resin 8.

このように、貫通孔７内に収容された電子部品３は、端子３ａが充填樹脂８の研磨された上面よりも貫通孔７内に凹んで位置することから、充填樹脂８が研磨される際に端子３ａが研磨により損傷を受けることがない。したがって、電子部品３の端３ａ子と配線導体４との電気的な接続信頼性に優れる配線基板１０を提供することができる。   Thus, since the electronic component 3 accommodated in the through hole 7 is located in the through hole 7 so that the terminal 3a is recessed in the through hole 7 from the polished upper surface of the filled resin 8, the electronic resin 3 is polished. The terminal 3a is not damaged by polishing. Therefore, it is possible to provide the wiring board 10 having excellent electrical connection reliability between the end 3a of the electronic component 3 and the wiring conductor 4.

次に、本発明の部品内蔵配線基板の製造方法の実施形態の一例について図２〜図４を基に説明する。なお、上述の部品内蔵配線基板１０の説明において説明した部位と同一の部位には同一の符号を付し、その詳細な説明は省略する。   Next, an example of an embodiment of a method for manufacturing a component built-in wiring board according to the present invention will be described with reference to FIGS. The same portions as those described in the description of the component built-in wiring board 10 are given the same reference numerals, and detailed description thereof is omitted.

まず、図２（ａ）に示すように、絶縁板１ａを準備する。絶縁板１ａは、両面銅張板の銅箔をエッチングにより除去することにより形成される。   First, as shown in FIG. 2A, an insulating plate 1a is prepared. The insulating plate 1a is formed by removing the copper foil of the double-sided copper-clad plate by etching.

次に、図２（ｂ）に示すように、絶縁板１ａに貫通孔７を形成する。貫通孔７の形成は、ルータ加工により行われる。   Next, as shown in FIG. 2B, a through hole 7 is formed in the insulating plate 1a. Formation of the through-hole 7 is performed by router processing.

次に、図２（ｃ）に示すように、絶縁板１ａの下面に貫通孔７を塞ぐようにして仮付シート１１を仮付する。仮付シート１１としては、絶縁板１ａ側に微粘着剤を塗布した粘着性を有する樹脂から成るシートを用いる。仮付シート１１の厚みは１０〜３００μｍ程度が好ましい。   Next, as shown in FIG. 2C, a temporary sheet 11 is temporarily attached to the lower surface of the insulating plate 1a so as to close the through hole 7. As the temporary attachment sheet 11, a sheet made of an adhesive resin in which a slight adhesive is applied to the insulating plate 1 a side is used. The thickness of the temporary attachment sheet 11 is preferably about 10 to 300 μm.

次に、図２（ｄ）に示すように、貫通孔７内の仮付シート１１上に電子部品３を載置する。電子部品３は、端子３ａが上側になるように載置される。このとき、端子３ａが絶縁板１ａの上面より０．１ｍｍ以上貫通孔７内に凹んで位置するようにする。   Next, as illustrated in FIG. 2D, the electronic component 3 is placed on the temporary sheet 11 in the through hole 7. The electronic component 3 is placed so that the terminal 3a is on the upper side. At this time, the terminal 3a is positioned to be recessed in the through hole 7 by 0.1 mm or more from the upper surface of the insulating plate 1a.

次に、図２（ｅ）に示すように、貫通孔７内の電子部品３以外の空間にペースト状の封止樹脂８を充填するとともに熱硬化させる。ペースト状の封止樹脂８は、未硬化のエポキシ樹脂組成物とシリカ等の無機絶縁物フィラーを含有し、貫通孔７内の電子部品３以外の空間を良好に充填可能な粘度を有している。   Next, as shown in FIG. 2E, a space other than the electronic component 3 in the through-hole 7 is filled with a paste-like sealing resin 8 and thermally cured. The paste-like sealing resin 8 contains an uncured epoxy resin composition and an inorganic insulating filler such as silica, and has a viscosity capable of satisfactorily filling a space other than the electronic component 3 in the through hole 7. Yes.

次に、図３（ｆ）に示すように、絶縁板１ａの下面から仮付シート１１を剥ぎ取って除去する。このとき、電子部品３の下面が露出する。また、電子部品３の電極３ａは、充填樹脂８内に埋没した状態となる。   Next, as shown in FIG. 3F, the temporary sheet 11 is peeled off from the lower surface of the insulating plate 1a and removed. At this time, the lower surface of the electronic component 3 is exposed. In addition, the electrode 3 a of the electronic component 3 is buried in the filling resin 8.

次に、図３（ｇ）に示すように、充填樹脂８の上下面を研磨処理して平坦な研磨面とする。このとき、電子部品３の下面は充填樹脂８とともに研磨される。また、充填樹脂８の上面は、電子部品３の端子３ａに到達しない深さまで研磨する。このとき、端子３ａを充填樹脂８の上面側の研磨面から１０μｍ以上貫通孔７に凹んで位置させる。この場合、絶縁板１ａの貫通孔７内に収容された電子部品３は、端子３ａが充填樹脂８の研磨面よりも貫通孔７内に凹んで位置することから、充填樹脂８が研磨される際に端子３ａが研磨により損傷を受けることがない。   Next, as shown in FIG. 3G, the upper and lower surfaces of the filling resin 8 are polished to form flat polished surfaces. At this time, the lower surface of the electronic component 3 is polished together with the filling resin 8. Further, the upper surface of the filling resin 8 is polished to a depth that does not reach the terminal 3 a of the electronic component 3. At this time, the terminal 3 a is positioned to be recessed in the through hole 7 by 10 μm or more from the polishing surface on the upper surface side of the filling resin 8. In this case, in the electronic component 3 accommodated in the through hole 7 of the insulating plate 1a, since the terminal 3a is located in the through hole 7 so as to be recessed from the polishing surface of the filled resin 8, the filled resin 8 is polished. At this time, the terminal 3a is not damaged by polishing.

次に、図３（ｈ）に示すように、絶縁板１ａの上下面に絶縁層１ｂを積層するとともにさらにその表面に銅箔１２積層する。絶縁層１ｂおよび銅箔１２は、絶縁板１ａの上下面に絶縁層１ｂ用のプリプレグと銅箔１２とを重ね、上下からプレスするとともに加熱してプリプレグを硬化させることにより積層される。これにより、上面側の絶縁層１ｂと絶縁板１ａ上面および充填樹脂８上面ならびに下面側の絶縁層１ｂと絶縁板１ａの下面および充填樹脂８下面ならびに電子部品３下面とが強固に密着する。絶縁層１ｂ用のプリプレグは、ガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂の未硬化樹脂を含浸させたプものを用いる。銅箔１２は、厚みが５〜１８μｍ程度の電解銅箔を用いる。   Next, as shown in FIG. 3 (h), the insulating layer 1b is laminated on the upper and lower surfaces of the insulating plate 1a, and the copper foil 12 is further laminated on the surface thereof. The insulating layer 1b and the copper foil 12 are laminated by overlapping the prepreg for the insulating layer 1b and the copper foil 12 on the upper and lower surfaces of the insulating plate 1a, pressing from above and below, and heating to cure the prepreg. Thereby, the insulating layer 1b on the upper surface side and the upper surface of the insulating plate 1a and the upper surface of the filling resin 8 and the insulating layer 1b on the lower surface side, the lower surface of the insulating plate 1a, the lower surface of the filling resin 8 and the lower surface of the electronic component 3 are firmly adhered. As the prepreg for the insulating layer 1b, a glass cloth in which an uncured resin such as an epoxy resin or a bismaleimide triazine resin is impregnated with a glass cloth is used. As the copper foil 12, an electrolytic copper foil having a thickness of about 5 to 18 μm is used.

次に、図３（ｉ）に示すように、積層された絶縁板１ａおよび絶縁層１ｂならびに銅箔１２を貫通するように、スルーホール６を形成する。スルーホール６の形成は、ドリル加工により行う。あるいは、レーザ加工やブラスト加工を用いても良い。   Next, as shown in FIG. 3 (i), the through hole 6 is formed so as to penetrate the laminated insulating plate 1 a and insulating layer 1 b and the copper foil 12. The through hole 6 is formed by drilling. Alternatively, laser processing or blast processing may be used.

次に、図３（ｊ）に示すように、スルーホール６の内壁および銅箔１２の表面に銅めっき層１３を被着する。銅めっき層１３は、無電解銅めっき層と電解銅めっき層とを順次析出させることにより被着される。無電解銅めっき層の厚みは、０．１〜１μｍ程度である。電解銅めっき層の厚みは、５〜２５μｍ程度である。   Next, as shown in FIG. 3 (j), a copper plating layer 13 is deposited on the inner wall of the through hole 6 and the surface of the copper foil 12. The copper plating layer 13 is deposited by sequentially depositing an electroless copper plating layer and an electrolytic copper plating layer. The thickness of the electroless copper plating layer is about 0.1 to 1 μm. The thickness of the electrolytic copper plating layer is about 5 to 25 μm.

次に、図４（ｋ）に示すように、銅めっき層１３が被着されたスルーホール６内に孔埋め樹脂１４を充填するとともに硬化させる。孔埋め樹脂１４の充填は、スクリーン印刷法により行う。   Next, as shown in FIG. 4 (k), the filling resin 14 is filled in the through hole 6 to which the copper plating layer 13 is deposited and cured. The filling of the hole filling resin 14 is performed by a screen printing method.

次に、図４（ｌ）に示すように、孔埋め樹脂１４の上下端を研磨処理して平坦化する。このとき、絶縁層１ｂ表面の銅箔１２および銅めっき層１３も同時に研磨されて厚みが薄くなる。   Next, as shown in FIG. 4L, the upper and lower ends of the hole filling resin 14 are polished and flattened. At this time, the copper foil 12 and the copper plating layer 13 on the surface of the insulating layer 1b are also polished simultaneously to reduce the thickness.

次に、図４（ｍ）に示すように、上面側の絶縁層１ｂに、電子部品３の端子３ａを底面とするビアホール９を形成する。ビアホール９の形成は、レーザ加工により行う。   Next, as shown in FIG. 4 (m), a via hole 9 having the bottom surface of the terminal 3a of the electronic component 3 is formed in the insulating layer 1b on the upper surface side. The via hole 9 is formed by laser processing.

次に、図４（ｎ）に示すように、研磨された銅箔１２の表面および孔埋め樹脂１４の表面ならびにビアホール９の表面に銅めっき層１５を被着する。銅めっき層１５は、無電解銅めっき層と電解銅めっき層とを順次析出させることにより被着される。無電解銅めっき層の厚みは、０．１〜１μｍ程度である。電解銅めっき層の厚みは、５〜２５μｍ程度である。   Next, as shown in FIG. 4 (n), a copper plating layer 15 is deposited on the surface of the polished copper foil 12, the surface of the hole filling resin 14, and the surface of the via hole 9. The copper plating layer 15 is deposited by sequentially depositing an electroless copper plating layer and an electrolytic copper plating layer. The thickness of the electroless copper plating layer is about 0.1 to 1 μm. The thickness of the electrolytic copper plating layer is about 5 to 25 μm.

次に、図４（ｏ）に示すように、銅箔１２および銅めっき層１５を所定のパターンにエッチングすることにより、コア基板１の上下面におよびビアホール９内に配線導体４を形成する。このとき、ビアホール９の底面を形成する端子３ａは、研磨による損傷を受けていないので、ビアホール９内の配線導体４と端子３ａとが極めて良好に接続される。したがって、本例の部品内蔵配線基板の製造方法によれば、電子部品３の端子３ａと配線導体４との電気的な接続信頼性に優れる配線基板１０を提供することができる。   Next, as shown in FIG. 4 (o), the copper foil 12 and the copper plating layer 15 are etched into a predetermined pattern, thereby forming the wiring conductor 4 on the upper and lower surfaces of the core substrate 1 and in the via hole 9. At this time, since the terminal 3a forming the bottom surface of the via hole 9 is not damaged by polishing, the wiring conductor 4 in the via hole 9 and the terminal 3a are connected very well. Therefore, according to the manufacturing method of the component built-in wiring board of this example, it is possible to provide the wiring board 10 having excellent electrical connection reliability between the terminal 3a of the electronic component 3 and the wiring conductor 4.

次に、コア用の配線導体４が形成されたコア基板１の上下面にビルドアップ用の絶縁層２および配線導体４を常法により必要層形成した後、最後にソルダーレジスト層５を形成することによって図１に示した配線基板１０が完成する。   Next, after forming the necessary layers of the build-up insulating layer 2 and the wiring conductor 4 on the upper and lower surfaces of the core substrate 1 on which the core wiring conductor 4 is formed, the solder resist layer 5 is finally formed. Thereby, the wiring board 10 shown in FIG. 1 is completed.

なお、本発明は、上述の実施形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。   The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

例えば上述の実施形態例では、電子部品３の下面は平坦面であったが、図５に示すように、電子部品３の下面にモールド樹脂から成る突起部３ｂが形成されており、この突起部３ｂの頂面が充填樹脂８の下面とともに研磨処理されていてもよい。この場合、突起部３ｂは、モールド樹脂から形成されていることから、充填樹脂８の下面を研磨処理する際に、突起部３ｂの頂面のみが研磨面に表れるように研磨処理することにより、電子部品３の内部に封止された半導体素子や電子部品モジュールに研磨が到達することがなく、それにより電子部品３内部の半導体素子や電子部品モジュールが研磨により損傷することを有効に防止することができる。   For example, in the embodiment described above, the lower surface of the electronic component 3 is a flat surface. However, as shown in FIG. 5, a protrusion 3b made of mold resin is formed on the lower surface of the electronic component 3, and this protrusion The top surface of 3b may be polished together with the lower surface of the filling resin 8. In this case, since the protrusion 3b is formed of a mold resin, when the lower surface of the filling resin 8 is polished, by polishing so that only the top surface of the protrusion 3b appears on the polishing surface, Polishing does not reach the semiconductor element or electronic component module sealed inside the electronic component 3, thereby effectively preventing the semiconductor element or electronic component module inside the electronic component 3 from being damaged by polishing. Can do.

また、上述の実施形態例では、図４（ｍ）に示すように、スルーホール６内壁に銅めっき層１３を被着するとともにスルーホール６内を孔埋め樹脂１４で充填した後、上面側の絶縁層１ｂに、電子部品３の端子３ａを底面とするビアホール９を設けたが、図２（ａ）〜図３（ｈ）までの工程を行った後、図６（ｉ）に示すように、積層された絶縁板１ａおよび絶縁層１ｂならびに銅箔１２を貫通するようにスルーホール６を形成するとともに、上面側の絶縁層１ｂに手剣士部品３の端子３ａを底面とするビアホール９を設け、次に図６（ｊ）に示すように、スルーホール６の内壁および銅箔１２ならびにビアホール９内の表面に銅めっき層１３を被着してもよい。   Further, in the above-described embodiment, as shown in FIG. 4 (m), the copper plating layer 13 is deposited on the inner wall of the through hole 6 and the inside of the through hole 6 is filled with the hole filling resin 14, and then the upper surface side. A via hole 9 having the bottom surface of the terminal 3a of the electronic component 3 is provided in the insulating layer 1b. After performing the steps from FIG. 2A to FIG. 3H, as shown in FIG. The through hole 6 is formed so as to penetrate the laminated insulating plate 1a and insulating layer 1b and the copper foil 12, and the via hole 9 having the bottom surface of the terminal 3a of the hand swordsman component 3 is provided in the insulating layer 1b on the upper surface side. Next, as shown in FIG. 6 (j), a copper plating layer 13 may be applied to the inner wall of the through hole 6, the copper foil 12, and the surface of the via hole 9.

１ａ・・・絶縁板
１ｂ・・・絶縁層
３・・・・電子部品
３ａ・・・端子
４・・・・配線導体
７・・・・貫通孔
８・・・・充填樹脂
９・・・・ビアホール
１１・・・・仮付シート DESCRIPTION OF SYMBOLS 1a ... Insulating plate 1b ... Insulating layer 3 ... Electronic component 3a ... Terminal 4 ... Wiring conductor 7 ... Through-hole 8 ... Filling resin 9 ... Via hole 11 ... Temporary sheet

Claims (4)

電子部品を収容するための貫通孔を有する絶縁板と、前記貫通孔内に収容されており、前記絶縁板の一方の主面側のみに端子を有するとともに高さが前記絶縁板の厚みよりも小さい電子部品と、前記貫通孔内の前記電子部品以外の空間を充填するとともに前記絶縁板の前記一方の主面側の表面および他方の主面側の表面が平坦な研磨面である充填樹脂と、前記絶縁板の前記一方の主面に前記研磨面と密着するように積層されており、前記端子を底面とするビアホールを有する絶縁層と、前記ビアホール内に前記端子に接続するように形成された配線導体と、を具備して成る部品内蔵配線基板であって、前記電子部品は、前記端子が前記一方の主面側の前記研磨面よりも前記貫通孔内に凹んで位置していることを特徴とする部品内蔵配線基板。   An insulating plate having a through-hole for accommodating an electronic component, and the terminal is accommodated in the through-hole, and has a terminal only on one main surface side of the insulating plate, and the height is higher than the thickness of the insulating plate. A small electronic component, and a filling resin that fills a space other than the electronic component in the through-hole and has a flat polished surface on the one main surface side and on the other main surface side of the insulating plate The insulating plate is laminated on the one main surface of the insulating plate so as to be in close contact with the polishing surface, and has an insulating layer having a via hole with the terminal as a bottom surface, and is formed to connect to the terminal in the via hole. A wiring board with a built-in component comprising the wiring conductor, wherein the electronic component is positioned such that the terminal is recessed in the through-hole from the polished surface on the one main surface side. Component built-in wiring board. 前記電子部品は、前記他方の主面側に樹脂から成る突起部が形成されており、該突起部の頂面が前記他方の主面側の前記充填樹脂の表面とともに研磨されていることを特徴とする請求項１記載の部品内蔵配線基板。   In the electronic component, a protrusion made of resin is formed on the other main surface, and the top surface of the protrusion is polished together with the surface of the filling resin on the other main surface. The component built-in wiring board according to claim 1. 平板状の絶縁板を準備する工程と、該絶縁板に電子部品を収容するための貫通孔を形成する工程と、前記絶縁板の一方の主面に、前記貫通孔を塞ぐ平坦な仮付シートを仮付けする工程と、前記貫通孔内の前記仮付シート上に、高さが前記絶縁板の厚みよりも小さいとともに、前記絶縁板の他方の主面側のみに端子を有する電子部品を、前記端子が前記絶縁板の前記他方の主面よりも前記貫通孔内に凹んで位置するように載置する工程と、前記貫通孔内の前記電子部品以外の空間を充填樹脂で充填するとともに該充填樹脂を硬化させる工程と、前記仮付シートを除去した後、前記一方の主面側の前記充填樹脂の表面を前記電子部品の一部とともに研磨して平坦な研磨面とするとともに、前記他方の主面側の前記充填樹脂の表面を前記端子に到達しない深さまで研磨して平坦な研磨面とする工程と、前記一方の主面および前記他方の主面に、前記研磨面に密着するように絶縁層をそれぞれ積層する工程と、前記他方の主面側の前記絶縁層に、前記端子を底面とするビアホールを形成するとともに、該ビアホール内に、前記端子と接続する配線導体を形成する工程と、を行うことを特徴とする部品内蔵配線基板の製造方法。   A step of preparing a flat insulating plate, a step of forming a through hole for accommodating an electronic component in the insulating plate, and a flat temporary sheet for closing the through hole on one main surface of the insulating plate An electronic component having a height smaller than the thickness of the insulating plate on the temporary sheet in the through hole and having terminals only on the other main surface side of the insulating plate, A step of placing the terminal so as to be recessed in the through-hole from the other main surface of the insulating plate; and filling a space other than the electronic component in the through-hole with a filling resin; A step of curing the filling resin, and after removing the temporary sheet, the surface of the filling resin on the one main surface side is polished together with a part of the electronic component to form a flat polishing surface, and the other The surface of the filling resin on the main surface side of the lead reaches the terminal Polishing to a flat depth by polishing to a flat depth, laminating an insulating layer on the one main surface and the other main surface so as to be in close contact with the polishing surface, and the other main surface Forming a via hole having the terminal as a bottom surface in the insulating layer on the side, and forming a wiring conductor connected to the terminal in the via hole. Method. 前記電子部品は、前記他方の主面側に樹脂から成る突起部が形成されており、該突起部の頂面が前記他方の主面側の前記充填樹脂の表面とともに研磨されることを特徴とする請求項３記載の部品内蔵配線基板の製造方法。   The electronic component has a protrusion made of resin on the other main surface side, and the top surface of the protrusion is polished together with the surface of the filling resin on the other main surface side. A method of manufacturing a component built-in wiring board according to claim 3.
JP2015085733A 2015-04-20 2015-04-20 Component build-in wiring board and manufacturing method therefor Pending JP2016207763A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200028602A (en) * 2018-09-07 2020-03-17 삼성전기주식회사 Printed circuit board with embedded interconnect structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200028602A (en) * 2018-09-07 2020-03-17 삼성전기주식회사 Printed circuit board with embedded interconnect structure
KR102163059B1 (en) 2018-09-07 2020-10-08 삼성전기주식회사 Printed circuit board with embedded interconnect structure

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