JP2016119586A - Δς変調器およびそのプログラム - Google Patents
Δς変調器およびそのプログラム Download PDFInfo
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- JP2016119586A JP2016119586A JP2014258600A JP2014258600A JP2016119586A JP 2016119586 A JP2016119586 A JP 2016119586A JP 2014258600 A JP2014258600 A JP 2014258600A JP 2014258600 A JP2014258600 A JP 2014258600A JP 2016119586 A JP2016119586 A JP 2016119586A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
- H03M7/3033—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs
- H03M7/3035—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs with provisions for rendering the modulator inherently stable, e.g. by restricting the swing within the loop, by removing part of the zeroes using local feedback loops, by positioning zeroes outside the unit circle causing the modulator to operate in a chaotic regime
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
- H03M7/3028—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
Description
2 入力端子
3 出力端子
4 ループフィルタ
5 n値量子化器
6 セレクタ
11、14 減算器
12、15 加算器
13、16、17 遅延器
Claims (4)
- m値(m:3以上の整数)デジタル信号をn値(n:mより小さい2以上の整数)デジタル信号に変換して出力するΔΣ変調器であって、
該m値デジタル信号が減算器に入力されるループフィルタと、
該ループフィルタから出力される第1出力信号を入力されて該n値デジタル信号である第2出力信号を出力するn値量子化器と、
該第1出力信号および該第2出力信号が入力されて、該第1出力信号の絶対値が所定値以上の場合に該第1出力信号を該ループフィルタの該減算器に帰還し、該第1出力信号の絶対値が所定値未満の場合に該第2出力信号を該ループフィルタの該減算器に帰還する切換器と、
を備え、
該切換器の該所定値が、該n値デジタル信号が取り得る量子化値の絶対値の最大値よりも大きく設定されている、
ΔΣ変調器。 - 前記n値量子化器が、前記n=2の場合に、出力する2値デジタル信号の信号値を第1の量子化値または第2の量子化値のいずれかに定める入力信号に対する閾値を、ゼロ値に設定されている、
請求項1に記載のΔΣ変調器。 - 前記n=2の場合に、前記n値量子化器の前記第1の量子化値および前記第2の量子化値が、絶対値の等しい正および負の量子化値として設定されている、
請求項1または2に記載のΔΣ変調器。 - m値(m:3以上の整数)デジタル信号をn値(n:mより小さい2以上の整数)デジタル信号に変換して出力するΔΣ変調の信号処理をコンピュータに実行させるプログラムであって、
該プログラムは、該コンピュータのプロセッサに、
該m値デジタル信号が減算器に入力されるループフィルタの信号処理を実行させるステップと、
該ループフィルタから出力される第1出力信号を入力されて該n値デジタル信号である第2出力信号を出力するn値量子化の信号処理を実行させるステップと、
該第1出力信号および該第2出力信号が入力されて、該第1出力信号の絶対値が所定値以上の場合に該第1出力信号を該ループフィルタの該減算器に帰還し、該第1出力信号の絶対値が所定値未満の場合に該第2出力信号を該ループフィルタの該減算器に帰還する切換処理を実行させるステップと、
を含み、
該切換処理の該所定値が、該n値デジタル信号が取り得る量子化値の絶対値の最大値よりも大きく設定されている、
プログラム。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014258600A JP6160604B2 (ja) | 2014-12-22 | 2014-12-22 | Δς変調器およびそのプログラム |
US14/957,971 US9455736B2 (en) | 2014-12-22 | 2015-12-03 | ΔΣ modulator and program of ΔΣ modulator |
EP15201265.4A EP3043480A1 (en) | 2014-12-22 | 2015-12-18 | Delta sigma modulator inherently stable |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2014258600A JP6160604B2 (ja) | 2014-12-22 | 2014-12-22 | Δς変調器およびそのプログラム |
Publications (2)
Publication Number | Publication Date |
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JP2016119586A true JP2016119586A (ja) | 2016-06-30 |
JP6160604B2 JP6160604B2 (ja) | 2017-07-12 |
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JP2014258600A Active JP6160604B2 (ja) | 2014-12-22 | 2014-12-22 | Δς変調器およびそのプログラム |
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EP (1) | EP3043480A1 (ja) |
JP (1) | JP6160604B2 (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5742246A (en) * | 1996-03-22 | 1998-04-21 | National Science Council | Stabilizing mechanism for sigma-delta modulator |
US5757301A (en) * | 1997-05-01 | 1998-05-26 | National Science Council | Instability recovery method for sigma-delta modulators |
US6157331A (en) * | 1998-10-01 | 2000-12-05 | Tritech Microelectronics, Ltd. | Sigma delta modulator with automatic saturation detection and recovery |
JP2006523999A (ja) * | 2003-04-16 | 2006-10-19 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | シグマ−デルタ変調器 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI88765C (fi) | 1991-04-09 | 1993-06-28 | Nokia Mobile Phones Ltd | Foerfarande och arrangemang foer stabilering av en hoegre grads sigma-delta-modulator |
JP3303585B2 (ja) | 1995-03-02 | 2002-07-22 | ソニー株式会社 | 分散フィードバック式δς変調器 |
JP4214850B2 (ja) | 2002-08-20 | 2009-01-28 | ソニー株式会社 | ディジタル信号処理装置及びディジタル信号処理方法 |
-
2014
- 2014-12-22 JP JP2014258600A patent/JP6160604B2/ja active Active
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2015
- 2015-12-18 EP EP15201265.4A patent/EP3043480A1/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5742246A (en) * | 1996-03-22 | 1998-04-21 | National Science Council | Stabilizing mechanism for sigma-delta modulator |
US5757301A (en) * | 1997-05-01 | 1998-05-26 | National Science Council | Instability recovery method for sigma-delta modulators |
US6157331A (en) * | 1998-10-01 | 2000-12-05 | Tritech Microelectronics, Ltd. | Sigma delta modulator with automatic saturation detection and recovery |
JP2006523999A (ja) * | 2003-04-16 | 2006-10-19 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | シグマ−デルタ変調器 |
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Publication number | Publication date |
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EP3043480A1 (en) | 2016-07-13 |
JP6160604B2 (ja) | 2017-07-12 |
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