JP2016051741A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2016051741A JP2016051741A JP2014174648A JP2014174648A JP2016051741A JP 2016051741 A JP2016051741 A JP 2016051741A JP 2014174648 A JP2014174648 A JP 2014174648A JP 2014174648 A JP2014174648 A JP 2014174648A JP 2016051741 A JP2016051741 A JP 2016051741A
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- film
- semiconductor device
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- flux
- cleaning
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Abstract
Description
図1は実施の形態1の半導体装置の主要部の構造の一例を示す部分平面図、図2は図1に示すA−A線に沿って切断した構造を示す部分断面図である。
図1に示す本実施の形態1の半導体装置は、ウエハプロセスパッケージ5であり、チップサイズと略同等の小型の半導体パッケージである。
次に、本実施の形態の半導体装置の製造方法について説明する。図3および図4は、それぞれ実施の形態1の半導体装置の製造方法の一部を示すフロー図と断面図である。
図11は実施の形態2の半導体装置の製造方法におけるバンプ搭載前処理の手順の一例を示すフロー図である。
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明はこれまで記載した実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
上記実施の形態1,2では、半導体装置がウエハプロセスパッケージの場合を説明したが、上記半導体装置は、再配置配線を有し、かつこの再配置配線上にNi/Au膜を有するパッケージであれば他の半導体パッケージであってもよい。
さらに、上記実施の形態で説明した技術思想の要旨を逸脱しない範囲内において、変形例同士を組み合わせて適用することができる。
1a 主面
1b 裏面
2a 電極パッド
2e 再配置配線(配線)
2f ポリイミド層(絶縁膜)
2h シード層
2k Au膜
2m 開口部
2n Ni膜
2q 導体
3 半田バンプ
5 ウエハプロセスパッケージ(半導体装置)
Claims (12)
- (a)半導体ウエハの主面に形成された複数の電極パッドのそれぞれに接続され、かつ前記複数の電極パッドのそれぞれの位置を異なる位置に配置する配線上に、Ni膜と前記Ni膜上に形成されたAu膜とから成るNi/Au膜を形成する工程、
(b)前記(a)工程の後、前記Ni/Au膜の表面に対して還元処理を行う工程、
(c)前記(b)工程の後、前記Ni/Au膜上に半田バンプを形成する工程、
を有する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記還元処理は、
(b1)フラックス構成材を塗布する工程、
(b2)前記(b1)工程の後、リフローを行う工程、
(b3)前記(b2)工程の後、洗浄を行う工程、
を有する、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記フラックス構成材は、前記還元処理の後で、かつ前記半田バンプを形成する前に前記Au膜に塗布するフラックス材と同じ材料を使用する、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記半田バンプを形成する前に、前記半導体ウエハの前記主面と反対側の裏面を研磨する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(c)工程では、前記Au膜上に前記半田バンプを搭載した後、
(c1)リフローを行う工程、
(c2)洗浄を行う工程、
を有する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記還元処理は、酸洗浄である、半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、
前記半田バンプを形成した後に、前記半導体ウエハの前記主面と反対側の裏面を研磨する、半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、
前記酸洗浄で用いる酸は、塩酸または硫酸である、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記Au膜を無電解めっきで形成する、半導体装置の製造方法。 - 請求項9に記載の半導体装置の製造方法において、
前記無電解めっきは、置換めっきである、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記Au膜は、前記配線上に形成された絶縁膜の開口部に露出している、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記電極パッドは、Alから成り、
前記配線は、Cuを主成分とする配線であり、
前記配線は、Cr膜を介して前記電極パッドと電気的に接続されている、半導体装置の製造方法。
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US20090230175A1 (en) * | 2008-03-11 | 2009-09-17 | Nec Electronics Corporation | Flux for soldering and method for manufacturing an electronic device using the same |
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JPH11354560A (ja) * | 1998-06-09 | 1999-12-24 | Matsushita Electron Corp | 半導体装置の製造方法 |
JP2005044979A (ja) * | 2003-07-28 | 2005-02-17 | Nippon Steel Corp | ウェハ保管方法及びバンプ形成方法 |
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