JP2015529017A5 - - Google Patents

Download PDF

Info

Publication number
JP2015529017A5
JP2015529017A5 JP2015524304A JP2015524304A JP2015529017A5 JP 2015529017 A5 JP2015529017 A5 JP 2015529017A5 JP 2015524304 A JP2015524304 A JP 2015524304A JP 2015524304 A JP2015524304 A JP 2015524304A JP 2015529017 A5 JP2015529017 A5 JP 2015529017A5
Authority
JP
Japan
Prior art keywords
insulating layer
etching
depositing
groove
upper portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015524304A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015529017A (ja
JP6185062B2 (ja
Filing date
Publication date
Priority claimed from US13/558,218 external-priority patent/US8765609B2/en
Priority claimed from US13/572,492 external-priority patent/US20140045318A1/en
Application filed filed Critical
Priority claimed from PCT/US2013/050046 external-priority patent/WO2014018273A1/en
Publication of JP2015529017A publication Critical patent/JP2015529017A/ja
Publication of JP2015529017A5 publication Critical patent/JP2015529017A5/ja
Application granted granted Critical
Publication of JP6185062B2 publication Critical patent/JP6185062B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2015524304A 2012-07-25 2013-07-11 テーパ付けされた酸化物の堆積/エッチング Expired - Fee Related JP6185062B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US13/558,218 US8765609B2 (en) 2012-07-25 2012-07-25 Deposit/etch for tapered oxide
US13/558,218 2012-07-25
US13/572,492 2012-08-10
US13/572,492 US20140045318A1 (en) 2012-08-10 2012-08-10 Forming a tapered oxide from a thick oxide layer
PCT/US2013/050046 WO2014018273A1 (en) 2012-07-25 2013-07-11 Method of forming a tapered oxide

Publications (3)

Publication Number Publication Date
JP2015529017A JP2015529017A (ja) 2015-10-01
JP2015529017A5 true JP2015529017A5 (sh) 2016-08-25
JP6185062B2 JP6185062B2 (ja) 2017-08-23

Family

ID=48877540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015524304A Expired - Fee Related JP6185062B2 (ja) 2012-07-25 2013-07-11 テーパ付けされた酸化物の堆積/エッチング

Country Status (4)

Country Link
JP (1) JP6185062B2 (sh)
KR (1) KR101955321B1 (sh)
CN (1) CN104488084B (sh)
WO (1) WO2014018273A1 (sh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014102029A1 (de) 2014-02-18 2015-08-20 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von Halbleiterbauelementen und Halbleiterbauelement
JP6203697B2 (ja) * 2014-09-30 2017-09-27 株式会社東芝 半導体装置およびその製造方法
JP6842616B2 (ja) * 2015-09-24 2021-03-17 東京エレクトロン株式会社 凹部フィーチャ内での膜のボトムアップ式付着のための方法
CN105931969A (zh) * 2016-05-31 2016-09-07 上海华虹宏力半导体制造有限公司 终端结构的制造方法
JP6709425B2 (ja) * 2016-05-31 2020-06-17 北九州市 半導体装置
JP6767302B2 (ja) * 2017-04-14 2020-10-14 東京エレクトロン株式会社 成膜方法
JP7337767B2 (ja) 2020-09-18 2023-09-04 株式会社東芝 半導体装置及びその製造方法
JP7492438B2 (ja) 2020-11-02 2024-05-29 株式会社東芝 半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191447B1 (en) * 1999-05-28 2001-02-20 Micro-Ohm Corporation Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same
JP4073176B2 (ja) * 2001-04-02 2008-04-09 新電元工業株式会社 半導体装置およびその製造方法
DE102005043916B3 (de) * 2005-09-14 2006-12-21 Infineon Technologies Austria Ag Leistungshalbleiterbauelement mit einer Feldelektrode und Verfahren zu dessen Herstellung
US7964912B2 (en) * 2008-09-18 2011-06-21 Power Integrations, Inc. High-voltage vertical transistor with a varied width silicon pillar
US20100264486A1 (en) * 2009-04-20 2010-10-21 Texas Instruments Incorporated Field plate trench mosfet transistor with graded dielectric liner thickness
KR101094373B1 (ko) * 2009-07-03 2011-12-15 주식회사 하이닉스반도체 랜딩플러그 전치 구조를 이용한 매립게이트 제조 방법
JP5323610B2 (ja) * 2009-08-18 2013-10-23 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置とその製造方法

Similar Documents

Publication Publication Date Title
JP2015529017A5 (sh)
JP2016532296A5 (sh)
CN103199019B (zh) 具有垂直鳍状件的鳍式场效应晶体管及其形成方法
US9324790B2 (en) Self-aligned dual-height isolation for bulk FinFET
JP2016213468A5 (sh)
US9147612B2 (en) Method for forming a semiconductor structure
JP2016534572A5 (sh)
US9245981B2 (en) Dielectric filler fins for planar topography in gate level
GB2510525A (en) Rare-earth oxide isolated semiconductor fin
JP2006186303A5 (sh)
CN103579007B (zh) 用于鳍式场效应晶体管器件的后栅极隔离区域形成方法
JP2013102149A5 (sh)
JP2013175718A5 (sh)
JP2010503212A5 (sh)
JP2013149963A5 (ja) 半導体装置の作製方法
WO2013002902A3 (en) Method and structure for low resistive source and drain regions in a replacement metal gate process flow
JP2013520844A5 (sh)
JP2014521229A5 (sh)
JP2014204041A5 (sh)
JP2012033896A5 (sh)
JP2011071304A5 (sh)
JP2011086941A5 (sh)
JP2019057603A5 (sh)
JP2013138187A5 (sh)
JP2012104811A5 (sh)