JP2015525499A5 - - Google Patents
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- Publication number
- JP2015525499A5 JP2015525499A5 JP2015513018A JP2015513018A JP2015525499A5 JP 2015525499 A5 JP2015525499 A5 JP 2015525499A5 JP 2015513018 A JP2015513018 A JP 2015513018A JP 2015513018 A JP2015513018 A JP 2015513018A JP 2015525499 A5 JP2015525499 A5 JP 2015525499A5
- Authority
- JP
- Japan
- Prior art keywords
- vcm
- connection
- transistor
- varactor
- adjustment signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102012104472 | 2012-05-23 | ||
| DE102012104472.4 | 2012-05-23 | ||
| PCT/DE2013/200016 WO2013174377A2 (de) | 2012-05-23 | 2013-05-23 | Schaltungsanordnung und verfahren zum kalibrieren von ansteuersignalen für spannungsgesteuerte oszillatoren |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015525499A JP2015525499A (ja) | 2015-09-03 |
| JP2015525499A5 true JP2015525499A5 (https=) | 2016-07-07 |
| JP6460980B2 JP6460980B2 (ja) | 2019-01-30 |
Family
ID=48537785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015513018A Expired - Fee Related JP6460980B2 (ja) | 2012-05-23 | 2013-05-23 | 電圧制御発振器のための作動信号を較正するための回路装置及び方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9484929B2 (https=) |
| EP (1) | EP2853029B1 (https=) |
| JP (1) | JP6460980B2 (https=) |
| DE (1) | DE112013002663A5 (https=) |
| WO (1) | WO2013174377A2 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3485573A2 (de) | 2016-07-14 | 2019-05-22 | Silicon Line GmbH | Vorrichtung und verfahren zum steuerbaren verzoegern elektrischer signale |
| CN111404545B (zh) * | 2020-04-20 | 2022-07-29 | 成都华微电子科技股份有限公司 | 带数字修调功能的振荡器电路和时钟信号生成方法 |
| CN111934678B (zh) * | 2020-09-28 | 2021-01-05 | 深圳英集芯科技有限公司 | 芯片内时钟频率自动校准方法及相关产品 |
| US12603655B1 (en) * | 2024-04-02 | 2026-04-14 | Cadence Design Systems, Inc. | Subranging digital to time converter-based fractional phase locked loop architecture |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5726607A (en) * | 1992-06-15 | 1998-03-10 | Adc Telecommunications, Inc. | Phase locked loop using a counter and a microcontroller to produce VCXO control signals |
| US5631920A (en) * | 1993-11-29 | 1997-05-20 | Lexmark International, Inc. | Spread spectrum clock generator |
| US6259326B1 (en) * | 1999-08-24 | 2001-07-10 | Agere Systems Guardian Corp. | Clock recovery from a burst-mode digital signal each packet of which may have one of several predefined frequencies |
| JP4089938B2 (ja) * | 2000-06-09 | 2008-05-28 | 日本電信電話株式会社 | 電圧制御発振器 |
| US7129763B1 (en) * | 2004-11-08 | 2006-10-31 | Western Digital Technologies, Inc. | Adjusting power consumption of digital circuitry by generating frequency error representing error in propagation delay |
| JP4733152B2 (ja) * | 2008-01-31 | 2011-07-27 | 日本電信電話株式会社 | 周波数制御回路およびcdr回路 |
| JP2010178148A (ja) * | 2009-01-30 | 2010-08-12 | Hitachi Kokusai Electric Inc | バッファ回路 |
| US8125285B2 (en) * | 2009-09-10 | 2012-02-28 | Analog Devices, Inc. | Digitally controlled oscillators |
-
2013
- 2013-05-23 WO PCT/DE2013/200016 patent/WO2013174377A2/de not_active Ceased
- 2013-05-23 EP EP13756304.5A patent/EP2853029B1/de active Active
- 2013-05-23 DE DE112013002663.5T patent/DE112013002663A5/de not_active Withdrawn
- 2013-05-23 JP JP2015513018A patent/JP6460980B2/ja not_active Expired - Fee Related
-
2014
- 2014-11-24 US US14/552,173 patent/US9484929B2/en active Active
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