Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
  • H03B1/00—Details
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
  • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

• phase detector In such circuits for clock and data recovery or CDR circuits, the type of phase detector is basically differentiated:
• the sign of the phase difference of the two inputs of the phase detector is determined (leading or lagging); this may be indicated, for example, by two digital phase detector output signals "up” and “down”, or by a phase detector output signal which may assume three different output levels, for example 200 millivolts leading, 400 Millivolts for phase difference equal to zero and 600 millivolts for lagging; It is characteristic of binary phase detectors that the magnitude of the output voltage does not contain any information about the actual phase difference at the inputs of the
• Phase detector provides - it is only distinguished between phase difference less than zero, phase difference equal to zero, phase difference greater than zero.
• CDR circuits with binary phase detectors are often used for data transmission in the frequency range greater than one gigahertz, because they are easier to implement at limited speed of the technology used and show a very robust behavior (better so-called power supply rejection).
• VCO Voltage Controlled Oscillator
• Fig. 1 shows a first example of a voltage-controlled ring oscillator RO with two tuning inputs Vtunel, Vtune2 from the prior art.
• the frequency of this voltage-controlled oscillator RO can be adjusted separately via these two tuning inputs Vtunel and Vtune2.
• the frequency change is set by four separate varactor (diodes) D1, D2, D3, D4.
• Fig. 2 shows a second example of a voltage-controlled ring oscillator RO 'with two tuning inputs Vtunel, Vtune2 from the prior art.
• the two digital signals up and dnb a fine adjustment of the voltage-controlled
• Oscillators RO 'made, up and dnb can be the digital output signals of a binary phase detector.
• Fig. 3 shows the frequency tuning range of the voltage controlled oscillator RO 'of Fig. 2 when, for example, the voltage on up or on dnb is changed from 100 millivolts to one volt
• Oscillator RO three different output frequencies:
• the present invention has the object, a circuit arrangement according to the preamble of claim 1 and a method according to the preamble of claim 13 educate so that the energy consumption as possible low and the output frequency is as large as possible.
• Phase detector or up / down phase detector so controlled that no longer four, but only two varactor (diod) s or tuning diodes or varactor diodes or varicaps are needed, the frequency change no longer with two control signals, but only with a Drive signal is achieved.
• a low power consumption that is, a low energy consumption feasible, because due to lower parasitic capacity than in the prior art less power is required to achieve the same output frequency.
• a higher output frequency is feasible, because only two varactors (instead of four varactors in the prior art) less parasitic capacitance is generated in the voltage controlled oscillator, so that the layout of the voltage controlled oscillator can be made more compact.
• FIG. 1 in conceptual-schematic representation of a first example of a voltage-controlled oscillator of the prior art, according to the method of the prior art is working;
• Figure 2 is a conceptual schematic of a second example of a prior art voltage controlled oscillator operating according to the prior art method
• Fig. 3 is a diagrammatic representation of the typical frequency-tuning characteristic of the voltage controlled oscillator of Fig. 2, with the driving voltage applied to the right-hand axis;
• Fig. 4 is a conceptual schematic representation of an embodiment of a voltage controlled oscillator which is part of the circuit arrangement according to the invention from Fig. 7 and operates according to the method according to the present invention;
• Fig. 5 is a diagrammatic representation of the frequency tuning characteristic of the voltage controlled oscillator of Fig. 4, with the drive voltage applied to the right axis;
• FIG. 6 is a diagrammatic representation of operating parameter-related deviations in the frequency tuning characteristic from FIG. 5; FIG.
• Fig. 7 is a conceptual schematic of an embodiment of a circuit arrangement according to the present invention operating according to the method of the present invention
• Fig. 8 is a conceptual schematic representation of an embodiment of a calibration oscillator which is part of the circuit arrangement according to the invention from Fig. 7 and operates according to the method according to the present invention;
• FIG. 9 is a conceptual schematic representation of an exemplary embodiment of a reference oscillator which is part of the circuit arrangement according to the invention from FIG. 7 and operates according to the method according to the present invention.
• FIG. 10 is a diagrammatic representation of a visual illustration of the calculations of the circuit arrangement of FIG. 7.
• FIGS. 1 to 10 Identical or similar configurations, elements or features are provided with identical reference symbols in FIGS. 1 to 10.
• FIG Vbb shows an exemplary embodiment of a voltage-controlled ring oscillator 10.
• FIG Vbb be set.
• the cathodic terminal of the first varactor 12 is connected to the source contact or emitter terminal of a first transistor 22 of the voltage controlled oscillator 10 and to the drain contact or collector terminal of a second transistor 24 of the voltage controlled oscillator 10, and the cathodic terminal of the second varactor 14 is connected to the source contact or
• Emitter terminal of a third transistor 26 of the voltage controlled oscillator 10 and to the drain contact or collector terminal of a fourth transistor 28 of the voltage controlled oscillator 10 is connected.
• the source contact or emitter terminal of the second transistor 24 and the source contact or emitter terminal of the fourth transistor 28 are connected to one another and to a current source 20.
• the gate contact or base terminal of the first transistor 22 and the gate contact or base terminal of the third transistor 26 are connected to each other and are applied with a bias voltage or bias voltage V bias.
• the drain contact or collector terminal of the first transistor 22 and the drain contact or collector terminal of the third transistor 26 provide the output signal Ve of the voltage-controlled oscillator 10.
• Fig. 5 shows the typical frequency tuning characteristic when the drive voltage Vbb is varied in the range of 100 millivolts to 700 millivolts.
• the oscillator 10 now receives three discrete voltages at the tuning input Vbb, corresponding to the voltages generated by the output of the binary phase detector, and thus generates three discrete output frequencies:
• Vbb 200 millivolts-> output frequency fO - df;
• Vbb 400 millivolts-> output frequency fO;
• Vbb 600 millivolts-> output frequency fO + df.
• the present invention has a calibration circuit 100, as illustrated by an exemplary embodiment in FIG. 7:
• the calibration circuit 100 of FIG. 7 has two additional oscillators 30, 50 of substantially the same type as the main oscillator 10 described above with reference to FIG. However, these two additional oscillators 30, 50 can be operated at a much lower frequency and thus with much lower power consumption than the main oscillator 10; Nevertheless, these two additional oscillators 30, 50 im
• the anodic terminal of a first varactor 52 of the calibration oscillator 50 is supplied with the first tuning voltage Vcm and the second tuning voltage Vcm-, and the anodic
• Connection of a second varactor 54 of the calibration oscillator 50 is applied to the first tuning voltage Vcm and to the third tuning voltage Vcm +.
• the cathodic terminal of the first varactor 52 and the cathodic terminal of the second varactor 54 are connected to each other with the source contact or emitter terminal of a first one
• Transistor 62 of the calibration oscillator 50 and with the drain contact or collector terminal of a second transistor 64 of the calibration oscillator 50 is connected.
• the anodic terminal of a third varactor 56 of the calibration oscillator 50 is supplied with the first tuning voltage Vcm and the second tuning voltage Vcm-, and the anodic
• Connection of a fourth varactor 58 of the calibration oscillator 50 is applied to the first tuning voltage Vcm and to the third tuning voltage Vcm +.
• the cathodic terminal of the third varactor 56 and the cathodic terminal of the fourth varactor 58 are connected to each other with the source contact or emitter terminal of a third one
• Transistor 66 of the calibration oscillator 50 and the drain contact or collector terminal of a fourth transistor 68 of the calibration oscillator 50 is connected.
• the source contact or emitter terminal of the second transistor 64 and the source contact or emitter terminal of the fourth transistor 68 are connected to one another and to a current source 60 connected.
• the gate contact or base terminal of the first transistor 62 and the gate contact or base terminal of the third transistor 66 are connected to each other and are applied with a bias voltage or bias voltage Vbias.
• the drain contact or collector terminal of the first transistor 62 and the drain contact or collector terminal of the third transistor 66 provide the output signal Vc of the calibration oscillator 50.
• the other of the two additional oscillators 30, 50 is a reference oscillator 30 exemplarily illustrated with reference to FIG. 9, which is assigned to the calibration oscillator 50 in a clock-wise manner.
• connection of a second varactor 34 of the reference oscillator 30 are applied to a reference potential or reference potential GND, namely at ground potential or ground potential or zero potential.
• GND reference potential or reference potential
• Varactors 34 are connected to each other, to the source contact or emitter terminal of a first transistor 42 of the reference oscillator 30 and to the drain contact or collector terminal of a second transistor 44 of the reference oscillator 30.
• connection of a fourth varactor 38 of the reference oscillator 30 are applied to the reference potential or reference potential GND, namely at ground potential or ground potential or zero potential.
• Varactors 38 are connected to each other, to the source contact or emitter terminal of a third transistor 46 of the reference oscillator 30 and to the drain contact or collector terminal of a fourth transistor 48 of the reference oscillator 30.
• Emitter terminal of the fourth transistor 48 are connected to each other and to a power source 40.
• the gate contact or base terminal of the first transistor 42 and the gate contact or base terminal of the third transistor 46 are connected to each other and are applied with a bias voltage or bias voltage Vbias.
• the drain contact or collector terminal of the first transistor 42 and the drain contact or collector terminal of the third transistor 46 provide the output signal Vr of the reference oscillator 30.
• varactor diodes or tuning diodes or varicabs 12, 14, 32, 34, 36, 38, 52, 54, 56, 58 are electronic semiconductor devices in which a variation occurs by changing the applied voltage the capacity of for example 10 to 1 reach, so that an electrically controllable capacity is available.
• a portion of the aforementioned transistors 22, 24, 26, 28, 42, 44, 46, 48, 62, 64, 66, 68 may or may be any of the foregoing transistors 22, 24, 26, 28, 42, 44, 46, 48, 62 , 64, 66, 68 can be used, in particular, as field effect transistors (FET), for example as metal oxide semiconductor devices.
• FET field effect transistors
• MOSFET Field-effect transistor
• MOSFET such as n-type metal-oxide-semiconductor field-effect transistors (n-type MOSFETs) may be formed.
• a clock counter 70 connected downstream of the calibration oscillator 50 and the reference oscillator 30 compares on the basis of the output signal Vc of the
• the resulting from the difference of these two clock numbers N clock error DE (so-called clock cycle error) is integrated in the clock counter 70 and provided as a digital bus signal to the clock counter 70 subsequent digital-to-analog converter 90 as an input signal.
• the digital-to-analog converter 90 converts the clock error DE into an analog signal which sets the tuning voltage Vcm, Vcm-, Vcm + in the calibration oscillator 50 to the correct value.
• Calibration oscillator 50 illustrates
• N coun t @ 6oo [N * T ref ⁇ o ref * N 0 ' 5 + ⁇ 60 ⁇ * ( ⁇ * ⁇ ⁇ ⁇ 6 ⁇ ) 0 ' 5 ] / ⁇ 60 ⁇ ;
• Number N count @ 20 o [N * T ref ⁇ 2 * ⁇ ⁇ * ⁇ 0 ' 5 ] / ⁇ 200 .
• GND reference potential or reference potential in particular ground potential or ground potential or zero potential
• RO voltage-controlled oscillator in particular voltage-controlled ring oscillator
• RO 'voltage-controlled oscillator in particular voltage-controlled ring oscillator
• T4 fourth transistor of the voltage-controlled oscillator RO '( prior art, see Fig. 2)
• Vcm first tuning signal of the calibration oscillator 50

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
• Manipulation Of Pulses (AREA)

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• 2013
  • 2013-05-23 WO PCT/DE2013/200016 patent/WO2013174377A2/de not_active Ceased
  • 2013-05-23 EP EP13756304.5A patent/EP2853029B1/de active Active
  • 2013-05-23 DE DE112013002663.5T patent/DE112013002663A5/de not_active Withdrawn
  • 2013-05-23 JP JP2015513018A patent/JP6460980B2/ja not_active Expired - Fee Related
• 2014
  • 2014-11-24 US US14/552,173 patent/US9484929B2/en active Active

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