JP2015513218A - パワー半導体装置およびその製造方法 - Google Patents
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Abstract
Description
4層構造を有する先行技術のパンチスルー絶縁ゲートバイポーラトランジスタ(IGBT)は、コレクタ側のコレクタ電極と、コレクタ側とは反対にあるエミッタ側のエミッタ電極とを備える。(n−)ドープされたドリフト層がエミッタ電極とコレクタ電極との間に位置する。エミッタ側には、nドープされたソース領域を取囲むpドープされたベース層が配置される。これらのソース領域とベース層とはエミッタ電極と電気的に接している。絶縁層によってすべての他の層から電気的に絶縁されるゲート電極もエミッタ側に配置される(プレーナゲートまたはトレンチゲート)。
そのような装置は、非パンチスルー(NPT)装置にさらに進化し、この中にはバッファ層が存在せず、pコレクタ層が(n−)ドープされたドリフト層にすぐ隣接している。そのような装置は、スイッチング能力およびそのようなチップの電流共有という点でいくつかの利点を与え、高電流モジュールにおいてIGBTを用いるのを可能にした。
−第1の主側および第1の主側とは反対の第2の主側を有する第1の導電型のウェハを設けることと、
−第1の導電型とは異なる第2の導電型または第1の導電型のドーパントを第2の主側に適用して、それぞれ第1または第2の導電型の層を形成することと、
−その後、第2の主側にチタン堆積層を堆積することとを備え、チタンの融点は1660℃、すなわちシリコン(1410℃)よりも高く、さらに
−チタン堆積層をアニールし、これにより、同時に、チタン堆積層とウェハとの間の界面に金属間化合物層が形成され、かつウェハの中にドーパントが拡散されることと、
−第2の側の上に第1の金属電極層を作製することとを備える。
図中で用いる参照記号およびその意味は、参照記号の一覧に要約される。一般的に、同様のまたは同様に機能する部分には同じ参照記号が与えられる。記載の実施形態は、例として意味されるものであり、発明を限るものではない。
−第1の導電型とは異なる第2の導電型または第1の導電型のドーパントを第2の主側15に適用して、第2または第1の導電型の層2を形成する(図2b)。
nまたはpドープされた層2,2′の作製のためのドーパントを、ドーパントの堆積または打込みによって第2の主側15に適用することができる。半導体の種類に依存して、ドーパントはn型またはp型である。たとえば、半導体がダイオードである場合はドーパントはn型であってもよく、半導体がIGBTである場合はp型ドーパントが適用される。(nまたはp型イオンのいずれかで予めドープされた)予めドープされた非晶質シリコンもドーパントとして適用可能である。
1 ウェハ、10 ドリフト層、11 第1の主側、13 バッファ層、15 第2の主側、100、110、120 発明のIGBT、150 発明のダイオード、2,2′ 第1または第2の導電型の層、3 チタン堆積層、35 金属間化合物層、4 第1の金属電極層、5 ベース層、55 アノード層、6 ソース領域、7,7′ ゲート電極、72 第1の絶縁層、74 第2の絶縁層、75 導電層、8 第2の金属電極層
Claims (12)
- パワー半導体装置を製造するための方法であって、
第1の導電型のウェハ(1)を設けるステップを備え、ウェハは、第1の主側(11)および前記第1の主側(11)とは反対の第2の主側(15)を有し、補正していないドーピング濃度を有するウェハの一部はドリフト層(10)を形成し、さらに
前記第2の主側(15)に、前記第1の導電型の層(2′)を形成するための前記第1の導電型のドーパント、および前記第2の導電型の層(2)を形成するための、前記第1の導電型とは異なる第2の導電型のドーパントのうち少なくとも1つを適用するステップと、
その後、前記第2の主側(15)上にチタン堆積層(3)を堆積するステップと、
前記チタン堆積層(3)をレーザアニールして、これにより、同時に、前記チタン堆積層(3)と前記ウェハ(1)との間の界面に金属間化合物層(35)が形成され、かつ前記少なくとも1つのドーパントが前記ウェハ(1)の中に拡散されるステップと、
前記第2の側(15)上に第1の金属電極層(4)を作製するステップとを備える、方法。 - 厚みが5〜200nmの間、特に10〜50nmの間である前記チタン堆積層(3)を堆積することを特徴とする、請求項1に記載の方法。
- 前記ドーパントを打込むまたは堆積することによって前記少なくとも1つのドーパントを適用することを特徴とする、請求項1から2のいずれかに記載の方法。
- 予めドープされた非晶質シリコンをドーパントとして堆積することによって前記少なくとも1つのドーパントを適用することを特徴とする、請求項1から2のいずれかに記載の方法。
- 前記第1の金属電極層(4)を焼結することを特徴とする、請求項1から4のいずれかに記載の方法。
- 前記第1の金属電極層(4)を作製する前に前記金属間化合物層(35)および前記チタン堆積層(3)を除去することを特徴とする、請求項1から5のいずれかに記載の方法。
- 前記第1の金属電極層(4)を作製する前に前記チタン堆積層(3)を除去し、前記金属間化合物層(35)を維持することを特徴とする、請求項1から5のいずれかに記載の方法。
- 前記ウェハ(1)としてシリコンまたは広バンドギャップのウェハを設けることを特徴とする、請求項1から7のいずれかに記載の方法。
- 前記ウェハ(1)を設ける前に前記ウェハ(1)の中にバッファ層(13)を導入し、バッファ層(13)は前記ドリフト層(10)と前記第2の主側(15)との間に導入され、バッファ層(13)は前記ドリフト層(10)よりもドーピング濃度が高いことを特徴とする、請求項1から8のいずれかに記載の方法。
- IGBT、特に逆導通IGBT、またはダイオードを前記パワー半導体装置として製造することを特徴とする、請求項1から9のいずれかに記載の方法。
- パワー半導体装置であって、第1の主側(11)および前記第1の主側(11)とは反対の第2の主側(15)を有するウェハ(1)を備え、ウェハ(1)は、前記第2の主側(15)上に、第1の導電型の層(2,2′)および前記第1の導電型とは異なる第2の導電型の層のうち少なくとも1つを備え、ウェハ(1)は、前記第2の主側(15)上に第1の金属電極層(4)を備え、チタンを備える金属間化合物層(35)が前記第1の金属電極層(4)と前記第1の導電型の前記層(2′)および前記第2の導電型の前記層(2)の少なくとも1つとの間に配置されることを特徴とする、パワー半導体装置。
- 前記金属間化合物層(35)と前記第1の金属電極層(8)との間にチタン堆積層(35)を備えることを特徴とする、請求項11に記載のパワー半導体装置。
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WO2016075242A1 (en) * | 2014-11-13 | 2016-05-19 | Abb Technology Ag | Method for manufacturing a power semiconductor device |
CN105895707B (zh) * | 2015-01-26 | 2020-02-07 | 三垦电气株式会社 | 半导体装置及其制造方法 |
CN104637803B (zh) * | 2015-01-30 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | 改善igbt背面金属化的工艺方法 |
CN105261564B (zh) * | 2015-11-04 | 2018-05-29 | 株洲南车时代电气股份有限公司 | 一种逆导igbt的制备方法 |
DE112017003587B4 (de) * | 2016-07-15 | 2024-05-29 | Rohm Co., Ltd. | Halbleitervorrichtung und verfahren zur herstellung einer halbleitervorrichtung |
US10361128B2 (en) * | 2017-01-11 | 2019-07-23 | International Business Machines Corporation | 3D vertical FET with top and bottom gate contacts |
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