JP2015507743A5 - - Google Patents
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- JP2015507743A5 JP2015507743A5 JP2014550289A JP2014550289A JP2015507743A5 JP 2015507743 A5 JP2015507743 A5 JP 2015507743A5 JP 2014550289 A JP2014550289 A JP 2014550289A JP 2014550289 A JP2014550289 A JP 2014550289A JP 2015507743 A5 JP2015507743 A5 JP 2015507743A5
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- JP
- Japan
- Prior art keywords
- test
- vector
- processor
- input
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000012360 testing method Methods 0.000 claims 60
- 239000013598 vector Substances 0.000 claims 23
- 238000000034 method Methods 0.000 claims 3
- 230000003139 buffering effect Effects 0.000 claims 2
- 238000006243 chemical reaction Methods 0.000 claims 2
- 230000001902 propagating effect Effects 0.000 claims 2
- 230000009466 transformation Effects 0.000 claims 2
- 238000013507 mapping Methods 0.000 claims 1
- 238000005192 partition Methods 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/338,581 US8719649B2 (en) | 2009-03-04 | 2011-12-28 | Method and apparatus for deferred scheduling for JTAG systems |
| US13/338,581 | 2011-12-28 | ||
| PCT/US2012/061824 WO2013101336A1 (en) | 2011-12-28 | 2012-10-25 | Method and apparatus for deferred scheduling for jtag systems |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2015507743A JP2015507743A (ja) | 2015-03-12 |
| JP2015507743A5 true JP2015507743A5 (enExample) | 2016-02-25 |
Family
ID=47144150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014550289A Pending JP2015507743A (ja) | 2011-12-28 | 2012-10-25 | Jtagシステムの遅延スケジューリングの方法および装置 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8719649B2 (enExample) |
| EP (1) | EP2798360A1 (enExample) |
| JP (1) | JP2015507743A (enExample) |
| KR (1) | KR101545109B1 (enExample) |
| CN (1) | CN104185795A (enExample) |
| WO (1) | WO2013101336A1 (enExample) |
Families Citing this family (19)
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|---|---|---|---|---|
| US8719649B2 (en) * | 2009-03-04 | 2014-05-06 | Alcatel Lucent | Method and apparatus for deferred scheduling for JTAG systems |
| US8407643B1 (en) * | 2011-07-30 | 2013-03-26 | Altera Corporation | Techniques and apparatus to validate an integrated circuit design |
| US9121892B2 (en) * | 2012-08-13 | 2015-09-01 | Analog Devices Global | Semiconductor circuit and methodology for in-system scan testing |
| US9183105B2 (en) | 2013-02-04 | 2015-11-10 | Alcatel Lucent | Systems and methods for dynamic scan scheduling |
| US10451676B2 (en) | 2015-10-27 | 2019-10-22 | Nvidia Corporation | Method and system for dynamic standard test access (DSTA) for a logic block reuse |
| US10481203B2 (en) | 2015-04-04 | 2019-11-19 | Nvidia Corporation | Granular dynamic test systems and methods |
| FR3038084B1 (fr) * | 2015-06-29 | 2017-12-29 | Centre National De La Recherche Scient (C N R S) | Microprocesseur parallele stochastique |
| US10521344B1 (en) * | 2017-03-10 | 2019-12-31 | Pure Storage, Inc. | Servicing input/output (‘I/O’) operations directed to a dataset that is synchronized across a plurality of storage systems |
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| US10436840B2 (en) * | 2017-10-26 | 2019-10-08 | Nvidia Corp. | Broadcast scan network |
| CN108896903A (zh) * | 2018-06-13 | 2018-11-27 | 天津大学 | 基于逻辑加密的逐次验证型安全扫描链装置和方法 |
| CN109697058B (zh) * | 2018-12-11 | 2022-05-17 | 中国航空工业集团公司西安航空计算技术研究所 | 一种适用于嵌入式系统的网络建模方法、装置及存储介质 |
| US11302412B2 (en) * | 2019-06-03 | 2022-04-12 | Advantest Corporation | Systems and methods for simulated device testing using a memory-based communication protocol |
| CN113312735B (zh) * | 2021-05-19 | 2022-06-03 | 太原理工大学 | 一种城市供水管网dma分区方法 |
| KR102373560B1 (ko) * | 2021-08-18 | 2022-03-14 | (주)이노티오 | Ic 칩 스캔 테스트를 위한 테스트 데이터의 사용 가능한 쉬프트 주파수를 찾기 위한 검색용 데이터를 생성하는 방법 및 그 장치 |
| KR102583916B1 (ko) * | 2021-10-26 | 2023-09-26 | 연세대학교 산학협력단 | 저전력 테스트를 위한 스캔 상관관계 기반 스캔 클러스터 리오더링 방법 및 장치 |
| CN114036885B (zh) * | 2021-11-08 | 2025-09-30 | 上海兆芯集成电路股份有限公司 | 内建自测试的方法及互连接口 |
| CN114860571B (zh) * | 2022-03-30 | 2025-01-21 | 阿里云计算有限公司 | 数据处理方法、工具、存储介质以及计算机终端 |
| US12291219B2 (en) * | 2022-10-24 | 2025-05-06 | Nvidia Corporation | Asynchronous in-system testing for autonomous systems and applications |
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| US5949692A (en) * | 1996-08-28 | 1999-09-07 | Synopsys, Inc. | Hierarchical scan architecture for design for test applications |
| JP3385210B2 (ja) | 1998-03-31 | 2003-03-10 | 富士通株式会社 | テストデータスキャン装置およびスキャン方法 |
| JP2957546B1 (ja) * | 1998-04-17 | 1999-10-04 | 三菱電機株式会社 | 半導体集積回路のテストパターン生成装置及び半導体集積回路のテストパターン生成方法 |
| US6061709A (en) | 1998-07-31 | 2000-05-09 | Integrated Systems Design Center, Inc. | Integrated hardware and software task control executive |
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| KR100880832B1 (ko) | 2004-02-10 | 2009-01-30 | 삼성전자주식회사 | 코-디버깅 기능을 지원하는 반도체 집적회로 및 반도체집적회로 테스트 시스템 |
| US7334060B2 (en) | 2004-03-19 | 2008-02-19 | International Business Machines Corporation | System and method for increasing the speed of serially inputting data into a JTAG-compliant device |
| US7143324B2 (en) * | 2004-11-04 | 2006-11-28 | Avago Technologies General Ip (Singapore) Pte. Ltd. | System and method for automatic masking of compressed scan chains with unbalanced lengths |
| JP2006146757A (ja) | 2004-11-24 | 2006-06-08 | Toshiba Corp | デバッグ用レジスタおよびデータ転送方法 |
| US8165167B2 (en) * | 2005-03-10 | 2012-04-24 | Qualcomm Incorporated | Time tracking for a communication system |
| US7206983B2 (en) | 2005-03-31 | 2007-04-17 | Lsi Logic Corporation | Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits |
| US7383478B1 (en) | 2005-07-20 | 2008-06-03 | Xilinx, Inc. | Wireless dynamic boundary-scan topologies for field |
| JP2007147352A (ja) | 2005-11-25 | 2007-06-14 | Sony Corp | 無線インターフェースモジュール及び電子機器 |
| US8015462B2 (en) | 2007-05-11 | 2011-09-06 | Renesas Electronics Corporation | Test circuit |
| US7886263B1 (en) * | 2007-12-10 | 2011-02-08 | Cadence Design Systems, Inc. | Testing to prescribe state capture by, and state retrieval from scan registers |
| US8024693B2 (en) * | 2008-11-04 | 2011-09-20 | Synopsys, Inc. | Congestion optimization during synthesis |
| US8621301B2 (en) * | 2009-03-04 | 2013-12-31 | Alcatel Lucent | Method and apparatus for virtual in-circuit emulation |
| US8533545B2 (en) * | 2009-03-04 | 2013-09-10 | Alcatel Lucent | Method and apparatus for system testing using multiple instruction types |
| US8719649B2 (en) * | 2009-03-04 | 2014-05-06 | Alcatel Lucent | Method and apparatus for deferred scheduling for JTAG systems |
-
2011
- 2011-12-28 US US13/338,581 patent/US8719649B2/en active Active
-
2012
- 2012-10-25 EP EP12783476.0A patent/EP2798360A1/en not_active Withdrawn
- 2012-10-25 JP JP2014550289A patent/JP2015507743A/ja active Pending
- 2012-10-25 CN CN201280070890.2A patent/CN104185795A/zh active Pending
- 2012-10-25 KR KR1020147017632A patent/KR101545109B1/ko not_active Expired - Fee Related
- 2012-10-25 WO PCT/US2012/061824 patent/WO2013101336A1/en not_active Ceased
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