Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
  • G01R31/318558—Addressing or selecting of subparts of the device under test
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
  • G01R31/318314—Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
  • G01R31/318558—Addressing or selecting of subparts of the device under test
  • G01R31/318563—Multiple simultaneous testing of subparts
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Definitions

• SIR TDI which is translated into TISA coding as 12010000.
• the SDR 24 TDI(value) SVF instruction is translated into TISA assembler as three operations:
• the memory 604 stores one or more debugger control programs 605.
• the TS 610 includes a TISA processor 612 coupled to a memory 614.
• the TISA processor 612 may be implemented using any suitable processor, such as SPARC V8 (as depicted and described hereinabove with respect to FIGs. 4A-4E and FIG. 5), INTEL, and the like.
• the memory 604 may be any suitable memory.
• the memory 614 stores TISA Binary Files 616.
• the TISA Binary Files 616.
• interface 609 may be implemented using any suitable communications capabilities, such as Transmission Control Protocol (TCP) / Internet Protocol (IP) or any other suitable communications protocols.
• TCP Transmission Control Protocol
• IP Internet Protocol
• HC 601 and TS 610 may include various other components, such as additional processors, additional memories, internal communications buses, input/output modules, additional support circuits (e.g., power supplies), and the like, as well as various combinations thereof.
• TISA-based testing environment 600 may be implemented in a manner enabling fully-interactive testing capabilities using various other debugger control programs, debugger display programs, interfaces, and the like, as well as various combinations thereof.
• exemplary TISA-based testing environment 700 includes a host computer (HC) 701 , a testing system (TS) 710, and a system under test (SUT) 720.
• HC host computer
• TS testing system
• SUT system under test
• the TS 710 includes a TISA processor 712 and a memory 714.
• the TS 710 includes a TISA processor 712 and a memory 714.
• TISA can enable by leveraging on GDB (or any other suitable debuggers), such as: (a) step-by-step execution while monitoring the variables "sent_value” and “received_value”; (b) on-the-fly modification of the value to be sent to the tap (variable "sent_value”); (c) modification of the looping end condition; (d) monitoring of all variables; and the like, as well as various combinations thereof.
• FIG. 9 depicts one embodiment of a method for adapting an Instruction Set Architecture (ISA) flow of a processor to form a Test Instruction Set Architecture (TISA) flow including TISA instructions adapted for use by the processor in testing at least a portion of a system under test.
• ISA Instruction Set Architecture
• TISA Test Instruction Set Architecture
• method 900 may be performed contemporaneously, or in a different order than depicted and described with respect to FIG. 9.
• FIG. 10 depicts one embodiment of a method for generating
• At step 1 122 at least one pre-processed computer science software file and at least one test operation description file are generated by pre- processing at least one computer science software file.
• an apparatus for use in testing at least a portion of a system under test via a Test Access Port includes a memory for storing a set of instructions of a test instruction set architecture and a processor executing the set of instructions of the test instruction set architecture for testing at least a portion of the system under test via the TAP.
• the set of instructions of the test instruction set architecture includes a first set of instructions comprising a plurality of instructions of an Instruction Set Architecture (ISA) supported by the processor and a second set of
• ISA Instruction Set Architecture
• a computer processor for testing a system under test (SUT) via a Test Access Port (TAP), includes circuitry configured to process instructions according to a test instruction set architecture (TISA) having semantics that enable interaction with the system under test via the TAP.
• TISA test instruction set architecture
• the TISA includes a plurality of instructions of a first type and a plurality of instructions of a second type, where the first type of instructions include instructions of an instruction set architecture (ISA) supported by the computer processor and the second type of instructions include test instructions for testing the system under test via the TAP.
• the test processor architecture may use a test adjunct processor unit architecture in which a central processor unit (CPU) cooperates with a test adjunct processor unit (TAPU) in order to support system testing.
• CPU central processor unit
• TAPU test adjunct processor unit
• the TCPU 1420 may be any CPU suitable for facilitating system testing of a system under test.
• the TCPU 1420 supports a Test Access Port (TAP) interface 1460, which may interface with any suitable TAP (e.g., such as an IEEE 1 149.1 TAP or any other suitable TAP used for testing a system under test).
• TAP Test Access Port
• the TCPU 1420 supports testing capabilities supported by secondary processor 1320 depicted and described with respect to FIG. 13.
• the TAP-related instructions detected by CPU are the TAP-related instructions detected by CPU
• the TAPU 1520 utilizes local test memory 1560 for performing various testing functions, such as storage of TAP-related instructions received from CPU 1510, processing of TAP-related instructions received from CPU 1510, and the like, as well as various combinations thereof.
• the local test memory 1560 may be any suitable processor memory.
• the local test memory 1560 may be relatively small since it handles processing of scan chain segments of the scan chain of the system under test, rather than the entire scan chain (as may be required in an on-chip memory).
• RunTest ⁇ startState>, ⁇ testState>, ⁇ endState>
• This opcode is used to scan the vector value of all "0" and store the captured value into the user data register destination registers The number of bits scanned is defined in
• RunTest/ldle RTI
• PauseDR PDR
• PauseIR PIR
• ScanDR SDR
• SIR ScanIR
• decomposition of a scan chain may be defined in any other suitable manner.
• the exemplary SUT 1700 includes four devices 1710i - 1710
• Scan Segments Level scan operations may require that one or more technological constraints linked to JTAG be addressed. For example, constraints such as the need to define the state of the TAP machine and the risk of using the Pause-DR state (not always implemented), among others, may need to be addressed.
• the actual sequence of TISA instructions can have multiple origins, including one or more of the following: (1 ) the TISA instructions may be statically computed by the TGT, in which case, each time the user wants to access a segment, the entire chain must be scanned (it will be appreciated that, while this solution is not optimized for scan time, it can be useful for embedded systems with limited computational resources and little or no time constraints); (2) the TISA instructions may be issued by a software scheduler, which receives access requests and composes them into scan operations; and/or (3) the TISA instructions may be issued by a hardware scheduler (e.g., such as, but not limited to, what is done for instruction reordering and bypass in some high-performance processors).
• a hardware scheduler e.g., such as, but not limited to, what is done for instruction reordering and bypass in some high-performance processors.
• a set of instructions is generated.
• the set of instructions includes processor instructions associated with an ISA and test instructions for testing the portion of the system under test.
• the test instructions include, for each of the segments of the scan chain, at least one scan operation to be performed on the segment.
• the test instructions may be any type of test instructions, such as conventional test instructions, test instructions of a TISA, and the like, and, thus, may be generated in any suitable manner.
• the set of instructions may be generated in any suitable manner (e.g., in a manner the same as or similar to as depicted and described hereinabove respect to
• Scan Segments Level Although primarily depicted and described herein with respect to embodiments in which embodiments of TISA are used to enable scan operations to be performed at the Scan Segments Level, it will be appreciated that one or more of the Scan Segments Level embodiments depicted and described herein also may be provided in environments using TISA-like instructions architectures, non-TISA instruction architectures and/or non-TISA testing environment implementations, and the like.
• the user application 1940 is configured to issue access requests associated with testing of SUT 1910.
• the user application 1940 may issue access requests for any of the instruments 1915.
• the user application 1940 does not have knowledge of the scan segment composition 1919 of SUT 1910; rather, the user application 1940 merely issues access requests without accounting for the order in which the TISA operations associated with the access requests may be or should be applied to the SUT 1910.
• the access requests issued by user application 1940 are received by scheduler 1930 for scheduling based on the scan segment composition 1919 as determined by the scheduler 1930 from the circuit model of the SUT 1910.
• the user application 1940 is further configured to receive access responses from the scheduler 1930 in response to the access requests, and to provide TISA operations to the TISA processor 1920 in response to the access responses.
• An exemplary process by which the user application 1940 may request and receive access to portions of JTAG scan chain 191 1 using the concept of critical section is depicted and described with respect to FIG. 22.
• the access request does not need to include the associated test data to be scanned for the resource to which access is requested, at least because the scheduler 1930 is configured to return an associated access response to the user application 1940 (at which time user application 1940 may then use the relevant test data, available at and/or to the user application 1940, when providing the associated TISA operation(s) to TISA processor 1920).
• the main CPU 2320 supports a TISA 2322, such that the main CPU
• exemplary SUT 2410 which supports a dynamic JTAG scan path 241 1 , may be represented using a Circuit Model 2420.
• cell X is represented as a super-segment 2421 (represented as the trapezium in FIG. 24).
• the cell X has a status associated therewith, such that super-segment 2421 has a status associated therewith.
• a vector transformation module configured to receive the input test vector from the reordering buffer module and to apply a vector transformation for the input test vector.

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• Engineering & Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Tests Of Electronic Circuits (AREA)
• Test And Diagnosis Of Digital Computers (AREA)

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• 2011
  • 2011-12-28 US US13/338,581 patent/US8719649B2/en active Active
• 2012
  • 2012-10-25 JP JP2014550289A patent/JP2015507743A/ja active Pending
  • 2012-10-25 KR KR1020147017632A patent/KR101545109B1/ko not_active Expired - Fee Related
  • 2012-10-25 EP EP12783476.0A patent/EP2798360A1/en not_active Withdrawn
  • 2012-10-25 WO PCT/US2012/061824 patent/WO2013101336A1/en not_active Ceased
  • 2012-10-25 CN CN201280070890.2A patent/CN104185795A/zh active Pending

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