KR101545109B1 - Jtag 시스템들에 대한 연기 스케줄링을 위한 방법 및 장치 - Google Patents

Jtag 시스템들에 대한 연기 스케줄링을 위한 방법 및 장치 Download PDF

Info

Publication number
KR101545109B1
KR101545109B1 KR1020147017632A KR20147017632A KR101545109B1 KR 101545109 B1 KR101545109 B1 KR 101545109B1 KR 1020147017632 A KR1020147017632 A KR 1020147017632A KR 20147017632 A KR20147017632 A KR 20147017632A KR 101545109 B1 KR101545109 B1 KR 101545109B1
Authority
KR
South Korea
Prior art keywords
test
tisa
processor
vector
operations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020147017632A
Other languages
English (en)
Korean (ko)
Other versions
KR20140136424A (ko
Inventor
미첼 포톨란
트레우렌 브래드포드 반
수레쉬 고얄
Original Assignee
알까뗄 루슨트
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 알까뗄 루슨트 filed Critical 알까뗄 루슨트
Publication of KR20140136424A publication Critical patent/KR20140136424A/ko
Application granted granted Critical
Publication of KR101545109B1 publication Critical patent/KR101545109B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318314—Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
KR1020147017632A 2011-12-28 2012-10-25 Jtag 시스템들에 대한 연기 스케줄링을 위한 방법 및 장치 Expired - Fee Related KR101545109B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/338,581 2011-12-28
US13/338,581 US8719649B2 (en) 2009-03-04 2011-12-28 Method and apparatus for deferred scheduling for JTAG systems
PCT/US2012/061824 WO2013101336A1 (en) 2011-12-28 2012-10-25 Method and apparatus for deferred scheduling for jtag systems

Publications (2)

Publication Number Publication Date
KR20140136424A KR20140136424A (ko) 2014-11-28
KR101545109B1 true KR101545109B1 (ko) 2015-08-17

Family

ID=47144150

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147017632A Expired - Fee Related KR101545109B1 (ko) 2011-12-28 2012-10-25 Jtag 시스템들에 대한 연기 스케줄링을 위한 방법 및 장치

Country Status (6)

Country Link
US (1) US8719649B2 (enExample)
EP (1) EP2798360A1 (enExample)
JP (1) JP2015507743A (enExample)
KR (1) KR101545109B1 (enExample)
CN (1) CN104185795A (enExample)
WO (1) WO2013101336A1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8719649B2 (en) * 2009-03-04 2014-05-06 Alcatel Lucent Method and apparatus for deferred scheduling for JTAG systems
US8407643B1 (en) * 2011-07-30 2013-03-26 Altera Corporation Techniques and apparatus to validate an integrated circuit design
US9121892B2 (en) * 2012-08-13 2015-09-01 Analog Devices Global Semiconductor circuit and methodology for in-system scan testing
US9183105B2 (en) * 2013-02-04 2015-11-10 Alcatel Lucent Systems and methods for dynamic scan scheduling
US10481203B2 (en) 2015-04-04 2019-11-19 Nvidia Corporation Granular dynamic test systems and methods
FR3038084B1 (fr) * 2015-06-29 2017-12-29 Centre National De La Recherche Scient (C N R S) Microprocesseur parallele stochastique
US10473720B2 (en) 2015-10-27 2019-11-12 Nvidia Corporation Dynamic independent test partition clock
US10521344B1 (en) * 2017-03-10 2019-12-31 Pure Storage, Inc. Servicing input/output (‘I/O’) operations directed to a dataset that is synchronized across a plurality of storage systems
US10162005B1 (en) * 2017-08-09 2018-12-25 Micron Technology, Inc. Scan chain operations
US10436840B2 (en) * 2017-10-26 2019-10-08 Nvidia Corp. Broadcast scan network
CN108896903A (zh) * 2018-06-13 2018-11-27 天津大学 基于逻辑加密的逐次验证型安全扫描链装置和方法
CN109697058B (zh) * 2018-12-11 2022-05-17 中国航空工业集团公司西安航空计算技术研究所 一种适用于嵌入式系统的网络建模方法、装置及存储介质
US11302412B2 (en) * 2019-06-03 2022-04-12 Advantest Corporation Systems and methods for simulated device testing using a memory-based communication protocol
CN113312735B (zh) * 2021-05-19 2022-06-03 太原理工大学 一种城市供水管网dma分区方法
KR102373560B1 (ko) * 2021-08-18 2022-03-14 (주)이노티오 Ic 칩 스캔 테스트를 위한 테스트 데이터의 사용 가능한 쉬프트 주파수를 찾기 위한 검색용 데이터를 생성하는 방법 및 그 장치
KR102583916B1 (ko) * 2021-10-26 2023-09-26 연세대학교 산학협력단 저전력 테스트를 위한 스캔 상관관계 기반 스캔 클러스터 리오더링 방법 및 장치
CN114036885B (zh) * 2021-11-08 2025-09-30 上海兆芯集成电路股份有限公司 内建自测试的方法及互连接口
CN114860571B (zh) * 2022-03-30 2025-01-21 阿里云计算有限公司 数据处理方法、工具、存储介质以及计算机终端
US12291219B2 (en) * 2022-10-24 2025-05-06 Nvidia Corporation Asynchronous in-system testing for autonomous systems and applications

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100229036A1 (en) * 2009-03-04 2010-09-09 Suresh Goyal Method and apparatus for system testing using multiple instruction types

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5694399A (en) 1996-04-10 1997-12-02 Xilinix, Inc. Processing unit for generating signals for communication with a test access port
US5828579A (en) * 1996-08-28 1998-10-27 Synopsys, Inc. Scan segment processing within hierarchical scan architecture for design for test applications
US5949692A (en) * 1996-08-28 1999-09-07 Synopsys, Inc. Hierarchical scan architecture for design for test applications
JP3385210B2 (ja) 1998-03-31 2003-03-10 富士通株式会社 テストデータスキャン装置およびスキャン方法
JP2957546B1 (ja) * 1998-04-17 1999-10-04 三菱電機株式会社 半導体集積回路のテストパターン生成装置及び半導体集積回路のテストパターン生成方法
US6061709A (en) 1998-07-31 2000-05-09 Integrated Systems Design Center, Inc. Integrated hardware and software task control executive
US6195774B1 (en) 1998-08-13 2001-02-27 Xilinx, Inc. Boundary-scan method using object-oriented programming language
US6370664B1 (en) 1998-10-29 2002-04-09 Agere Systems Guardian Corp. Method and apparatus for partitioning long scan chains in scan based BIST architecture
US7392431B2 (en) 1999-02-19 2008-06-24 Texas Instruments Incorporated Emulation system with peripherals recording emulation frame when stop generated
US7089404B1 (en) 1999-06-14 2006-08-08 Transmeta Corporation Method and apparatus for enhancing scheduling in an advanced microprocessor
JP2001201543A (ja) 2000-01-18 2001-07-27 Rooran:Kk スキャン・パス構築用プログラムを記録した記録媒体とスキャン・パスの構築方法及びこのスキャン・パスを組み込んだ演算処理システム
US6453456B1 (en) 2000-03-22 2002-09-17 Xilinx, Inc. System and method for interactive implementation and testing of logic cores on a programmable logic device
US6640322B1 (en) 2000-03-22 2003-10-28 Sun Microsystems, Inc. Integrated circuit having distributed control and status registers and associated signal routing means
US6748564B1 (en) * 2000-10-24 2004-06-08 Nptest, Llc Scan stream sequencing for testing integrated circuits
US6691270B2 (en) 2000-12-22 2004-02-10 Arm Limited Integrated circuit and method of operation of such a circuit employing serial test scan chains
US6957371B2 (en) 2001-12-04 2005-10-18 Intellitech Corporation Method and apparatus for embedded built-in self-test (BIST) of electronic circuits and systems
US20030163773A1 (en) 2002-02-26 2003-08-28 O'brien James J. Multi-core controller
US7073110B1 (en) 2002-04-26 2006-07-04 Xilinx, Inc. Method and system for programmable boundary-scan instruction register
US7039841B2 (en) 2002-05-08 2006-05-02 Credence Systems Corporation Tester system having multiple instruction memories
US7234092B2 (en) * 2002-06-11 2007-06-19 On-Chip Technologies, Inc. Variable clocked scan test circuitry and method
JP4182202B2 (ja) 2002-08-02 2008-11-19 富士通マイクロエレクトロニクス株式会社 シミュレーション用カバレッジ算出装置及びシミュレーション用カバレッジ算出方法
US20040078179A1 (en) 2002-10-17 2004-04-22 Renesas Technology Corp. Logic verification system
US7539915B1 (en) 2003-01-07 2009-05-26 Marvell Israel (Misl) Ltd. Integrated circuit testing using segmented scan chains
JP2004280588A (ja) 2003-03-17 2004-10-07 Cats Kk システムｌｓｉ設計支援装置およびシステムｌｓｉ設計支援プログラム
US7406699B2 (en) 2003-04-02 2008-07-29 Microsoft Corporation Enhanced runtime hosting
US7305586B2 (en) 2003-04-25 2007-12-04 International Business Machines Corporation Accessing and manipulating microprocessor state
US7080789B2 (en) 2003-05-09 2006-07-25 Stmicroelectronics, Inc. Smart card including a JTAG test controller and related methods
US7149943B2 (en) 2004-01-12 2006-12-12 Lucent Technologies Inc. System for flexible embedded Boundary Scan testing
US7139950B2 (en) 2004-01-28 2006-11-21 International Business Machines Corporation Segmented scan chains with dynamic reconfigurations
KR100880832B1 (ko) 2004-02-10 2009-01-30 삼성전자주식회사 코-디버깅 기능을 지원하는 반도체 집적회로 및 반도체집적회로 테스트 시스템
US7334060B2 (en) 2004-03-19 2008-02-19 International Business Machines Corporation System and method for increasing the speed of serially inputting data into a JTAG-compliant device
US7143324B2 (en) * 2004-11-04 2006-11-28 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for automatic masking of compressed scan chains with unbalanced lengths
JP2006146757A (ja) 2004-11-24 2006-06-08 Toshiba Corp デバッグ用レジスタおよびデータ転送方法
US8144824B2 (en) * 2005-03-10 2012-03-27 Qualcomm Incorporated Trend influenced time tracking
US7206983B2 (en) 2005-03-31 2007-04-17 Lsi Logic Corporation Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits
US7383478B1 (en) 2005-07-20 2008-06-03 Xilinx, Inc. Wireless dynamic boundary-scan topologies for field
JP2007147352A (ja) 2005-11-25 2007-06-14 Sony Corp 無線インターフェースモジュール及び電子機器
US8015462B2 (en) 2007-05-11 2011-09-06 Renesas Electronics Corporation Test circuit
US7886263B1 (en) * 2007-12-10 2011-02-08 Cadence Design Systems, Inc. Testing to prescribe state capture by, and state retrieval from scan registers
US8024693B2 (en) * 2008-11-04 2011-09-20 Synopsys, Inc. Congestion optimization during synthesis
US8621301B2 (en) * 2009-03-04 2013-12-31 Alcatel Lucent Method and apparatus for virtual in-circuit emulation
US8719649B2 (en) * 2009-03-04 2014-05-06 Alcatel Lucent Method and apparatus for deferred scheduling for JTAG systems

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100229036A1 (en) * 2009-03-04 2010-09-09 Suresh Goyal Method and apparatus for system testing using multiple instruction types

Also Published As

Publication number Publication date
US8719649B2 (en) 2014-05-06
CN104185795A (zh) 2014-12-03
US20120117436A1 (en) 2012-05-10
JP2015507743A (ja) 2015-03-12
KR20140136424A (ko) 2014-11-28
WO2013101336A1 (en) 2013-07-04
EP2798360A1 (en) 2014-11-05

Similar Documents

Publication Publication Date Title
KR101545109B1 (ko) Jtag 시스템들에 대한 연기 스케줄링을 위한 방법 및 장치
KR101364397B1 (ko) 가상 인서킷 에뮬레이션을 위한 방법 및 장치
KR101329465B1 (ko) 여러 프로세서들을 사용하는 시스템 테스트 방법 및 장치
US8775884B2 (en) Method and apparatus for position-based scheduling for JTAG systems

Legal Events

Date Code Title Description
A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20180811

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20180811