JP2015507743A - Ｊｔａｇシステムの遅延スケジューリングの方法および装置 - Google Patents

Ｊｔａｇシステムの遅延スケジューリングの方法および装置 Download PDF

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JP2015507743A
JP2015507743A JP2014550289A JP2014550289A JP2015507743A JP 2015507743 A JP2015507743 A JP 2015507743A JP 2014550289 A JP2014550289 A JP 2014550289A JP 2014550289 A JP2014550289 A JP 2014550289A JP 2015507743 A JP2015507743 A JP 2015507743A
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test
tisa
processor
vector
scheduler
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JP2015507743A5 (enExample
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ポートラン，ミシェル
ファン，トリューレン，ブラッドフォード
ゴヤル，スレシュ
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アルカテル−ルーセント
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318314—Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP2014550289A 2011-12-28 2012-10-25 Ｊｔａｇシステムの遅延スケジューリングの方法および装置 Pending JP2015507743A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/338,581 US8719649B2 (en) 2009-03-04 2011-12-28 Method and apparatus for deferred scheduling for JTAG systems
US13/338,581 2011-12-28
PCT/US2012/061824 WO2013101336A1 (en) 2011-12-28 2012-10-25 Method and apparatus for deferred scheduling for jtag systems

Publications (2)

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JP2015507743A true JP2015507743A (ja) 2015-03-12
JP2015507743A5 JP2015507743A5 (enExample) 2016-02-25

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JP2014550289A Pending JP2015507743A (ja) 2011-12-28 2012-10-25 Ｊｔａｇシステムの遅延スケジューリングの方法および装置

Country Status (6)

Country Link
US (1) US8719649B2 (enExample)
EP (1) EP2798360A1 (enExample)
JP (1) JP2015507743A (enExample)
KR (1) KR101545109B1 (enExample)
CN (1) CN104185795A (enExample)
WO (1) WO2013101336A1 (enExample)

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KR20200139083A (ko) * 2019-06-03 2020-12-11 주식회사 아도반테스토 메모리 기반 통신 프로토콜을 사용하여 시뮬레이션된 장치를 테스트하기 위한 시스템 및 방법

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US10521344B1 (en) * 2017-03-10 2019-12-31 Pure Storage, Inc. Servicing input/output (‘I/O’) operations directed to a dataset that is synchronized across a plurality of storage systems
US10162005B1 (en) * 2017-08-09 2018-12-25 Micron Technology, Inc. Scan chain operations
US10436840B2 (en) * 2017-10-26 2019-10-08 Nvidia Corp. Broadcast scan network
CN108896903A (zh) * 2018-06-13 2018-11-27 天津大学 基于逻辑加密的逐次验证型安全扫描链装置和方法
CN109697058B (zh) * 2018-12-11 2022-05-17 中国航空工业集团公司西安航空计算技术研究所 一种适用于嵌入式系统的网络建模方法、装置及存储介质
CN113312735B (zh) * 2021-05-19 2022-06-03 太原理工大学 一种城市供水管网dma分区方法
KR102373560B1 (ko) * 2021-08-18 2022-03-14 (주)이노티오 Ic 칩 스캔 테스트를 위한 테스트 데이터의 사용 가능한 쉬프트 주파수를 찾기 위한 검색용 데이터를 생성하는 방법 및 그 장치
KR102583916B1 (ko) * 2021-10-26 2023-09-26 연세대학교 산학협력단 저전력 테스트를 위한 스캔 상관관계 기반 스캔 클러스터 리오더링 방법 및 장치
CN114036885B (zh) * 2021-11-08 2025-09-30 上海兆芯集成电路股份有限公司 内建自测试的方法及互连接口
CN114860571B (zh) * 2022-03-30 2025-01-21 阿里云计算有限公司 数据处理方法、工具、存储介质以及计算机终端
US12291219B2 (en) * 2022-10-24 2025-05-06 Nvidia Corporation Asynchronous in-system testing for autonomous systems and applications

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Publication number Priority date Publication date Assignee Title
KR20200139083A (ko) * 2019-06-03 2020-12-11 주식회사 아도반테스토 메모리 기반 통신 프로토콜을 사용하여 시뮬레이션된 장치를 테스트하기 위한 시스템 및 방법
KR102243791B1 (ko) 2019-06-03 2021-04-22 주식회사 아도반테스토 메모리 기반 통신 프로토콜을 사용하여 시뮬레이션된 장치를 테스트하기 위한 시스템 및 방법

Also Published As

Publication number Publication date
US8719649B2 (en) 2014-05-06
CN104185795A (zh) 2014-12-03
KR101545109B1 (ko) 2015-08-17
KR20140136424A (ko) 2014-11-28
US20120117436A1 (en) 2012-05-10
EP2798360A1 (en) 2014-11-05
WO2013101336A1 (en) 2013-07-04

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