JP2015502035A - クワッド・フラット・ノーリード(qfn)パッケージ構造及びその製造方法 - Google Patents
クワッド・フラット・ノーリード(qfn)パッケージ構造及びその製造方法 Download PDFInfo
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Abstract
Description
本出願は、半導体パッケージング技術に出願された中国特許出願201110374237.2号の優先権を主張し、参照することによりその全体が本明細書に組み込まれる。
1) 高価な高温フィルムが金属基板の裏面に貼付されなければならないので、製造コストは直接的に増加する;
2) 包装工程のダイ取付プロセスにおいて、高温耐熱性フィルムが金属基板の裏面に貼付されなければならないこともあるため、ダイ取付工程に使用できるのはエポキシのみに限り、共晶プロセスまたは軟質はんだ技術などの特定の技術を使用することができずため、大幅に利用可能な製品の選択は制限される;
3) 包装工程のワイヤボンディングプロセスにおいて、高温耐熱性フィルムが金属基板の裏面に貼付されなければならないこともあるため、高温耐性フィルムが軟質材料の一種であり、ワイヤボンディングパラメータは、不安定になることがあり、ワイヤボンディングの品質、製品の信頼性と安定性に深刻な影響を与える;及び
4) 成形プロセスにおいて、高温耐熱性フィルムが金属基板の裏面に貼付されなければならないこともあるため、成形時の成形圧力は、リードフレーム及び高温耐熱性フィルムとの間に特定のモールドブリーディングを引き起こす恐れがあり、図50に示すように、導電性の金属リードを絶縁リードに変更することがある(図の左側にある特定の金属リードは、材料ブリーディングで絶縁されている)。
1) リードフレームのエッチング工程が二回実施されたため、製造コストが増える可能性がある;
2) リードフレームの組成が金属材料および化合物であるため、高温および低温環境下で動作する場合、リードフレームは、異なる材料の異なる膨張および収縮応力によりワーピングされることがある;
3) リードフレームの反りは、ダイ取付プロセスの精度に影響を与える恐れがあり、またダイ取付工程にワーピングリードフレームのスムーズ転送に与える影響のため、製造歩留まりに影響を与える可能性がある;
4) リードフレームの反りは、ワイヤボンディングの位置合わせ精度にも影響を与える恐れがあり、またワイヤボンディング工程にワーピングリードフレームのスムーズ転送に与える影響のため、製造歩留まりに影響を与える可能性がある;及び
5) インナーリードがエッチング技術を用いてリードフレームの上面に形成されるため、インナーリードの幅は
よりも大きく、二つの隣接するインナーリード間の距離も
より大きくなるようにする必要がある。これにより、インナーリードの高密度化を達成することは困難であり得る。
Claims (23)
- クワッド・フラット・ノーリード(QFN)パッケージ構造は以下を含む:
金属基材;
金属基板上に基づいて形成された第一アウターダイパッド;
アウターダイパッドの上面に結合された第一のダイ;
複数の金属基板上に基づいて形成されたI/Oパッド;
複数のインナーリードのリードピッチが大幅に低減されるように、複数のI/Oパッドに対応し、ダイの近傍に延び、そして多層の電気めっき処理によって金属基板上に形成される複数のインナーリードを含む第一金属層
ダイと複数のインナーリードを接続する金属細線;及び
ダイパッドと複数のI/Oパッドの裏面に取り付ける第二金属層、
そこにダイ、複数のインナーリードおよび金属ワイヤは、成形化合物で封止されている。 - 請求項1に記載のQFNパッケージ構造であって、ここで:
ダイが接着材を介してアウターダイパッドの上面に取り付けられる。 - 請求項1に記載のQFNパッケージ構造であって、さらに以下を含む:
多層の電気めっき処理により、アウターダイパッドの上面上に形成された一つまたは複数のインナーダイパッド、そこにはダイが接着材料によってインナーダイパッドに取り付けられる。 - 請求項1に記載のQFNパッケージ構造であって、ここで:
複数のI/Oパッドは、シングルリング構成に配置される;及び
複数のインナーリードも、対応シングルリング構成に配置される。 - 請求項1に記載のQFNパッケージ構造であって、ここで:
複数のI/Oパッドは、マルチリング構成に配置される;及び
複数のインナーリードも、対応マルチリング構成に配置される。 - 請求項1に記載のQFNパッケージ構造であって、さらに以下を含む:
接着材料によって複数のインナーリードのリード線との間に結合された一つまたは複数の受動素子。 - 請求項1に記載のQFNパッケージ構造であって、さらに以下を含む:
アウターダイパッドとI/Oパッドとの間の金属基板に基づいて形成されるアウター静電放電リング;及び
アウター静電放電リングの上面に形成されたインナー静電放電リング、ダイに接続される。 - 請求項1に記載のQFNパッケージ構造であって、さらに以下を含む:
アウターダイパッドとI/Oパッドの周辺領域、アウターダイパッドとI/Oパッドの間の領域、及び金属基板の裏面におけるI/Oパッドのパッド間の領域に充填されたシール材。 - 請求項1に記載のQFNパッケージ構造であって、さらに以下を含む:
第一のアウターダイパッドに対してサイドバイサイド構成で形成された第二のアウターダイパッド;及び
第二アウターダイパッドの上面に結合された第二のダイ、そこには第一のダイおよび第二のダイが金属ワイヤで接続される。 - クワッド・フラット・ノーリード(QFN)パッケージ構造の製造方法、以下を含む:
金属基板を設ける;
金属基板の上面に第一フォトレジスト膜を形成する工程;
フォトリソグラフィを用いて第一フォトレジスト膜のめっきグパターンを形成する工程;
複数のインナーリードのリードピッチが大幅に低減されるように、第一のフォトレジスト膜にめっきパターンをマスクとして用いる多層の電気めっき処理により複数のインナーリードを含む第一金属層を形成する工程;
金属基板の表面上の所定の領域に一つのダイを取り付ける工程;
ワイヤボンディングプロセスにより金属ワイヤを用いてダイと複数のインナーリードを接続する工程;
ダイ、複数のインナーリードおよび金属ワイヤを成形化合物で封止する工程;
複数のインナーリードに該当する複数のI/Oパッド、ダイを搭載した所定の領域に該当するアウターダイパッドを形成するために金属基板の裏面から金属基板をエッチングする工程;及び
アウターダイパッドと複数のI/Oパッドの裏面に取り付ける第二金属層を成形する工程。 - 請求項11に記載の方法であって、更に第一のフォトレジスト膜を形成することは以下を含む:
多層の電気めっき処理中に金属基板を保護するために金属基板の裏面上に第二のフォトレジスト膜を形成する工程。 - 請求項11に記載の方法であって、更に第一金属層を形成することは以下を含む:
第一のフォトレジスト膜及び第二のフォトレジスト膜を除去する工程。 - 請求項11に記載の方法であって、更に金属基板をエッチングすることは以下を含む:
金属基板の裏面に第三フォトレジスト膜を形成する工程;
フォトリソグラフィを用いて第三フォトレジスト膜のエッチンググパターンを形成する工程;
金属基板の裏面上に第三フォトレジスト膜のエッチングパターンを用いて金属基板をエッチングする工程。 - 請求項14に記載の方法であって、更に第三フォトレジスト膜のエッチンググパターンを形成することは以下を含む:
エッチングプロセスから金属基板を保護するため封止材料を含めて金属基板の上に第四フォトレジスト膜を形成する工程。 - 請求項15に記載の方法であって、更に金属基板をエッチングすることは以下を含む:
金属基板をエッチングした後に第三フォトレジスト膜と第四フォトレジスト膜を除去する工程。 - 請求項11に記載の方法であって、さらに以下を含む:
アウターダイパッドとI/Oパッドの周辺領域、アウターダイパッドとI/Oパッドの間の領域、及び金属基板の裏面におけるI/Oパッドのパッド間の領域に充填されたシール材。 - 請求項11に記載の方法であって、更にダイを取り付けることは以下を含む:
アウターダイパッドに該当して接着材料を用いて金属基板の表面上の所定の領域にダイを取り付ける工程。 - 請求項11に記載の方法であって、さらに以下を含む:
多層の電気めっき処理により、アウターダイパッドの上面上に一つまたは複数のインナーダイパッドを形成する工程、そこにはダイが接着材料によってインナーダイパッドに取り付けられる。 - 請求項11に記載の方法であって、ここで:
複数のI/Oパッドは、シングルリング構成に配置される;及び
複数のインナーリードも、対応シングルリング構成に配置される。 - 請求項11に記載の方法であって、ここで:
複数のI/Oパッドは、マルチリング構成に配置される;及び
複数のインナーリードも、対応マルチリング構成に配置される。 - 請求項11に記載の方法であって、さらに以下を含む:
接着材料によって複数のインナーリードの間に結合された一つまたは複数の受動素子。 - 請求項10に記載の方法であって、さらに以下を含む:
アウターダイパッドとI/Oパッドの複数との間の金属基板に基づいて、アウター静電放電リングを形成する工程;
アウター静電放電リングの上面にインナー静電放電リングを形成する工程;及び
インナー静電放電リングとダイを接続する工程。
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CN2011103742372A CN102403282B (zh) | 2011-11-22 | 2011-11-22 | 有基岛四面无引脚封装结构及其制造方法 |
CN201110374237.2 | 2011-11-22 | ||
PCT/CN2012/000018 WO2013075383A1 (en) | 2011-11-22 | 2012-01-06 | Quad flat no-lead (qfn) packaging structures and method for manufacturing the same |
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CN104269393A (zh) * | 2014-09-15 | 2015-01-07 | 江苏长电科技股份有限公司 | 一体金属框架静电释放圈用于指纹传感器结构及制造方法 |
US9997439B2 (en) | 2015-04-30 | 2018-06-12 | Qualcomm Incorporated | Method for fabricating an advanced routable quad flat no-lead package |
US11729915B1 (en) * | 2022-03-22 | 2023-08-15 | Tactotek Oy | Method for manufacturing a number of electrical nodes, electrical node module, electrical node, and multilayer structure |
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