JP2015170676A - Wiring board and manufacturing method thereof - Google Patents

Wiring board and manufacturing method thereof Download PDF

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JP2015170676A
JP2015170676A JP2014043558A JP2014043558A JP2015170676A JP 2015170676 A JP2015170676 A JP 2015170676A JP 2014043558 A JP2014043558 A JP 2014043558A JP 2014043558 A JP2014043558 A JP 2014043558A JP 2015170676 A JP2015170676 A JP 2015170676A
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base layer
wiring pattern
conductor
wiring
layer
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陽一 三浦
Yoichi Miura
陽一 三浦
関口 毅
Takeshi Sekiguchi
関口  毅
英範 吉岡
Hidenori Yoshioka
英範 吉岡
健史 下村
Takeshi Shimomura
健史 下村
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board including a base layer contributing to the improvement of production efficiency and cost reduction and formed with highly reliable vertical-direction conductors thereon and a manufacturing method thereof.SOLUTION: A wiring board includes: a base layer which is made from an inorganic material and is provided with a plurality of holes passing through from a first surface to a second surface; vertical-direction conductors which are made from a conductive composition and are disposed inside each hole of the base layer so as to have lower surfaces connected to the first surface and upper surfaces connected to the second surface; first and second wiring patterns which are provided on each of the first surface and the second surface of the base layer and the lower surfaces and the upper surfaces of the vertical-direction conductors to cover all boundaries between the second surface on the lower surfaces and the upper surfaces of the vertical-direction conductors and the first surface and not to cover partial regions of the lower surfaces and the upper surfaces; and first and second insulation layers located in a laminar form on each of the first surface side and the second surface side of the base layer so as to cover regions which are not covered with the first and second wiring patterns of the lower surfaces and the upper surfaces of the vertical-direction conductors and bury the first and second wiring patterns.

Description

本発明は、電子デバイスを実装するための配線板およびその製造方法に係り、特に、基層として無機材料層を有する配線板およびその製造方法に関する。   The present invention relates to a wiring board for mounting an electronic device and a manufacturing method thereof, and more particularly to a wiring board having an inorganic material layer as a base layer and a manufacturing method thereof.

近年、配線板として、基板素材がエポキシ樹脂などの有機材料である一般的なものに代わり、無機材料のものもその用途を広げている。例えば、半導体チップ部品を大型の配線基板(マザーボードなど)に実装する簡便化するため使われる、端子配置を粗ピッチに変換するインターポーザーもそのひとつである。   In recent years, the use of an inorganic material as a wiring board has been expanded in place of a general material in which a substrate material is an organic material such as an epoxy resin. One example is an interposer that converts terminal arrangements to a coarse pitch, which is used to simplify the mounting of semiconductor chip components on a large wiring board (such as a mother board).

インターポーザーは、その面上に電子デバイスである半導体チップが実装され、その形態でさらにこのインターポーザーより大きな配線基板を介して、またはこの形態のインターポーザーがそのまま大型の配線基板に実装される。インターポーザーは、半導体チップ自体と配線基板との面方向の熱膨張率の違いから生じるストレスを緩和する作用もあり、その点で板素材に無機材料を用いると有利である。   The interposer is mounted with a semiconductor chip as an electronic device on its surface, and in that form, the interposer is further mounted via a wiring board larger than the interposer, or this form of the interposer is directly mounted on a large wiring board. The interposer also has an action to relieve stress caused by the difference in thermal expansion coefficient between the semiconductor chip itself and the wiring substrate, and it is advantageous to use an inorganic material for the plate material.

一例であるインターポーザーとして、基板材料に半導体チップと同様のシリコンを使用したものが存在する。シリコンの場合、微細な配線の形成方法として半導体製造プロセスで培った技術を活用できるため有用性が大きい。また、別の例のインターポーザーとして、同じく無機材料であるガラスを基板材料とするものも存在する。ガラスに対しては半導体への加工技術をそのまま活用できないものの、素材としてシリコンとの比較で非常に安価でコスト的に有望である。   As an example of an interposer, there is a substrate material using silicon similar to a semiconductor chip. In the case of silicon, the technology cultivated in the semiconductor manufacturing process can be utilized as a method for forming fine wiring, so that it is very useful. Another example of an interposer is one that uses glass, which is also an inorganic material, as a substrate material. Although it is not possible to use the processing technology for semiconductors as it is for glass, it is very cheap and promising in terms of cost compared to silicon as a material.

無機材料の基板素材を用いる場合の留意点としては、有機材料の基板との素材としての違いに基づいて、その貫通導体をどのように構成するかが挙げられる。その主な観点は、一般的に信頼性およびコストになるが、前提として、無機材料としての利点を活かすようにファイン化に寄与する構成が好ましい。   A point to be noted when using a substrate material made of an inorganic material is how to configure the through conductor based on the difference between the material and the substrate made of an organic material. The main viewpoint is generally reliability and cost, but as a premise, a configuration that contributes to refinement so as to take advantage of the inorganic material is preferable.

特開2010−171377号公報JP 2010-171377 A

本発明は、電子デバイスを実装するための、少なくとも基層として無機材料層を有する配線板およびその製造方法において、生産効率向上に寄与してコスト削減に貢献しかつ信頼性も高い縦方向導電体が形成された基層を含む配線板およびその製造方法を提供することを目的とする。   The present invention relates to a wiring board having an inorganic material layer as at least a base layer for mounting an electronic device, and a method for manufacturing the wiring board, and a longitudinal conductor that contributes to improvement in production efficiency and contributes to cost reduction and high reliability. It aims at providing the wiring board containing the formed base layer, and its manufacturing method.

上記の課題を解決するため、本発明の一態様である配線板は、第1面と該第1面の反対の側の第2面とを有し、前記第1面から前記第2面に貫通する孔が複数設けられた無機材料製の基層と、前記基層の前記第1面に連なるような下面と前記基層の前記第2面に連なるような上面とを有するように前記基層の前記孔それぞれの内部を充填して配置された、導電性組成物でできた縦方向導電体と、前記縦方向導電体の前記下面の、前記基層の前記第1面との境界線上をすべて覆う一方、該下面の一部の領域上は覆わないように、前記基層の前記第1面上および前記縦方向導電体の前記下面上に設けられた第1の配線パターンと、前記縦方向導電体の前記下面のうちの前記第1の配線パターンに覆われない領域を覆いかつ前記第1の配線パターンを埋め込むように、前記基層の前記第1面の側に積層状に位置する第1の絶縁層と、前記縦方向導電体の前記上面の、前記基層の前記第2面との境界線上をすべて覆う一方、該上面の一部の領域上は覆わないように、前記基層の前記第2面上および前記縦方向導電体の前記上面上に設けられた第2の配線パターンと、前記縦方向導電体の前記上面のうちの前記第2の配線パターンに覆われない領域を覆いかつ前記第2の配線パターンを埋め込むように、前記基層の前記第2面の側に積層状に位置する第2の絶縁層とを具備する。   In order to solve the above problems, a wiring board according to an aspect of the present invention has a first surface and a second surface opposite to the first surface, and the first surface extends to the second surface. The hole of the base layer having a base layer made of an inorganic material provided with a plurality of through-holes, a lower surface continuous with the first surface of the base layer, and an upper surface continuous with the second surface of the base layer While covering the entire boundary line between the longitudinal conductor made of a conductive composition and filled in each interior, and the lower surface of the longitudinal conductor and the first surface of the base layer, A first wiring pattern provided on the first surface of the base layer and on the lower surface of the vertical conductor so as not to cover a partial region of the lower surface; Covering a region of the lower surface that is not covered with the first wiring pattern and the first wiring pattern Cover the entire boundary line between the first insulating layer positioned in a stacked manner on the first surface side of the base layer and the upper surface of the longitudinal conductor and the second surface of the base layer so as to be embedded. On the other hand, a second wiring pattern provided on the second surface of the base layer and the upper surface of the vertical conductor so as not to cover a part of the upper surface, and the vertical conductor A second insulating layer positioned on the second surface side of the base layer so as to cover a region of the upper surface of the base layer that is not covered with the second wiring pattern and to be embedded in the second wiring pattern. A layer.

すなわち、無機材料の基層に貫通形成された孔の内部に設ける縦方向導電体に、その素材として導電性組成物を用いる。導電性組成物には一般に樹脂が含まれている。導電性組成物を用いれば、例えばスクリーン印刷を用いて孔に対してペースト状に調製された導電性組成物の充填工程を効率よく行うことができ、大きなコスト削減を図ることができる。   That is, a conductive composition is used as a material for a longitudinal conductor provided in a hole formed through a base layer of an inorganic material. In general, the conductive composition contains a resin. If the conductive composition is used, for example, the filling process of the conductive composition prepared in a paste form with respect to the holes using screen printing can be performed efficiently, and a large cost reduction can be achieved.

そして、次に、無機材料である基層と導電性組成物である縦方向導電体との素材の違いに起因する、それらの熱変形による第1(および第2)の絶縁層へのダメージを大きく軽減する構成を有している。具体的には、縦方向導電体の下面の、基層の第1面との境界線上をすべて覆う一方、下面の一部の領域上は覆わないように、基層の第1面上および縦方向導電体の下面上に第1の配線パターンを設けている。このような第1の配線パターンにより、縦方向導電体の熱変形が第1の絶縁層へのせん断力として直に及ぶのを防いでいる。第2の配線パターンと第2の絶縁層との関係も同様である。これにより、第1(および第2)の絶縁層に亀裂が生じるなどの悪影響を防止できる。   Then, the damage to the first (and second) insulating layer due to the thermal deformation due to the difference in material between the base layer that is an inorganic material and the longitudinal conductor that is a conductive composition is large. It has a configuration to reduce. Specifically, on the first surface of the base layer and in the longitudinal direction so that the lower surface of the vertical conductor covers the entire boundary line with the first surface of the base layer, but does not cover a part of the lower surface. A first wiring pattern is provided on the lower surface of the body. Such a first wiring pattern prevents thermal deformation of the longitudinal conductor from being directly applied as a shearing force to the first insulating layer. The same applies to the relationship between the second wiring pattern and the second insulating layer. Thereby, it is possible to prevent adverse effects such as a crack in the first (and second) insulating layer.

さらに、第1の絶縁層は、縦方向導電体の下面のうちの第1の配線パターンに覆われない領域を覆うように設けられているので、縦方向導電体の周りが基層を始めほぼすべて無機材料であっても、樹脂が含まれた縦方向導電体を発生源とする気体や水分の脱出経路として第1の絶縁層を機能させることができ、信頼性維持を図れる。第2の絶縁層についても同様である。以上より、生産効率向上に寄与してコスト削減に貢献しかつ信頼性も高い縦方向導電体が形成された基層を含む配線板が得られることになる。   Furthermore, since the first insulating layer is provided so as to cover a region of the lower surface of the vertical conductor that is not covered by the first wiring pattern, almost all of the periphery of the vertical conductor, including the base layer, is provided. Even if it is an inorganic material, a 1st insulating layer can be functioned as the escape route of the gas and water | moisture content which used the longitudinal direction conductor containing resin as a generation source, and can maintain reliability. The same applies to the second insulating layer. From the above, it is possible to obtain a wiring board including a base layer on which a longitudinal conductor is formed, which contributes to improvement in production efficiency, contributes to cost reduction, and has high reliability.

また、本発明の別の態様である配線板の製造方法は、第1面と該第1面の反対の側の第2面とを有する無機材料製の基層に貫通孔を形成する工程と、前記基層の前記貫通孔内に導電性組成物を充填して、前記基層の前記第1面に連なるような下面と前記基層の前記第2面に連なるような上面とを有する縦方向導電体を形成する工程と、前記縦方向導電体の前記下面の、前記基層の前記第1面との境界線上をすべて覆う一方、該下面の一部の領域上は覆わないように、前記基層の前記第1面上および前記縦方向導電体の前記下面上に第1の配線パターンを設ける工程と、前記縦方向導電体の前記上面の、前記基層の前記第2面との境界線上をすべて覆う一方、該上面の一部の領域上は覆わないように、前記基層の前記第2面上および前記縦方向導電体の前記上面上に第2の配線パターンを設ける工程と、前記縦方向導電体の前記下面のうちの前記第1の配線パターンに覆われない領域を覆いかつ前記第1の配線パターンを埋め込むように、前記基層の前記第1面の側に積層状に第1の絶縁層を形成する工程と、前記縦方向導電体の前記上面のうちの前記第2の配線パターンに覆われない領域を覆いかつ前記第2の配線パターンを埋め込むように、前記基層の前記第2面の側に積層状に第2の絶縁層を形成する工程とを具備する。   Moreover, the method for manufacturing a wiring board according to another aspect of the present invention includes a step of forming a through hole in a base layer made of an inorganic material having a first surface and a second surface opposite to the first surface; A longitudinal conductor having a bottom surface that is continuous with the first surface of the base layer and a top surface that is continuous with the second surface of the base layer by filling the through hole of the base layer with a conductive composition. And covering the entire bottom line of the lower surface of the longitudinal conductor with the first surface of the base layer, while not covering a partial region of the lower surface. A step of providing a first wiring pattern on one surface and on the lower surface of the longitudinal conductor, and covering all of the boundary line between the upper surface of the longitudinal conductor and the second surface of the base layer, On the second surface of the base layer and the longitudinal direction so as not to cover a partial region of the upper surface A step of providing a second wiring pattern on the upper surface of the electric body, and a region of the lower surface of the vertical conductor that is not covered by the first wiring pattern and embedded in the first wiring pattern As described above, a step of forming a first insulating layer in a stacked manner on the first surface side of the base layer, and a region of the upper surface of the vertical conductor that is not covered with the second wiring pattern Forming a second insulating layer in a laminated form on the second surface side of the base layer so as to cover and embed the second wiring pattern.

この製造方法は、上記の配線板を製造するためのひとつの態様である。   This manufacturing method is one aspect for manufacturing the wiring board.

本発明によれば、電子デバイスを実装するための、少なくとも基層として無機材料層を有する配線板およびその製造方法において、生産効率向上に寄与してコスト削減に貢献しかつ信頼性も高い縦方向導電体が形成された基層を含む配線板およびその製造方法を提供することができる。   According to the present invention, in a wiring board having an inorganic material layer as at least a base layer for mounting an electronic device and a method for manufacturing the same, it contributes to improvement in production efficiency, contributes to cost reduction, and has high reliability. A wiring board including a base layer on which a body is formed and a method for manufacturing the wiring board can be provided.

一実施形態である配線板の例としてインターポーザーの場合の構成を模式的に示す断面図および要部の平面図。Sectional drawing which shows the structure in the case of an interposer as an example of the wiring board which is one Embodiment, and the top view of the principal part. 図1に示したインターポーザーにおいて縦方向導電体31が変形することによる影響を示す説明図。Explanatory drawing which shows the influence by the longitudinal direction conductor 31 deform | transforming in the interposer shown in FIG. 図1に示したインターポーザーを製造する過程を模式的な断面で示す工程図。Process drawing which shows the process in which the interposer shown in FIG. 図3の続図であって、図1に示したインターポーザーを製造する過程を模式的な断面で示す工程図。FIG. 4 is a continuation diagram of FIG. 3, and is a process diagram schematically showing a process of manufacturing the interposer shown in FIG. 1. 別の実施形態である配線板の例としてインターポーザーの場合の構成を模式的に示す断面図および要部の平面図。Sectional drawing which shows the structure in the case of an interposer as an example of the wiring board which is another embodiment, and the top view of the principal part.

本発明の実施態様として、前記基層が、ガラス製である、とすることができる。無機材料としてガラスは非常に安価であり、同じ無機材料であるシリコンと比較してその点で有利である。   As an embodiment of the present invention, the base layer may be made of glass. As an inorganic material, glass is very inexpensive and is advantageous in that respect compared to silicon, which is the same inorganic material.

また、実施態様として、前記基層が、前記孔の前記第1面および前記第2面における平面形状がそれぞれ円形であるように前記孔が設けられた基層であり、前記第1の配線パターンが、外側輪郭と内側輪郭とを有する、前記基層の前記孔の前記第1面における前記円形と同心のリング状の形状を有し、前記第2の配線パターンが、外側輪郭と内側輪郭とを有する、前記基層の前記孔の前記第2面における前記円形と同心のリング状の形状を有する、とすることができる。   Further, as an embodiment, the base layer is a base layer provided with the holes so that the planar shapes of the first surface and the second surface of the holes are circular, respectively, and the first wiring pattern is Having a ring-like shape concentric with the circle in the first surface of the hole of the base layer having an outer contour and an inner contour, and the second wiring pattern has an outer contour and an inner contour; The base layer may have a ring shape concentric with the circular shape on the second surface of the hole.

これは、基層に設ける孔の平面形状の一例であり、かつ、その場合の第1、第2の配線パターンの形状の一例である。孔の平面形状として基層の第1面、第2面においてともに円形とすれば、もっとも孔加工として容易と考えられる。また、第1、第2の配線パターンを孔の平面形状に合わせてリング状の形状とすれば、円形状は微細化に適したパターンと考えられるためファイン化に都合がよい。   This is an example of the planar shape of the hole provided in the base layer, and is an example of the shape of the first and second wiring patterns in that case. If both the first surface and the second surface of the base layer are circular as the planar shape of the hole, it is considered that the hole processing is most easy. Further, if the first and second wiring patterns are formed in a ring shape according to the planar shape of the hole, the circular shape is considered to be a pattern suitable for miniaturization, which is convenient for refinement.

また、実施態様として、前記第1の配線パターンの前記内側輪郭から離間してさらに内側に、前記縦方向導電体の前記下面に接触するように設けられた第3の配線パターンをさらに具備し、前記第1の絶縁層が、前記第3の配線パターンをも埋め込むように設けられており、前記第1の絶縁層を貫通するように、前記縦方向導電体に接触する側とは反対の側の前記第3の配線パターン上に設けられた第1絶縁層貫通導体をさらに具備する、とすることができる。   Further, as an embodiment, further comprising a third wiring pattern provided so as to be in contact with the lower surface of the vertical conductor, further on the inner side away from the inner contour of the first wiring pattern, The first insulating layer is provided so as to embed the third wiring pattern, and is opposite to the side in contact with the longitudinal conductor so as to penetrate the first insulating layer. And a first insulating layer through conductor provided on the third wiring pattern.

この態様においては、第3の配線パターンは、電気的に第1の配線パターンを補助する導体となるが、かかる第3の配線パターンを設ければ、これを利用してその直上に第1絶縁層貫通導体を設けることができる。したがって、配線板として、第1絶縁層貫通導体の配置の自由度を増加させることができる。   In this aspect, the third wiring pattern serves as a conductor that electrically assists the first wiring pattern. If such a third wiring pattern is provided, the first insulation is formed immediately above the third wiring pattern. A layer through conductor can be provided. Therefore, the degree of freedom of arrangement of the first insulating layer through conductor can be increased as the wiring board.

また、実施態様として、前記第2の配線パターンの前記内側輪郭から離間してさらに内側に、前記縦方向導電体の前記上面に接触するように設けられた第3の配線パターンをさらに具備し、前記第2の絶縁層が、前記第3の配線パターンをも埋め込むように設けられており、前記第2の絶縁層を貫通するように、前記縦方向導電体に接触する側とは反対の側の前記第3の配線パターン上に設けられた第2絶縁層貫通導体をさらに具備する、とすることができる。   Further, as an embodiment, further comprising a third wiring pattern provided so as to be in contact with the upper surface of the vertical conductor, further on the inner side away from the inner contour of the second wiring pattern, The second insulating layer is provided so as to embed the third wiring pattern, and is opposite to the side in contact with the longitudinal conductor so as to penetrate the second insulating layer. And a second insulating layer through conductor provided on the third wiring pattern.

この態様は、上記の場合と捉え方は同じである。この場合は、基層の、第2の配線パターンおよび第2の絶縁層の設けられた側での利点になる。   This aspect is the same as the above case. In this case, it becomes an advantage on the side of the base layer on which the second wiring pattern and the second insulating layer are provided.

以上を踏まえ、以下では本発明の実施形態を図面を参照しながら説明する。図1は、一実施形態である配線板の例としてインターポーザーの場合の構成を模式的に示す断面図(図1(a))および要部の平面図(図1(b))である。   Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view (FIG. 1 (a)) schematically showing a configuration in the case of an interposer as an example of a wiring board according to an embodiment and a plan view (FIG. 1 (b)) of a main part.

同図に示すように、このインターポーザーは、ガラス基層11、樹脂層(配線層間絶縁層)12、13、配線パターン21a、21c、22a、22c、ビアホール内めっきビア21b、22b、ニッケル金めっき層21d、22d、縦方向導電体31、配線カバー膜(はんだレジスト膜)41、42、はんだボール51を有する。図1(a)に示す断面は、図1(b)中に示すA−Aa位置における断面に相当する。図1(b)の図示は、同図中に示される要素のみを描いた要部の平面図である。   As shown in the figure, this interposer includes a glass base layer 11, resin layers (interlayer insulating layers) 12, 13, wiring patterns 21a, 21c, 22a, 22c, via-hole plated vias 21b, 22b, nickel gold plated layer 21d, 22d, longitudinal conductors 31, wiring cover films (solder resist films) 41, 42, and solder balls 51. The cross section shown in FIG. 1A corresponds to the cross section at the position A-Aa shown in FIG. The illustration of FIG. 1B is a plan view of the main part depicting only the elements shown in the figure.

概略として、このインターポーザーは、図1(a)図示上面にあるニッケル金めっき層22dの部分を接続ランドに利用して半導体チップ(不図示)が例えばフリップチップボンディングにより実装され、一方、同図示下面にあるはんだボール51を使用して他のより大型の樹脂製配線基板(不図示)に全体が表面実装され得る構成である。ニッケル金めっき層22dを有するランドの配置ピッチは半導体チップの端子(不図示)のそれに合わせて狭ピッチであり、はんだボール51は、これより広いピッチで配置されている。   As an outline, in this interposer, a semiconductor chip (not shown) is mounted by, for example, flip-chip bonding using a portion of the nickel gold plating layer 22d on the upper surface shown in FIG. The entire structure can be surface-mounted on another larger resin wiring board (not shown) using the solder balls 51 on the lower surface. The arrangement pitch of the lands having the nickel gold plating layer 22d is a narrow pitch corresponding to that of a terminal (not shown) of the semiconductor chip, and the solder balls 51 are arranged at a wider pitch.

インターポーザーにより、狭端子ピッチの半導体チップ部品の、大型の配線基板(マザーボードなど)への実装が簡便化される。なお、ニッケル金めっき層22dは、これを形成せず、代わりに配線パターン22c上に銅の金属バンプを形成する形態も考えられる。この場合、この金属バンプは、半導体 チップ(不図示)の実装のため、その半導体チップの面上に設けられた別の金属バンプ(端子)に接続される。   The interposer simplifies the mounting of semiconductor chip components with a narrow terminal pitch on a large wiring board (such as a mother board). In addition, the nickel gold plating layer 22d is not formed, but a form in which copper metal bumps are formed on the wiring pattern 22c instead is also conceivable. In this case, this metal bump is connected to another metal bump (terminal) provided on the surface of the semiconductor chip for mounting a semiconductor chip (not shown).

ニッケル金めっき層22dを有する接続ランドは、電気的に、配線パターン22c、ビアホール内めっきビア22b、配線パターン22a、縦方向導電体31、配線パターン21a、ビアホール内めっきビア21b、配線パターン21c、ニッケル金めっき層21dを経て、はんだボール51に導通している。   The connection land having the nickel gold plating layer 22d is electrically connected to the wiring pattern 22c, the via hole plating via 22b, the wiring pattern 22a, the vertical conductor 31, the wiring pattern 21a, the via hole plating via 21b, the wiring pattern 21c, nickel. It is electrically connected to the solder ball 51 through the gold plating layer 21d.

以上の縦方向および横方向の導体部分が存在する一方、ガラス基層11、樹脂層12、13、配線カバー膜41、42は絶縁体であり、これらの積層構成により、上記の導体をそれぞれ図示するように所望に配置させる(あるいは保護する)ことができる。絶縁体のうち、ガラス基層11は、その名称のとおりガラスを使用したコア層に相当する層であり、樹脂素材よりも熱膨張率が相当に小さいことにより、このインターポーザーに取り付ける半導体チップ(不図示)との熱膨張率の違いで生じるストレスを大きく軽減させることができる。   While the above-described vertical and horizontal conductor portions exist, the glass base layer 11, the resin layers 12 and 13, and the wiring cover films 41 and 42 are insulators. Can be arranged (or protected) as desired. Among the insulators, the glass base layer 11 is a layer corresponding to a core layer using glass as the name suggests, and since the coefficient of thermal expansion is considerably smaller than that of a resin material, a semiconductor chip (non-conductive) attached to the interposer is used. It is possible to greatly reduce the stress caused by the difference in coefficient of thermal expansion from that shown in the figure.

ガラス基層11を貫通して設けられた縦方向導電体31は、ガラス基層11に貫通形成されたビア孔11a内に配置させた、導電性組成物による導体である。縦方向導電体31は、基層11の両面に連なるような下面、上面を有するようにビア孔11aそれぞれの内部を充填して設けられている。導電性組成物を用いれば、例えばスクリーン印刷を用いてビア孔11aに対してペースト状に調製された導電性組成物の充填工程を効率よく行うことができ、大きなコスト削減を図ることができる。   The vertical conductor 31 provided through the glass base layer 11 is a conductor made of a conductive composition disposed in a via hole 11 a formed through the glass base layer 11. The longitudinal conductor 31 is provided by filling the inside of each via hole 11 a so as to have a lower surface and an upper surface that are continuous with both surfaces of the base layer 11. If a conductive composition is used, the filling process of the conductive composition prepared in a paste form with respect to the via hole 11a using, for example, screen printing can be efficiently performed, and a large cost reduction can be achieved.

また、縦方向導電体31と配線パターン21a、22aとは、それらの関係として、ガラス基層11と縦方向導電体31との素材の違いに起因する、それらの熱変形による樹脂層12、13へのダメージを大きく軽減する構成を有している。具体的には、配線パターン21a(22a)は、縦方向導電体31の下面(上面)の、基層11面との境界線上をすべて覆う一方、その下面(上面)の一部の領域上は覆わないように、基層11の面上および縦方向導電体31の下面(上面)上に設けられている(図1(b)を参照)。   In addition, the vertical conductor 31 and the wiring patterns 21a and 22a are related to the resin layers 12 and 13 due to their thermal deformation caused by the difference in material between the glass base layer 11 and the vertical conductor 31. It has a configuration that greatly reduces the damage. Specifically, the wiring pattern 21a (22a) covers all of the lower surface (upper surface) of the vertical conductor 31 on the boundary line with the surface of the base layer 11, while covering a part of the lower surface (upper surface). It is provided on the surface of the base layer 11 and on the lower surface (upper surface) of the longitudinal conductor 31 (see FIG. 1B).

このような構成により、縦方向導電体31の熱変形が樹脂層12(13)へのせん断力として直に及ぶのを防いでおり、よって、配線パターン21a(22a)を埋め込んで基層11上に積層された樹脂層12(13)に亀裂が生じるなどの悪影響を防止できる。この点を補足的に図示したものが図2である。   With such a configuration, the thermal deformation of the longitudinal conductor 31 is prevented from being directly applied as a shearing force to the resin layer 12 (13). Therefore, the wiring pattern 21a (22a) is embedded on the base layer 11. Adverse effects such as the occurrence of cracks in the laminated resin layer 12 (13) can be prevented. FIG. 2 supplementarily illustrates this point.

図2は、図1に示したインターポーザーにおいて縦方向導電体31が変形することによる影響を示す説明図であり、図1中で使用した符号については変更せず付している。ガラス基層11に比較して縦方向導電体31の熱膨張率は数倍以上大きいため、使用中に周りの電子デバイスの発熱により膨張して縦方向導電体31の上面、下面においてはガラス基層11からはみ出す方向に変形しようとする。そこで、図2に示すように、配線パターン21a、22aが上記説明済みの位置に設けられることによって、縦方向導電体31の変形が樹脂層12、13へのせん断力として直に及ぶことが回避される。   FIG. 2 is an explanatory diagram showing the influence of deformation of the longitudinal conductor 31 in the interposer shown in FIG. 1, and the reference numerals used in FIG. 1 are not changed. Since the thermal expansion coefficient of the vertical conductor 31 is several times greater than that of the glass base layer 11, the glass base layer 11 is expanded on the upper and lower surfaces of the vertical conductor 31 by expansion due to heat generated by surrounding electronic devices during use. Attempts to deform in a direction that protrudes. Therefore, as shown in FIG. 2, by providing the wiring patterns 21a and 22a at the above-described positions, the deformation of the vertical conductor 31 is prevented from being directly applied as the shearing force to the resin layers 12 and 13. Is done.

また、配線パターン21a、22aが、縦方向導電体31の下面、上面の領域のすべてを覆わないように設けられている点については以下の理由がある。すなわち、縦方向導電体31の周りには基層11や配線パターン21a、22aという無機材料が存在するが、これらの無機材料は、樹脂を含む縦方向導電体31を発生源とする気体や水分の脱出経路として機能しない。そこで、縦方向導電体31の下面、上面の一部を樹脂層12、13で覆うように構成することで、これらの樹脂層12、13を縦方向導電体31を発生源とする気体や水分の脱出経路として機能させる。これにより縦方向導電体31として大きな信頼性の維持を図ることができる。   The wiring patterns 21a and 22a are provided so as not to cover the entire area of the lower and upper surfaces of the vertical conductor 31 for the following reason. In other words, there are inorganic materials such as the base layer 11 and the wiring patterns 21a and 22a around the vertical conductor 31, and these inorganic materials contain gas or moisture that originates from the vertical conductor 31 containing resin. Does not function as an escape route. Therefore, by configuring the lower surface and a part of the upper surface of the vertical conductor 31 to be covered with the resin layers 12 and 13, the resin layer 12 and 13 may be gas or moisture using the vertical conductor 31 as a source. To function as an escape route. Thereby, it is possible to maintain a large reliability as the vertical conductor 31.

以上説明した点により、この形態によれば、生産効率向上に寄与してコスト削減に貢献しかつ信頼性も高い縦方向導電体31が形成された基層11を含むようにインターポーザーを構成できる。   As described above, according to this embodiment, the interposer can be configured so as to include the base layer 11 on which the longitudinal conductors 31 that contribute to the improvement of production efficiency and contribute to cost reduction and high reliability are formed.

なお、本形態では、より具体的に、ビア孔11aの基層11面における平面形状が円形であり、配線パターン21a、22aが、外側輪郭と内側輪郭とを有する、基層11面のビア孔11aの形状と同心のリング状の形状を有している。ビア孔11aの平面形状として基層11面において円形とすれば、もっとも孔加工として容易であり、また、配線パターン21a、22aをビア孔11aの平面形状に合わせてリング状の形状とすれば、円形状は微細化に適したパターンと考えられるためファイン化に都合がよいと考えられる。   In the present embodiment, more specifically, the planar shape of the via hole 11a on the surface of the base layer 11 is circular, and the wiring patterns 21a and 22a have the outer contour and the inner contour, and the via hole 11a on the surface of the base layer 11 has. It has a ring shape concentric with the shape. If the via hole 11a has a circular shape on the surface of the base layer 11 as the planar shape, the hole is most easily processed, and if the wiring patterns 21a and 22a have a ring shape in accordance with the planar shape of the via hole 11a, a circular shape is obtained. Since the shape is considered to be a pattern suitable for miniaturization, it is considered convenient for refinement.

さらに具体的に、ビア孔11aの径と配線パターン21a、22aの内側輪郭の径との関係を2対1程度に設定し、ビア孔11aの径と配線パターン21a、22aの外側輪郭の径との関係を2対3程度に設定するのが、バランスのよいひとつのレイアウトになる。このようにすれば、ビア孔11aと配線パターン21aとの形成位置ずれにも十分対応した上で、説明した効果を維持しかつファイン化も実現する。   More specifically, the relationship between the diameter of the via hole 11a and the diameter of the inner contour of the wiring patterns 21a and 22a is set to about 2 to 1, and the diameter of the via hole 11a and the outer contour of the wiring patterns 21a and 22a Setting the relationship of 2 to 3 is a well-balanced layout. In this way, the above-described effects can be maintained and refinement can be realized while sufficiently dealing with the formation position deviation between the via hole 11a and the wiring pattern 21a.

以上一実施形態について説明したが、以下補足を行う。配線層間絶縁層である樹脂層12、13の構成や、縦方向導電体31に接触または電気的につながる導体(配線パターン21a、ビアホール内めっきビア21b、配線パターン21c、配線パターン22a、ビアホール内めっきビア22b、配線パターン22c)の構成については、公知の種々の構成を利用することができる。絶縁層や配線パターンの層数も必要に応じて任意に選択することができる。   Although one embodiment has been described above, supplementary explanation will be given below. The structure of the resin layers 12 and 13 which are wiring interlayer insulation layers, and conductors connected to or electrically connected to the longitudinal conductor 31 (wiring pattern 21a, via hole plating via 21b, wiring pattern 21c, wiring pattern 22a, via hole plating) Various known configurations can be used for the configuration of the via 22b and the wiring pattern 22c). The number of insulating layers and wiring patterns can be arbitrarily selected as necessary.

例えばビアホール内めっきビアは、これに代えて導電性組成物によるビアを採用してもよい。配線パターンについては、金属箔(例えば銅箔など)のエッチングによるサブトラクティブな形成のほか、導電性ペースト(例えば金属ナノペーストなど)の塗布やめっきによる形成などアディティブな形成を採用することもできる。樹脂層の具体的な材料や、各導体の具体的な材料についても公知の種々のものを活用することができる。   For example, the via-hole plated via may be replaced with a via made of a conductive composition. For the wiring pattern, in addition to subtractive formation by etching a metal foil (for example, copper foil), additive formation such as application of a conductive paste (for example, metal nanopaste) or formation by plating can be employed. Various known materials can be used for the specific material of the resin layer and the specific material of each conductor.

また、ビア孔11aについては、その内壁面のガラス素材に導電性組成物による縦方向導電体31をそのまま対向させる以外に、内壁面上に金属(例えば銅)のめっき層を形成するようにしてから導電性組成物を充填して縦方向導電体31を形成するようにしてもよい。このようにすれば縦方向導電体としてより低抵抗のものを形成できる。この場合、めっき層の形成厚さの分、縦方向導電体が横方向に大型化するため、めっき層をより薄く形成するなどして縦方向導電体31の配置密度の低下を防止するように留意する。   In addition, with respect to the via hole 11a, a metal (for example, copper) plating layer is formed on the inner wall surface, in addition to the longitudinal conductor 31 made of the conductive composition facing the glass material of the inner wall surface as it is. Alternatively, the longitudinal conductor 31 may be formed by filling the conductive composition. In this way, a lower resistance can be formed as the longitudinal conductor. In this case, since the vertical conductor is increased in size in the horizontal direction by the formation thickness of the plating layer, the plating layer is formed thinner to prevent the arrangement density of the vertical conductors 31 from being lowered. pay attention to.

また、ガラス基層11の素材については、この形態のようにガラスを用いるのが低コストを図る上で好ましい。ただし、ガラスに限らず、ほかの無機材料、例えばシリコンのような半導体の板を用いることも可能である。シリコンを用いる場合は、例えば、シリコン基層にビア孔11aを形成した後、このシリコン基層を熱酸化工程に供して、ビア孔11aの内壁面上を含めて全表面上に熱酸化膜(=絶縁膜)を形成する。これによればビア孔11a内に導体を位置させてもそれらの導体間の絶縁性は確保でき、また図示の位置に配線パターン21a、22aを形成しても支障が生じない。   Moreover, about the raw material of the glass base layer 11, it is preferable to use glass like this form from the viewpoint of low cost. However, it is possible to use not only glass but also other inorganic materials, for example, a semiconductor plate such as silicon. In the case of using silicon, for example, after forming a via hole 11a in the silicon base layer, this silicon base layer is subjected to a thermal oxidation process, and a thermal oxide film (= insulation) is formed on the entire surface including the inner wall surface of the via hole 11a. Film). According to this, even if a conductor is positioned in the via hole 11a, insulation between these conductors can be ensured, and even if the wiring patterns 21a and 22a are formed at the illustrated positions, no trouble occurs.

次に、図1に示したインターポーザーを製造する工程例について以下説明する。図3、図4は、図1に示したインターポーザー基板の、主たる製造過程を示す工程図である。図3、図4において、図1中に示したものと同一、または同一相当のものには同一符号を付してある。   Next, an example of a process for manufacturing the interposer shown in FIG. 1 will be described below. 3 and 4 are process diagrams showing a main manufacturing process of the interposer substrate shown in FIG. 3 and 4, the same or equivalent parts as those shown in FIG. 1 are denoted by the same reference numerals.

まず、図3(a)に示すように、加工前のガラス基層11(想定される厚さは例えば50μm〜1000μm。典型的には例えば300μm)を用意し、その必要な個所にビア孔11a(孔径は例えば10μm〜100μm。典型的には例えば60μm)を例えばレーザ加工で貫通形成する。レーザ加工に加えフッ酸で孔の内壁をエッチングして拡げあるいは平滑化する処理を行ってもよい。また、ガラス基層11として感光性ガラスなど、光反応性のガラスを利用すると孔開けの加工がより簡単になる。レーザ加工に代えて、サンドブラストなどの公知の方法による孔形成も採用し得る。   First, as shown in FIG. 3A, a glass base layer 11 (assumed thickness is, for example, 50 μm to 1000 μm, typically 300 μm) before processing is prepared, and via holes 11a ( The hole diameter is, for example, 10 μm to 100 μm (typically, for example, 60 μm). In addition to laser processing, etching may be performed to expand or smooth the inner wall of the hole with hydrofluoric acid. Further, when a photoreactive glass such as a photosensitive glass is used as the glass base layer 11, the drilling process becomes easier. Instead of laser processing, hole formation by a known method such as sand blasting may be employed.

次に、形成されたビア孔11a内に、縦方向導電体31とすべき導電性組成物を例えばスクリーン印刷を用いて充填する。このとき使用するスクリーン版には、ビア孔11aの位置に相当する位置に印刷孔(ピット)が設けられている。印刷する導電性組成物は、熱硬化性樹脂中に微細な金属粒子(例えば銀粒子)が分散され全体として導電性を有する、よく知られた組成物である。   Next, the formed via hole 11a is filled with a conductive composition to be the longitudinal conductor 31 by using, for example, screen printing. The screen plate used at this time is provided with printing holes (pits) at positions corresponding to the positions of the via holes 11a. The conductive composition to be printed is a well-known composition having fine metal particles (for example, silver particles) dispersed in a thermosetting resin and having conductivity as a whole.

ビア孔11a内に導電性組成物を充填したら、次に、この導電性組成物を乾燥させ、さらに熱硬化する。導電性組成物が乾燥、硬化されることにより縦方向導電体31になる(図3(b)参照)。以上、ガラス基層11の部分に関する製造過程である。   Once the via hole 11a is filled with the conductive composition, the conductive composition is then dried and further thermally cured. When the conductive composition is dried and cured, the vertical conductor 31 is formed (see FIG. 3B). The manufacturing process related to the glass base layer 11 has been described above.

次に、図3(c)に示すように、縦方向導電体31が形成された後のガラス基層11の上下面上に配線パターン21a、22aを形成する。形成方法は、周知の方法、例えば、(1)金属箔(銅箔)を積層してエッチングを行う、(2)スパッター、蒸着、めっきなどのプロセスを利用して金属(銅)パターンを形成する、(3)導電性ペースト(例えば金属ナノペーストなど)の塗布により導電パターンを形成する、などの中から適宜選択することができる。   Next, as shown in FIG. 3C, wiring patterns 21a and 22a are formed on the upper and lower surfaces of the glass base layer 11 after the vertical conductors 31 are formed. As a forming method, for example, (1) a metal foil (copper foil) is stacked and etched, and (2) a metal (copper) pattern is formed using processes such as sputtering, vapor deposition, and plating. (3) A conductive pattern is formed by applying a conductive paste (for example, a metal nano paste), and the like.

例としてめっきプロセスで配線パターン21a、22aを形成する場合は、例えば以下の工程を行う。まず、縦方向導電体31が形成された後のガラス基層11の上下面上に、シード層(例えばクロム層(クロムニッケル層)のあと銅層)を例えばスパッターで形成する。次に、シード層上に位置選択的にレジスト膜を形成し、その状態で電解銅めっき工程を行う。そして、レジスト膜を除去し、さらにレジスト膜下に現れたシード層をエッチング除去する。これにより、レジスト膜による抜けたパターンに従い配線パターン21a、22aが形成できる。   For example, when the wiring patterns 21a and 22a are formed by a plating process, for example, the following steps are performed. First, a seed layer (for example, a copper layer after a chromium layer (chromium nickel layer)) is formed by sputtering, for example, on the upper and lower surfaces of the glass base layer 11 after the vertical conductor 31 is formed. Next, a resist film is selectively formed on the seed layer, and an electrolytic copper plating process is performed in that state. Then, the resist film is removed, and the seed layer appearing under the resist film is removed by etching. Thereby, the wiring patterns 21a and 22a can be formed according to the missing pattern by the resist film.

配線パターン21a、22aが形成できたら、次に、それらの上に樹脂層12、13を積層、形成する。樹脂層12、13は、例えば、熱硬化性樹脂を用い、当初は未硬化状態のものを積層し加熱加圧して流動化させその後硬化させることで形成できる。次に、形成された樹脂層12、13に、形成すべきビアホール内めっきの位置に相当して、ビア孔21h、22hを例えばレーザ加工により形成する(以上、図4(a)を参照)。   After the wiring patterns 21a and 22a are formed, the resin layers 12 and 13 are stacked and formed on them. The resin layers 12 and 13 can be formed by, for example, using a thermosetting resin, laminating an uncured state at first, fluidizing it by heating and pressing, and then curing it. Next, via holes 21h and 22h are formed in the formed resin layers 12 and 13 by laser processing, for example, corresponding to the position of via-hole plating to be formed (see FIG. 4A).

そして、ビア孔内を充填してビア21b、22bを形成するようにかつ配線パターン21c、22cを形成するように、めっきプロセスを施す(図4(b)を参照)。なお、配線パターン21c、22cについては、ビア21b、22bとは別のプロセスまたは方法(配線パターン21a、22aでの説明と同様)により設けることもできる。   Then, a plating process is performed so that the via holes 21b and 22b are formed by filling the via holes and the wiring patterns 21c and 22c are formed (see FIG. 4B). Note that the wiring patterns 21c and 22c can be provided by a process or method different from that of the vias 21b and 22b (similar to the description of the wiring patterns 21a and 22a).

配線パターン21c、22cの形成まで終わったら、次に、配線カバー膜41、42をパターン形成し、さらにその後、ニッケル金メッキ層21d、22dの形成を行う。以上より、図1に示したインターポーザーを製造することができる。なお、はんだボール51の取り付けは、実際上、ニッケル金めっき層22dが形成された接続ランドへの半導体チップ(不図示)の実装後に行われることが多い。   After completing the formation of the wiring patterns 21c and 22c, next, the wiring cover films 41 and 42 are formed, and then the nickel gold plating layers 21d and 22d are formed. From the above, the interposer shown in FIG. 1 can be manufactured. The solder ball 51 is actually attached in many cases after mounting a semiconductor chip (not shown) on a connection land on which the nickel gold plating layer 22d is formed.

次に、図5を参照して、別の実施形態である配線板の例としてインターポーザーの場合について説明する。図5は、別の実施形態である配線板の例としてインターポーザーの場合の構成を模式的に示す断面図および要部の平面図であり、図1中に示した構成と同一または同一相当のものには同一符号を付してある。その部分については加えるべき事項がない限り説明を省略する。なお、図5(a)に示す断面は、図5(b)中に示すB−Ba位置における断面に相当する。図5(b)の図示は、同図中に示される要素のみを描いた要部の平面図である。   Next, with reference to FIG. 5, the case of an interposer will be described as an example of a wiring board according to another embodiment. FIG. 5 is a cross-sectional view schematically showing a configuration in the case of an interposer as an example of a wiring board according to another embodiment, and a plan view of the main part. The same reference numerals are given to the objects. The description is omitted unless there is a matter to be added. In addition, the cross section shown to Fig.5 (a) is corresponded in the cross section in the B-Ba position shown in FIG.5 (b). The illustration of FIG. 5B is a plan view of the main part depicting only the elements shown in the figure.

このインターポーザーの、図1に示したものとの構成上の違いは、配線パターン21a、22aの内側輪郭から離間してさらに内側に、縦方向導電体31の上下面に接触するように、新たに導体(配線パターン21a1、22a1)がそれぞれ設けられている点である。配線パターン22a1、22a1は、ガラス基層11を平面視する方向において同じ投影図形である。電気的に、新たな配線パターン21a1はもとの配線パターン21aを補助する導体として、新たな配線パターン22a1はもとの配線パターン22aを補助する導体として、それぞれ捉えることができる。なお、新たな配線パターン22a1、22a1は、これらのうち一方のみを新たに設けるとする構成も考えられる。   The difference in configuration of this interposer from that shown in FIG. 1 is that the interposer is further away from the inner contours of the wiring patterns 21a and 22a and further inwardly in contact with the upper and lower surfaces of the vertical conductor 31. Are provided with conductors (wiring patterns 21a1, 22a1) respectively. The wiring patterns 22a1 and 22a1 are the same projected figures in the direction in which the glass base layer 11 is viewed in plan. Electrically, the new wiring pattern 21a1 can be regarded as a conductor that assists the original wiring pattern 21a, and the new wiring pattern 22a1 can be regarded as a conductor that assists the original wiring pattern 22a. It is also possible to adopt a configuration in which only one of the new wiring patterns 22a1 and 22a1 is newly provided.

このインターポーザーおいては、新たに配線パターン21a1、22a1を設けているため、配線パターン21a1、22a1の直上に、図示するように、ビアホール内めきビア21b、22bを設けることができる。したがって、インターポーザーとしてビアの配置の自由度を増加させていることになる。換言すると、ビアホール内めっきビア21b、22bの配置については、図1に示したインターポーザーでのそれと同様の位置を保つこともできる。   In this interposer, since the wiring patterns 21a1 and 22a1 are newly provided, via holes 21b and 22b in the via holes can be provided immediately above the wiring patterns 21a1 and 22a1, respectively. Therefore, the degree of freedom of via arrangement as an interposer is increased. In other words, the arrangement of the via-hole plated vias 21b and 22b can be maintained at the same position as that in the interposer shown in FIG.

なお、配線パターン21a、21a1、22a、22a1が、縦方向導電体31の下面、上面の領域のすべてを覆わないように設けられている点については、図1に示した形態と同じであり、このことによる効果は維持されている。図5に示すインターポーザーの製造工程については特に説明しないが、上記の構成の説明、および図3、図4を参照して説明した製造工程の点から容易に把握することができる。   The wiring patterns 21a, 21a1, 22a, and 22a1 are the same as those shown in FIG. 1 in that the wiring patterns 21a, 21a1, 22a, and 22a1 are provided so as not to cover all of the lower and upper surface regions of the vertical conductor 31. The effect by this is maintained. Although the manufacturing process of the interposer shown in FIG. 5 is not particularly described, it can be easily grasped from the description of the above configuration and the manufacturing process described with reference to FIGS.

以上の実施形態の説明は、例としてインターポーザーの場合を挙げたが、インターポーザーに限らず一般的な配線板の場合であっても、生産効率向上に寄与してコスト削減に貢献しかつ信頼性も高い縦方向導電体が形成された基層を有するという効果の点は変わらない。   In the above description of the embodiment, the case of an interposer is given as an example. However, the present invention is not limited to an interposer, and even in the case of a general wiring board, it contributes to an improvement in production efficiency and contributes to cost reduction and reliability. The effect of having a base layer on which a highly conductive vertical conductor is formed remains the same.

11…ガラス基層、11a…ビア孔、12,13,14,15…樹脂層(配線層間絶縁層)、21a,21a1,21c,22a,22a1,22c…配線パターン、21b,22b…ビアホール内めっきビア、21d,22d…ニッケル金めっき層、21h,22h…ビア孔、31…縦方向導電体、41,42…配線カバー膜(はんだレジスト膜)、51…はんだボール。   DESCRIPTION OF SYMBOLS 11 ... Glass base layer, 11a ... Via hole, 12, 13, 14, 15 ... Resin layer (interconnection layer insulation layer), 21a, 21a1, 21c, 22a, 22a1, 22c ... Wiring pattern, 21b, 22b ... Plating via in via hole 21d, 22d ... nickel gold plating layer, 21h, 22h ... via hole, 31 ... longitudinal conductor, 41, 42 ... wiring cover film (solder resist film), 51 ... solder ball.

Claims (6)

第1面と該第1面の反対の側の第2面とを有し、前記第1面から前記第2面に貫通する孔が複数設けられた無機材料製の基層と、
前記基層の前記第1面に連なるような下面と前記基層の前記第2面に連なるような上面とを有するように前記基層の前記孔それぞれの内部を充填して配置された、導電性組成物でできた縦方向導電体と、
前記縦方向導電体の前記下面の、前記基層の前記第1面との境界線上をすべて覆う一方、該下面の一部の領域上は覆わないように、前記基層の前記第1面上および前記縦方向導電体の前記下面上に設けられた第1の配線パターンと、
前記縦方向導電体の前記下面のうちの前記第1の配線パターンに覆われない領域を覆いかつ前記第1の配線パターンを埋め込むように、前記基層の前記第1面の側に積層状に位置する第1の絶縁層と、
前記縦方向導電体の前記上面の、前記基層の前記第2面との境界線上をすべて覆う一方、該上面の一部の領域上は覆わないように、前記基層の前記第2面上および前記縦方向導電体の前記上面上に設けられた第2の配線パターンと、
前記縦方向導電体の前記上面のうちの前記第2の配線パターンに覆われない領域を覆いかつ前記第2の配線パターンを埋め込むように、前記基層の前記第2面の側に積層状に位置する第2の絶縁層と
を具備する配線板。
A base layer made of an inorganic material having a first surface and a second surface opposite to the first surface, and a plurality of holes penetrating from the first surface to the second surface;
A conductive composition arranged to fill the inside of each of the holes of the base layer so as to have a lower surface continuous with the first surface of the base layer and an upper surface continuous with the second surface of the base layer. A longitudinal conductor made of
The lower surface of the vertical conductor covers the entire boundary line with the first surface of the base layer, but does not cover a part of the lower surface. A first wiring pattern provided on the lower surface of the longitudinal conductor;
Positioned in a stacked manner on the first surface side of the base layer so as to cover a region of the lower surface of the vertical conductor that is not covered by the first wiring pattern and to embed the first wiring pattern. A first insulating layer that
The upper surface of the longitudinal conductor covers the entire boundary line with the second surface of the base layer, but does not cover a part of the upper surface, and covers the second surface of the base layer and the A second wiring pattern provided on the upper surface of the vertical conductor;
Positioned in a stacked manner on the second surface side of the base layer so as to cover a region of the upper surface of the vertical conductor that is not covered with the second wiring pattern and to embed the second wiring pattern. A wiring board comprising: a second insulating layer.
前記基層が、ガラス製である請求項1記載の配線板。   The wiring board according to claim 1, wherein the base layer is made of glass. 前記基層が、前記孔の前記第1面および前記第2面における平面形状がそれぞれ円形であるように前記孔が設けられた基層であり、
前記第1の配線パターンが、外側輪郭と内側輪郭とを有する、前記基層の前記孔の前記第1面における前記円形と同心のリング状の形状を有し、
前記第2の配線パターンが、外側輪郭と内側輪郭とを有する、前記基層の前記孔の前記第2面における前記円形と同心のリング状の形状を有する
請求項1記載の配線板。
The base layer is a base layer provided with the holes so that the planar shapes of the first surface and the second surface of the holes are respectively circular;
The first wiring pattern has an outer contour and an inner contour, and has a ring-like shape concentric with the circle in the first surface of the hole of the base layer;
The wiring board according to claim 1, wherein the second wiring pattern has an outer contour and an inner contour, and has a ring shape concentric with the circle in the second surface of the hole of the base layer.
前記第1の配線パターンの前記内側輪郭から離間してさらに内側に、前記縦方向導電体の前記下面に接触するように設けられた第3の配線パターンをさらに具備し、
前記第1の絶縁層が、前記第3の配線パターンをも埋め込むように設けられており、
前記第1の絶縁層を貫通するように、前記縦方向導電体に接触する側とは反対の側の前記第3の配線パターン上に設けられた第1絶縁層貫通導体をさらに具備する
請求項3記載の配線板。
A third wiring pattern provided so as to be in contact with the lower surface of the longitudinal conductor further inside and spaced from the inner contour of the first wiring pattern;
The first insulating layer is provided to embed the third wiring pattern;
The first insulating layer through conductor provided on the third wiring pattern on the side opposite to the side in contact with the longitudinal conductor so as to penetrate the first insulating layer. 3. The wiring board according to 3.
前記第2の配線パターンの前記内側輪郭から離間してさらに内側に、前記縦方向導電体の前記上面に接触するように設けられた第3の配線パターンをさらに具備し、
前記第2の絶縁層が、前記第3の配線パターンをも埋め込むように設けられており、
前記第2の絶縁層を貫通するように、前記縦方向導電体に接触する側とは反対の側の前記第3の配線パターン上に設けられた第2絶縁層貫通導体をさらに具備する
請求項3記載の配線板。
A third wiring pattern provided to be in contact with the upper surface of the vertical conductor further inside and spaced from the inner contour of the second wiring pattern;
The second insulating layer is provided to embed the third wiring pattern;
The semiconductor device further includes a second insulating layer through conductor provided on the third wiring pattern on a side opposite to the side in contact with the longitudinal conductor so as to penetrate the second insulating layer. 3. The wiring board according to 3.
第1面と該第1面の反対の側の第2面とを有する無機材料製の基層に貫通孔を形成する工程と、
前記基層の前記貫通孔内に導電性組成物を充填して、前記基層の前記第1面に連なるような下面と前記基層の前記第2面に連なるような上面とを有する縦方向導電体を形成する工程と、
前記縦方向導電体の前記下面の、前記基層の前記第1面との境界線上をすべて覆う一方、該下面の一部の領域上は覆わないように、前記基層の前記第1面上および前記縦方向導電体の前記下面上に第1の配線パターンを設ける工程と、
前記縦方向導電体の前記上面の、前記基層の前記第2面との境界線上をすべて覆う一方、該上面の一部の領域上は覆わないように、前記基層の前記第2面上および前記縦方向導電体の前記上面上に第2の配線パターンを設ける工程と、
前記縦方向導電体の前記下面のうちの前記第1の配線パターンに覆われない領域を覆いかつ前記第1の配線パターンを埋め込むように、前記基層の前記第1面の側に積層状に第1の絶縁層を形成する工程と、
前記縦方向導電体の前記上面のうちの前記第2の配線パターンに覆われない領域を覆いかつ前記第2の配線パターンを埋め込むように、前記基層の前記第2面の側に積層状に第2の絶縁層を形成する工程と
を具備する配線板の製造方法。
Forming a through hole in a base layer made of an inorganic material having a first surface and a second surface opposite to the first surface;
A longitudinal conductor having a bottom surface that is continuous with the first surface of the base layer and a top surface that is continuous with the second surface of the base layer by filling the through hole of the base layer with a conductive composition. Forming, and
The lower surface of the vertical conductor covers the entire boundary line with the first surface of the base layer, but does not cover a part of the lower surface. Providing a first wiring pattern on the lower surface of the longitudinal conductor;
The upper surface of the longitudinal conductor covers the entire boundary line with the second surface of the base layer, but does not cover a part of the upper surface, and covers the second surface of the base layer and the Providing a second wiring pattern on the upper surface of the longitudinal conductor;
The base layer is stacked on the first surface side so as to cover a region of the lower surface of the vertical conductor that is not covered by the first wiring pattern and to embed the first wiring pattern. Forming an insulating layer of 1;
The upper surface of the vertical conductor is stacked on the second surface side of the base layer so as to cover a region not covered by the second wiring pattern and to embed the second wiring pattern. And a step of forming an insulating layer.
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