JP2008041790A - Manufacturing method of interposer board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method capable of manufacturing a very reliable interposer board in which the adhesion of a through-electrode to a wiring layer is excellent. <P>SOLUTION: The interposer board manufacturing method comprises processes of forming a wiring forming conductive material layer 18(19) on, at least, one surface of the board main body of a silicon board where the through electrode is provided penetrating it through in a perpendicular direction, and then patterning the wiring forming conductive material layer 18(19) into a wiring layer with an electrode pad electrically connected to the through electrode. In the interposer board manufacturing method, degassing holes 22 are bored in the wiring forming conductive material layer 18(19). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing an interposer substrate used for high-density mounting of semiconductor chips.

  2. Description of the Related Art In recent years, semiconductor chips having small and large-scale integrated circuits are used in electronic devices, particularly computers and communication devices, as functions increase. As a method for increasing the degree of circuit integration in a small size, there are proposed an SOC (System On Chip) in which circuits are integrated on one chip and an SIP (System In Package) in which a plurality of chips are integrated in one package. Among these systems, SIP has the advantage that the cost in designing and processing of a semiconductor substrate can be reduced because existing chips can be used in combination.

  In such a SIP, each semiconductor chip is mounted on a substrate called an interposer. In particular, as an interposer that can cope with high speed and large capacity, wiring provided on both main surfaces through a silicon substrate. One having a through electrode connected to a layer is known (see, for example, Patent Document 1).

FIG. 7 shows an example thereof. The silicon substrate 1, the via hole 2 that penetrates the silicon substrate 1 in the thickness direction, and the inner wall of the via hole 2 are sequentially provided on both main surfaces of the silicon substrate 1. An insulating layer 3 made of silicon dioxide (SiO ₂ ) or the like, a barrier layer 4 made of titanium nitride (TiN) or the like, a through electrode (via) 5 made of copper (Cu) or the like formed in the via hole 2, and First and second wiring layers 6 and 7 having first and second electrode pads 6a and 7a provided on both surfaces are provided.

Such an interposer is generally manufactured by the following method.
First, a hole that does not penetrate the substrate is formed on one main surface of the silicon substrate 1 by a method such as RIE (Reactive Ion Etching), Deep RIE, optical etching, or wet etching. Next, the silicon substrate 1 is retracted (thinned) by a method such as grinding from the other main surface of the silicon substrate 1, that is, the surface opposite to the surface where the holes are formed, and then the holes are penetrated. An insulating film 3 and a barrier layer 4 are formed on the inner surface of the hole (via hole 2) and both main surfaces of the silicon substrate 1 by LPCVD (Low Pressure Chemical Vapor Deposition) method or the like. Next, after the conductive material for the through electrode 5 is embedded in the through hole in which the insulating layer 3 and the barrier layer 4 are formed in order, the excess conductive material protruding from the through hole is removed by a CMP (Chemical Mechanical Polishing) method. Thereafter, first and second wiring conductor layers are formed on both main surfaces with copper (Cu), and further patterned to have first and second electrode pads 6a and 7a. 2 wiring layers 6 and 7 are formed (see, for example, Patent Document 1).

  Or after forming the hole which does not penetrate a board | substrate in one main surface of the silicon substrate 1, the insulating layer 3 and the barrier layer 4 are formed in order on the inner surface of this hole, and one main surface of the silicon substrate 1, A conductive material for the through electrode 5 is embedded in these holes. Thereafter, the silicon substrate 1 is retracted (thinned) to penetrate the hole, and the first and second wiring conductor layers are formed. Then, the first and second wiring layers 6 and 7 are patterned. Form.

  However, in such a conventional method for manufacturing an interposer substrate, when the first and second wiring conductor layers are formed, the portions where the electrode pads 6a and 7a of the through electrode 5 are formed are swollen. was there. When such swelling occurs, the adhesion between the first and second wiring layers 6 and 7 and the through electrode 5 decreases, and the reliability of the substrate is impaired.

Therefore, as a result of intensive research to prevent the occurrence of such blisters, the present inventor is the main cause of blistering due to the water vapor generated in the via hole 2 in the process of forming the through electrode 5. It has been found that the above problem can be solved by preventing the problem by some method or discharging it to the outside.
Special table 2003-503855 gazette

  The present invention has been made based on such knowledge, and an object thereof is to provide a method capable of manufacturing a highly reliable interposer substrate having excellent adhesion between a through electrode and a wiring layer.

  In a method of manufacturing an interposer substrate according to an aspect of the present invention, a conductive material layer for forming a wiring is formed on at least one main surface of a substrate body provided with a through electrode penetrating in a thickness direction in a silicon substrate. An interposer substrate manufacturing method for patterning a wiring forming conductive material layer to form a wiring layer having an electrode pad electrically connected to the through electrode, wherein the wiring forming conductive material layer is for degassing. A hole is formed.

  According to the method for manufacturing an interposer substrate according to one embodiment of the present invention, a highly reliable substrate having excellent adhesion between the through electrode and the wiring layer can be manufactured.

  Embodiments of the present invention will be described below. In the following, embodiments of the present invention will be described with reference to the drawings. However, the drawings are provided for illustration, and the present invention is not limited to the drawings.

(First embodiment)
First, the first embodiment will be described. 1 and 2 are cross-sectional views showing the steps of the method of manufacturing the interposer substrate according to the present embodiment.

  In the first embodiment, first, as shown in FIG. 1A, an etching resist layer 12 patterned by a photolithography method is formed on one main surface of a silicon substrate 11 serving as a base material of an interposer substrate. To do. That is, after a resist layer is formed on the entire main surface of the silicon substrate 11 by roll lamination of a dry film or application of a liquid resist, the resist layer is exposed and developed to form a patterned etching resist layer 12. Form.

  Next, as shown in FIG. 1B, one main surface side of the silicon substrate 11 is etched using the patterned etching resist layer 12 as a mask to form a hole 13 that does not penetrate the silicon substrate 11. For the etching, a method such as RIE, Deep RIE, optical etching, wet etching, or the like can be used. For forming the hole 13, a processing method using a laser or a micro drill can be applied. In the case of using such a processing method, the formation of the etching resist layer 12 and the subsequent removal step of the etching resist layer 12 shown in FIG. 1A can be omitted.

  Next, as shown in FIG. 1C, the patterned etching resist layer 12 is removed, and the other main surface of the silicon substrate 11 is ground until, for example, the thickness of the silicon substrate 11 becomes 150 μm. Then, the hole 13 is penetrated. As a result, a via hole 14 having a diameter of 70 μm and a depth of 150 μm, for example, penetrating the silicon substrate 11 in the thickness direction is formed.

  After the via hole 14 is formed, an insulating layer 15 and a barrier layer 16 are sequentially formed on the inner wall of the via hole 14 and subsequent main surfaces of the silicon substrate 11 as shown in FIG.

The insulating layer 15 is made of, for example, silicon dioxide (SiO ₂ ), silicon nitride (SiN), silicon carbide (SiC), or the like, and is formed by, for example, LPCVD, plasma CVD, or sputtering. When the insulating layer 15 is made of silicon dioxide (SiO ₂ ), it can be formed by a thermal oxidation method or an anodic oxidation method. The insulating layer 15 may be formed as a single layer or may have a stacked structure of two or more layers.

  The barrier layer 16 is a metal material containing titanium (Ti), such as titanium nitride (TiN), titanium (Ti), titanium nitride silicon (TiSiN), or the like, which has a diffusion preventing effect on copper, tantalum (Ta), and tantalum nitride. It is made of a metal material containing tantalum (Ta) such as (TaN) or a metal material containing tungsten (W) such as tungsten nitride (WN). For film formation, an LPCVD method, a plasma CVD method, a sputtering method, an electroless plating method, or the like is used. The barrier layer 16 may be formed as a single layer or may have a laminated structure of two or more layers. When the insulating layer 15 is made of silicon nitride (SiN), the barrier layer 16 may be omitted because silicon nitride (SiN) serves as a barrier for copper diffusion.

  Next, as shown in FIG. 1E, copper (Cu) or a copper alloy 17A, which is a material for forming a through electrode, is embedded in the via hole 14 by, for example, a combination of sputtering and electrolytic plating. For embedding the copper (Cu) or the copper alloy 17, a sputtering method, an electroless plating method, a molten metal suction method, a printing method, a CVD method, or the like can also be used.

  Next, as shown in FIG. 2F, excess copper (Cu) or copper alloy 17A protruding from the via hole 14 is removed by a CMP (Chemical Mechanical Polishing) method or the like, and the through electrode 17 is formed.

  Next, as shown in FIG. 2 (g), a first made of copper (Cu) or a copper alloy having a thickness of, for example, about 1 to 10 μm is formed on both main surfaces of the silicon substrate 11 on which the through electrodes 17 are formed. And second wiring forming conductive material layers, that is, first and second wiring layers 20, 21 having first and second electrode pads 20 a, 21 a electrically connected through the through electrode 17. Conductive material layers 18 and 19 for forming are formed. At that time, a plurality of degassing holes 22 are formed around the portion where the first and second electrode pads 20a and 21a are formed. In this embodiment, as shown in FIG. 3, the gas vent hole 22 is a portion to be the first and second electrode pads 20a, 21a of the first and second wiring forming conductive material layers 20, 21. (For example, a circular shape having a diameter of 90 μm) is provided along the outer periphery, and each hole 22 is, for example, a sector shape in which an annular hole having an inner diameter of 90 μm and an outer diameter of 150 μm is divided into a plurality (four in the example of the drawing). It is formed into a shape.

  By providing a plurality of vent holes 22 in the vicinity of the through electrode 17 in this way, the water vapor generated in the via hole 14 in the previous step, that is, in the process of forming the through electrode 17, is removed from the vent hole 22. Therefore, the portion where the through electrode 17 of the first and second wiring forming conductive material layers 18 and 19 is located does not swell as seen in the conventional example, and the through electrode 17 In contrast, the first and second wiring forming conductive material layers 18 and 19 having good adhesion can be formed.

  The shape and number of the vent holes 22 are not particularly limited to such an example. For example, as shown in FIG. 4, a large number of circular or polygonal small holes, You may make it provide along the outer periphery of the part used as the 2nd electrode pad 20a, 21a. However, from the viewpoint of ease of formation and gas venting effect, as shown in FIG. 3, it is preferable to form a plurality of annular holes, preferably in a shape divided into about 3 to 5. 3 and 4, reference numeral 23 denotes a formation part of the first and second electrode pads 20 a and 21 a, and 24 denotes the position of the through electrode 17.

  The wiring forming conductive material layers 18 and 19 having such gas venting holes 22 can be formed as follows, for example. First, a thin conductive seed layer is formed by sputtering on one main surface of the silicon substrate 11 on which the through electrode 17 is formed, and then a dry film roll laminate or a liquid resist coating is applied to the surface of the conductive seed layer. A resist layer is formed by attaching. Next, the resist layer is exposed to light and developed to form a plating resist layer in the portion where the gas vent hole 22 is to be formed, and then electrolysis is performed on the portion of the conductive seed layer where the plating resist layer is not formed. A plating layer is formed by plating. Thereafter, the plating resist layer is removed, and unnecessary portions of the conductive seed layer are removed by flash etching. A similar process is performed on the other main surface of the silicon substrate 11. Thereby, the conductive material layers 18 and 19 for wiring formation which have the hole 22 for degassing are formed.

  After forming the first and second wiring forming conductive material layers 18 and 19 having the degassing holes 22 in the vicinity of the through electrodes 17 in this way, as shown in FIG. The first and second wiring forming conductive material layers 18 and 19 are patterned by a conventional method to form the first and second wiring layers 20 and 21. As a result, an interposer substrate on which the first and second wiring layers 20 and 21 having the first and second electrode pads 20a and 21a electrically connected via the through electrode 17 are formed is obtained.

  As described above, according to the method of manufacturing the interposer substrate of the present embodiment, the water vapor generated in the via hole 14 in the process of forming the through electrode 17 penetrating the silicon substrate 11 in the thickness direction is the hole for degassing. The first and second conductive material layers 18 and 19 for forming a wiring having good adhesion to the through electrode 17 are formed so that the portion where the through electrode 17 is located does not swell and is discharged quickly. Can do. Accordingly, the first and second wiring layers 20 and 21 formed by patterning the first and second wiring forming conductive material layers 18 and 19 are also excellent in adhesion to the through electrode 17. Thus, a highly reliable interposer substrate can be obtained.

(Second Embodiment)
Next, a second embodiment will be described. 5 and 6 are cross-sectional views showing the steps of the method of manufacturing the interposer substrate according to the present embodiment. This embodiment differs from the first embodiment described above in that a conductive material for a through electrode is embedded after a hole 13 that does not penetrate the silicon substrate 11 is provided before the hole 13 is penetrated. Is different. In addition, the same code | symbol is attached | subjected about the part which is common in 1st Embodiment, and the overlapping description is partially abbreviate | omitted.

  In the second embodiment, first, as shown in FIGS. 5A and 5B, etching is performed by patterning a main surface of a silicon substrate 11 serving as a base material of an interposer substrate by a photolithography method. After the resist layer 12 is formed, the main surface side of the silicon substrate 11 is etched using the patterned resist layer 12 as a mask to form a hole 13 that does not penetrate the silicon substrate 11. This step is the same as the step shown in FIGS. 1A and 1B in the first embodiment.

  Next, as shown in FIG. 5C, the insulating layer 15 and the barrier layer 16 are formed in order on the inner wall of the hole 13 that does not penetrate and the main surface of the silicon substrate 11 that follows. The insulating layer 15 and the barrier layer 16 can be formed in the same manner as in the first embodiment.

  Next, as shown in FIG. 5D, copper (Cu) or a copper alloy 17A, which is a material for forming the through electrode, is embedded in the hole 13 that does not penetrate, for example, by a combination of sputtering and electrolytic plating. For embedding the copper (Cu) or the copper alloy 17, a sputtering method, an electroless plating method, a molten metal suction method, a printing method, a CVD method, or the like can also be used.

  Next, as shown in FIG. 5E, excess copper (Cu) or copper protruding from the hole 13 so that copper (Cu) or copper alloy 17A remains only in the hole 13 by CMP or the like. Alloy 17A is removed.

  Next, as shown in FIG. 6F, the other main surface of the silicon substrate 11 is ground to expose the copper (Cu) or the copper alloy 17A. Thus, the through electrode 17 is formed in the via hole 14 having a diameter of 70 μm and a depth of 150 μm that penetrates the silicon substrate 11 in the thickness direction.

  Next, as shown in FIG. 6G, the insulating layer 15 and the barrier layer 16 are sequentially formed on the other main surface of the silicon substrate 11, and the through electrode 17 is exposed again.

  In the step shown in FIG. 5D, the insulating layer 15 and the barrier layer 16 covering one main surface of the silicon substrate 11 together with the copper (Cu) or the copper alloy 17A embedded in the hole 13 are also sequentially removed by the CMP method. can do. In this case, similarly to the step shown in FIG. 6G, the insulating layer 15 and the barrier layer 16 are sequentially formed, and then the through electrode 17 is exposed.

  Thereafter, first and second wiring forming conductive material layers 18 and 19 are formed in the same manner as in the steps shown in FIGS. 2G and 2H in the first embodiment. The first and second wiring forming conductive material layers 18 and 19 are patterned to form the first and second wiring layers 20 and 21.

  That is, first, as shown in FIG. 6H, first and second wirings made of copper (Cu) or a copper alloy having a thickness of, for example, about 1 to 10 μm are formed on both main surfaces of the silicon substrate 11. Conductive material layer, that is, a conductive material for forming the first and second wiring layers 20, 21 having the first and second electrode pads 20a, 21a electrically connected through the through electrode 17 Layers 18 and 19 are formed, respectively. At that time, a plurality of degassing holes 22 are formed around the portion where the first and second electrode pads 20a and 21a are formed. By providing a plurality of gas vent holes 22 in the vicinity of the through electrode 17 in this manner, the water vapor generated in the via hole 14 in the previous step, that is, in the process of forming the through electrode 17 is degassed. Therefore, the portion where the through electrode 17 of the first and second wiring forming conductive material layers 18 and 19 is located does not swell as seen in the conventional example, and the through electrode 17 In contrast, the first and second wiring forming conductive material layers 18 and 19 having good adhesion can be formed.

  Next, as shown in FIG. 6 (i), the first and second wiring forming conductive material layers 18 and 19 are patterned by a conventional method to form the first and second wiring layers 20 and 21. Form. As a result, an interposer substrate on which the first and second wiring layers 20 and 21 having the first and second electrode pads 20a and 21a electrically connected via the through electrode 17 are formed is obtained.

  Also in the method of manufacturing the interposer substrate of the present embodiment, the water vapor generated in the via hole 14 in the process of forming the through electrode 17 penetrating the silicon substrate 11 in the thickness direction is the same as in the first embodiment. The first and second wiring-forming conductive material layers 18 having good adhesion to the through-electrodes 17 that do not swell in the portions where the through-electrodes 17 are located, because they are quickly discharged from the vent holes 22. 19 can be formed. Accordingly, the first and second wiring layers 20 and 21 formed by patterning the first and second wiring forming conductive material layers 18 and 19 are also excellent in adhesion to the through electrode 17. Thus, a highly reliable interposer substrate can be obtained.

  In addition, this invention is not limited to description content of embodiment described above, It cannot be overemphasized that it can change suitably in the range which does not deviate from the summary of this invention.

It is sectional drawing which shows the process of the first half of the manufacturing method of the interposer substrate which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the process of the second half of the manufacturing method of the interposer substrate which concerns on the 1st Embodiment of this invention. It is a top view which shows the shape of the hole for degassing formed in the process shown in FIG.2 (g). It is a top view which shows the modification of the hole for degassing shown in FIG. It is sectional drawing which shows the process of the first half of the manufacturing method of the interposer board | substrate which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the process of the latter half of the manufacturing method of the interposer board | substrate which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows an example of an interposer board | substrate.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Silicon substrate, 14 ... Via hole, 17 ... Through-electrode, 18 ... 1st wiring formation conductive material layer, 19 ... 2nd wiring formation conductive material layer, 20 ... 1st wiring layer, 20a ... 1st Electrode pad, 21... Second wiring layer, 21a.

Claims (5)

A wiring forming conductive material layer is formed on at least one main surface of a substrate body provided with a through electrode penetrating in the thickness direction in the silicon substrate, and then the wiring forming conductive material layer is patterned to form the through electrode. A method of manufacturing an interposer substrate for forming a wiring layer having electrode pads electrically connected to
A method for manufacturing an interposer substrate, wherein a hole for venting gas is formed in a conductive material layer for wiring formation.   2. The method of manufacturing an interposer substrate according to claim 1, wherein a plurality of the vent holes are provided.   3. The method of manufacturing an interposer substrate according to claim 2, wherein the plurality of vent holes are provided along an outer periphery of a portion where the electrode pad is formed.   4. The method for manufacturing an interposer substrate according to claim 2, wherein the plurality of vent holes have a shape obtained by dividing an annular hole.   The method of manufacturing an interposer substrate according to any one of claims 1 to 4, wherein the through electrode and the wiring layer are made of copper or a copper alloy.

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