JP2017143140A - Method for manufacturing core substrate for wiring circuit board, method for manufacturing wiring circuit board, and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide methods for manufacturing a core substrate, a wiring circuit board and a semiconductor device, which are reliable and enable fine wiring formation by precisely controlling the diameter of a through-hole, removing a thermal strain around the through-hole, and increasing the flatness of a surface of a glass substrate when forming the through-hole in the glass substrate.SOLUTION: A method for manufacturing a core substrate comprises the steps of (1) forming a through-hole in a glass substrate, (2) immersing the glass substrate obtained in the step (1) in a hydrogen fluoride-containing etchant to increase the diameter of the through-hole, and (3) forming a through-electrode in the through-hole and a wiring part on a surface of the glass substrate, provided that the through-electrode is electrically connected with the wiring part. Also, methods for manufacturing a wiring circuit board and a semiconductor device are disclosed, in which the core substrate is used.SELECTED DRAWING: Figure 17

Description

  The present invention relates to a core substrate manufacturing method for forming a printed circuit board (interposer). The present invention also relates to a method for manufacturing a printed circuit board using the above-described method and a method for manufacturing a semiconductor device.

  The printed circuit board (interposer) is interposed between the package board and the semiconductor element. Conventionally, a package substrate is used to connect a semiconductor element having a plurality of contacts arranged at a fine pitch to an external substrate having a plurality of contacts arranged at a coarse pitch. As the package substrate, a ceramic package substrate or a resin package substrate has been used. Various methods have been proposed as a method for connecting a package substrate and a semiconductor element using a printed circuit board (interposer) (see Patent Document 1 and Patent Document 2).

  Since the ceramic package substrate uses the fired metallization as the wiring part, the resistance of the conductive part tends to increase. Furthermore, due to an increase in parasitic capacitance due to the high dielectric constant of ceramic, it is difficult to use it for connecting high-frequency semiconductor devices with high frequency drive.

  On the other hand, since the resin package substrate uses copper wiring formed by plating, the resistance of the wiring can be lowered. Further, since the parasitic capacitance can be reduced by the low dielectric constant of the resin, it is relatively easy to use for connection of high-frequency driving and high-performance semiconductor elements. However, since the linear expansion coefficient of the resin is significantly different from the linear expansion coefficient of the semiconductor element, the generation of stress due to dimensional changes when the temperature rises becomes a problem.

  In recent years, as a printed circuit board (interposer) for high-end applications, a printed circuit board (interposer) manufactured using a silicon substrate or a glass substrate has attracted much attention, and active research has been conducted. In a silicon wiring circuit board (interposer), a technique called TSV (Through-Silicon Via) is used in which a through hole is formed in a silicon substrate, and the formed through hole is filled with a conductive material to form a through electrode. This is a major feature. A similar technique called TGV (Through-Glass Via) is also used in a silicon wiring circuit board (interposer). Through electrodes formed using these technologies are expected to achieve excellent electrical characteristics such as increased signal transmission speed by connecting the front and back surfaces of a silicon substrate or glass substrate with the shortest distance. . Furthermore, by adopting the through electrode, two-dimensional connection with multiple pins becomes possible, and there is a possibility that excellent electrical characteristics can be obtained without the necessity of driving the semiconductor element at a high frequency or improving the performance. These effects are expected to reduce the power consumption of the semiconductor device.

  In addition, since the linear expansion coefficient of the silicon substrate or glass substrate is equal to or close to the linear expansion coefficient of the semiconductor element, it is possible to suppress the generation of stress due to dimensional changes when the temperature rises, There is a possibility of realizing high-density wiring.

  Among them, a glass wiring circuit board (interposer) using a glass substrate has attracted much attention. This is because the size of a silicon wiring circuit board (interposer) is limited to the size of an available silicon wafer, whereas a glass wiring circuit board (interposer) uses a larger glass substrate in large quantities. This is because manufacturing is considered possible. If mass production becomes possible, it will be possible to reduce the manufacturing cost, which has been a major issue for conventional printed circuit boards (interposers) for high-end applications.

  On the other hand, there are many problems to be overcome when manufacturing a glass wiring circuit board (interposer). One of the problems with a glass wiring circuit board (interposer) is that glass is an amorphous material having a low elastic modulus, so that it is easily broken. Methods for forming a through hole in a glass substrate include a drill method, a blast method, an etching method using a reactive gas or hydrofluoric acid, a laser processing method, and the like.

  In the physical processing methods including the drill method and the blast method, there are problems such as generation of microcracks and cracking of the glass substrate. In the etching method using a reactive gas such as a fluorine-based gas, there are problems such as a low etching rate and a long processing time. Further, the etching method using hydrofluoric acid has a problem that a through hole having a small diameter cannot be formed because etching proceeds isotropically.

On the other hand, a laser processing method using a UV laser, a CO ₂ laser, a short pulse laser, or the like has attracted attention because of features such as a high processing speed and the ability to form a through hole with a small diameter. However, since the glass substrate is locally heated to several hundred degrees Celsius at the time of laser irradiation, thermal distortion occurs around the through-hole, and there is a possibility that the glass substrate breaks and / or micro-cracks with time. Further, the glass material melted by heating may be scattered to generate deposits (dross) around the through-holes and / or deposits (nodules) in a region separated from the through-holes. FIG. 1 shows a thermal strain region 3 when a through hole 2 is formed by irradiating a laser beam from the upper surface of a glass substrate 1, FIG. 1 (a) is a photograph of the upper surface, and FIG. It is sectional drawing. Although depending on the processing conditions, the thermal strain region 3 typically has a width of about 10 μm. FIG. 2 shows microcracks 4 and dross 5 generated around the through-hole 2 when the through-hole 2 is formed by irradiating laser light from the upper surface of the glass substrate 1, and FIG. FIG. 2B is a photograph and FIG. 2B is a cross-sectional view. Although it depends on the processing conditions, typically, the dross 5 and the nodule (not shown) have a height of about 10 μm from the surface of the glass substrate 1.

  It has been proposed to reduce the thermal strain region 3 by suppressing the temperature rise of the glass substrate 1 during laser irradiation, or by heat-treating the glass substrate 1 at a temperature of 500 to 600 ° C. after the formation of the through hole 2. Yes. In addition, several methods for suppressing microcracks 4 generated by the laser processing method and removing dross 5 and nodules generated by the laser processing method have been proposed (see Patent Document 3 and Patent Document 4).

  Further, the diameter of the through hole 2 of the glass substrate 1 formed by the laser processing method is controlled by the laser output, the aperture diameter, the number of shots, and the like. However, it is highly difficult to form the through hole 2 having the designed hole diameter by the laser processing method. Further, when the through hole 2 having a large hole diameter is formed by increasing the number of shots, there are problems such that thermal strain increases and microcracks 4 are easily generated.

JP 2001-102479 A JP 2002-261204 A JP 2000-302488 A JP 2000-246474 A

  One problem to be solved by the present invention is to provide a method capable of precisely controlling the diameter of a through hole when the through hole is formed in a glass substrate. Another problem to be solved by the present invention is that when a through hole is formed in a glass substrate, the glass surface after the formation of the through hole is smoothed and a thermal strain region around the through hole is eliminated, It is to provide a method that makes it possible to form a highly reliable wiring on the surface.

The manufacturing method of the core substrate of the first embodiment of the present invention includes (1) a step of forming a through hole in a glass substrate, and (2) an etching including hydrogen fluoride on the glass substrate obtained in step (1). A step of increasing the hole diameter of the through-hole by immersing in a liquid; and (3) forming a through-electrode in the through-hole and a wiring portion on the surface of the glass substrate. The wiring portion is electrically connected. Here, the hole diameter of the through hole at the end of the step (1) is 50 μm or less, and the hole diameter of the through hole at the end of the step (2) is 10 to 40 μm than the hole diameter of the through hole at the end of the step (1). Larger is desirable. In addition, the maximum height Rz of the surface of the glass substrate at the end of the step (2) is desirably 5 μm or less. Further, step (1) may be performed by light irradiation using a CO ₂ laser. In addition, each of the through electrode and the wiring portion is independently a metal selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, A conductive material selected from the group consisting of an alloy selected from the group consisting of tin-copper, tin-bismuth, and tin-lead may be included.

The method for manufacturing a core substrate according to the second embodiment of the present invention includes (1) a step of providing insulating layers on both surfaces of the glass substrate, (2) forming openings in the insulating layer, and the glass substrate. A step of forming a through hole in the substrate, (3) a step of immersing the glass substrate obtained in step (2) in an etching solution containing hydrogen fluoride to increase the diameter of the through hole, and (4) the glass Forming a through-hole in the substrate and a through-electrode in the opening of the insulating layer, and a wiring portion on the surface of the insulating layer, and the through-electrode and the wiring portion are in electrical communication with each other Features. Here, the hole diameter of the through hole at the end of the step (2) is 50 μm or less, and the hole diameter of the through hole at the end of the step (3) is 10 to 40 μm than the hole diameter of the through hole at the end of the step (2). Larger is desirable. Further, the maximum height Rz of the surface of the insulating layer at the end of the step (3) is desirably 5 μm or less. Furthermore, step (2) may be performed by light irradiation using a CO ₂ laser. In addition, each of the through electrode and the wiring portion is independently a metal selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, A conductive material selected from the group consisting of an alloy selected from the group consisting of tin-copper, tin-bismuth, and tin-lead may be included.

The method for manufacturing a core substrate according to the third embodiment of the present invention includes (1) a step of forming a non-through hole on one surface of a glass substrate, and (2) a step of hooking the glass substrate obtained in step (1). A step of immersing in an etching solution containing hydrogen fluoride to increase the diameter of the non-through hole, and simultaneously making the non-through hole a through hole; (3) the through electrode in the through hole, and the glass substrate surface; Forming the wiring part, and the through electrode and the wiring part are in electrical communication with each other. Here, the hole diameter of the non-through hole at the end of step (1) is 50 μm or less, and the hole diameter of the non-through hole at the end of step (2) is larger than the hole diameter of the non-through hole at the end of step (1). It is desirable that it is 10 to 40 μm larger. In addition, the maximum height Rz of the surface of the glass substrate at the end of the step (2) is desirably 5 μm or less. Further, step (1) may be performed by light irradiation using a CO ₂ laser. In addition, each of the through electrode and the wiring portion is independently a metal selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, A conductive material selected from the group consisting of an alloy selected from the group consisting of tin-copper, tin-bismuth, and tin-lead may be included.

The core substrate manufacturing method of the fourth embodiment of the present invention includes (1) a step of forming a non-through hole on one surface of a glass substrate, and (2) a glass substrate obtained in step (1). A step of increasing the hole diameter of the through-hole by immersing in an etching solution containing hydrogen fluoride, and (3) polishing the other surface of the glass substrate obtained in the step (2) to make the non-through-hole a through-hole. And (4) forming a through electrode in the through hole and a wiring part on the surface of the glass substrate, wherein the through electrode and the wiring part are in electrical communication with each other. Features. Here, the hole diameter of the non-through hole at the end of step (1) is 50 μm or less, and the hole diameter of the non-through hole at the end of step (2) is larger than the hole diameter of the non-through hole at the end of step (1). It is desirable that it is 10 to 40 μm larger. In addition, the maximum height Rz of the surface of the glass substrate at the end of the step (2) is desirably 5 μm or less. Further, step (1) may be performed by light irradiation using a CO ₂ laser. In addition, each of the through electrode and the wiring portion is independently a metal selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, A conductive material selected from the group consisting of an alloy selected from the group consisting of tin-copper, tin-bismuth, and tin-lead may be included.

  The method for manufacturing a printed circuit board according to the fifth embodiment of the present invention includes (4) a step of manufacturing a core substrate by any one of the first to third embodiments; and (5) a wiring step. (A) forming an insulating resin layer; (b) providing a via hole in the insulating resin layer to expose at least a part of the wiring portion immediately below the insulating resin layer formed in the sub-step (a); c) A conductive via in the via hole formed in the sub-step (b) and a wiring portion on the insulating resin layer formed in the sub-step (a) are formed, and the conductive via is formed in the sub-step (a). A wiring step carried out by electrically connecting the wiring portion immediately below the insulating resin layer formed in step 1 and the wiring portion on the insulating resin layer formed in the substep (a); (6) carried out immediately before Opening for exposing at least a part of the wiring part formed in sub-step (c) of step (5) Characterized in that it comprises a step of providing a surface insulating layer having. Here, the wiring step of step (5) may be repeated a plurality of times to form a plurality of insulating resin layers and wiring portions.

  The semiconductor device manufacturing method of the sixth embodiment of the present invention includes (7) a step of manufacturing a printed circuit board by the method of the fifth embodiment, and (8) a conductive pad in the opening of the surface insulating layer. And (9) fixing a semiconductor element on the conductive pad.

  By adopting the above configuration, the method of the present invention can form a through hole having a precisely controlled hole diameter in the glass substrate. Further, by eliminating the thermal strain region formed around the through-hole to be formed and the deposits (dross and nodules) on the glass substrate, the generation of microcracks in the glass substrate is suppressed, and the glass substrate It becomes possible to make the surface of the flat. As a result, the core substrate, the printed circuit board, and the wiring provided in the semiconductor device obtained by the method of the present invention have high reliability.

It is a figure which shows the thermal strain area | region at the time of forming a through-hole by the laser processing of a prior art, (a) is a photograph of an upper surface, (b) is sectional drawing. It is a figure which shows a microcrack and dross at the time of forming a through-hole by the laser processing of a prior art, (a) is a photograph of an upper surface, (b) is sectional drawing. It is a figure explaining 1 process of the manufacturing method of the core substrate of 1st Embodiment. It is a figure explaining 1 process of the manufacturing method of the core substrate of 1st Embodiment. It is a figure explaining 1 process of the manufacturing method of the core substrate of 1st Embodiment. It is a figure explaining 1 process of the manufacturing method of the core substrate of 1st Embodiment. It is a figure explaining 1 process of the manufacturing method of the core board | substrate of 2nd Embodiment. It is a figure explaining 1 process of the manufacturing method of the core board | substrate of 2nd Embodiment. It is a figure explaining 1 process of the manufacturing method of the core board | substrate of 2nd Embodiment. It is a figure explaining 1 process of the manufacturing method of the core board | substrate of 2nd Embodiment. It is a figure explaining 1 process of the manufacturing method of the core board | substrate of 2nd Embodiment. It is a figure explaining 1 process of the manufacturing method of the core substrate of 3rd Embodiment. It is a figure explaining 1 process of the manufacturing method of the core substrate of 3rd Embodiment. It is a figure explaining 1 process of the manufacturing method of the printed circuit board of 5th Embodiment. It is a figure explaining 1 process of the manufacturing method of the printed circuit board of 5th Embodiment. It is a figure explaining 1 process of the manufacturing method of the printed circuit board of 5th Embodiment. It is a figure explaining 1 process of the manufacturing method of the printed circuit board of 5th Embodiment. It is a figure explaining 1 process of the manufacturing method of the printed circuit board of 5th Embodiment. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 6th Embodiment. It is a figure explaining 1 process of the manufacturing method of the semiconductor device of 6th Embodiment.

[First Embodiment]
The manufacturing method of the core substrate of the first embodiment of the present invention includes (1) a step of forming a through hole in a glass substrate, and (2) an etching including hydrogen fluoride on the glass substrate obtained in step (1). A step of increasing the hole diameter of the through-hole by immersing in a liquid; and (3) forming a through-electrode in the through-hole and a wiring portion on the surface of the glass substrate. The wiring portion is electrically connected.

  In step (1), through-holes 12 are formed in the glass substrate 10 as shown in FIG. A thermal strain region 14 exists around the through hole 12. Although not shown, there is a possibility that dross exists on the surface of the glass substrate 10 around the through hole 12 and nodules exist on the surface of the glass substrate 10 away from the through hole 12. Moreover, although the case where two through-holes 12 are formed in FIG. 3, it goes without saying that three or more through-holes 12 may be formed.

The glass substrate 10 used in the step (1) has SiO ₂ as a main component. The glass substrate 10 can be formed using a low expansion glass having a linear expansion coefficient of 3 to 4 ppm / ° C., a soda glass having a linear expansion coefficient of 8 to 9 ppm / ° C., or the like. The linear expansion coefficient of the glass substrate 10 can be adjusted within a range of 3 to 9 ppm / ° C. by changing the production method or adding a metal component such as Na. The linear expansion coefficient can be measured by thermomechanical analysis (TMA) according to JIS R3102: 1995 for glass or JIS K7197: 2012 for plastic. Further, the glass substrate 10 has an arithmetic average roughness Ra of 10 nm or less before the through holes 12 are formed. The arithmetic average roughness Ra can be obtained by measurement with a stylus type film thickness meter according to JIS B0601: 2013, or by measurement with an optical microscope capable of depth of focus measurement. Moreover, it is desirable that the glass substrate 10 used in the step (1) has a thickness in the range of 50 μm to 700 μm.

Formation of the through hole 12 in the step (1) is performed by irradiating the glass substrate 10 with laser light. Lasers that can be used include CO ₂ lasers, UV lasers, picosecond lasers, femtosecond lasers, and the like. Considering the processing speed, the shape of the through-hole 12 to be formed, the cost of the apparatus, etc., it is preferable to use a CO ₂ laser. The laser beam irradiation for forming the through hole 12 may be performed from one surface of the glass substrate 10 or from both surfaces of the glass substrate 10.

For example, the through-hole 12 can be formed using a CO ₂ laser having a laser pulse width of 100 μs or less and a peak output of 7 kW or more. As the number of laser shots (number of pulses to be irradiated) used for processing increases, the width and amount of distortion of the thermal strain region 14 formed around the through-hole 12 tend to increase. In consideration of this point, when the through-hole 12 is formed using a laser, it is preferable that the diameter of the through-hole 12 is 100 μm or less, desirably 50 μm or less so that the number of shots of the laser is not increased.

  Alternatively, the through-hole 12 may be formed by using photosensitive glass as the glass substrate 10 and irradiating light having an appropriate wavelength. As a further alternative, the through holes 12 may be formed in the glass substrate 10 using blasting. When these methods are used, formation of the thermal strain region 14 formed around the through hole 12 can be prevented. However, since the problem that it is difficult to control the hole diameter of the through hole 12 still exists, it is desirable to control the hole diameter of the through hole 12 by performing etching in the step (2) described later.

  In the step (2), the glass substrate 10 having the through holes 12 obtained in the step (1) is immersed in an etchant containing hydrogen fluoride to remove the thermal strain region 14 as shown in FIG. The diameter of the through hole 12 is increased.

  The etching solution used in the step (2) is an aqueous solution containing hydrogen fluoride as a main component. The etchant may further include nitric acid or an additive for controlling the etch rate and / or etchant stability. The ratio of these components can be appropriately set in consideration of the desired etching amount, the time required for etching, and the like. In addition, the temperature of the etching solution when performing the step (2) can be appropriately set in consideration of a desired etching amount, a time required for etching, and the like. The etching amount can be controlled to about 1 μm by setting the etching conditions. Therefore, as an average value of the hole diameter, the etching method is easier to obtain a desired value than the laser processing method. For example, the step (2) may be performed using an aqueous solution containing 5% hydrogen fluoride at a temperature of 25 ° C.

  The etching amount in the step (2) removes the thermal strain region 14 formed in the step (1) completely, and the hole diameter of the through hole 12 after the completion of this step becomes the design value of the printed circuit board (interposer). Can be set as follows. Typically, the etching amount is set within a range of 10 μm to 40 μm. In other words, in the step (2), the hole diameter of the through hole 12 is expanded within a range of 20 μm to 80 μm.

  The average value of the diameters of the through holes 12 finally obtained in the step (2) is controlled with high accuracy by using the etching step. Therefore, in the method according to the present embodiment, the hole diameter of the through hole 12 can be strictly managed as compared to the formation of the through hole only by laser light irradiation.

  Further, in the step (2), dross and nodules on the surface of the glass substrate 10 are removed. Dross and nodules reduce the flatness of the surface of the glass substrate 10 and cause disconnection or short-circuiting of the wiring part and fluctuations in the film thickness and / or line width of the wiring part. Dross and nodules formed by reattaching molten glass on the surface have a higher dissolution rate in the etching solution than the dissolution rate of the glass substrate 10. Therefore, by performing etching under appropriate conditions, dross and nodules can be removed preferentially, and the flatness of the surface of the glass substrate 10 can be improved. The glass substrate 10 after the step (2) has preferably a maximum height Rz of 5 μm or less. The maximum height Rz can be obtained by measurement with a stylus-type film thickness meter according to JIS B0601: 2013, or measurement with an optical microscope capable of measuring the depth of focus.

  In the step (2), the surface of the glass substrate 10 is also etched to some extent, and the film thickness of the glass substrate is reduced. The reduction of the film thickness of the glass substrate 10 in this step is useful for manufacturing a core substrate having a smaller film thickness and a printed circuit board having a smaller film thickness formed using the core substrate.

  Next, in step (3), the through-electrode 20 in the through-hole 12 and the wiring part 30 on the surface of the glass substrate 10 are formed to obtain the core substrate 100. Step (3) can be performed using a subtractive method or a semi-additive method. First, the case where the subtractive method is used will be described.

  First, as shown in FIG. 5, a conductive material is attached to the inside of the through hole 12 and the surface of the glass substrate 10. The conductive material may be attached by, for example, attaching an inorganic adhesion layer (not shown) and subsequently attaching the conductive material. The inorganic adhesion layer improves the adhesion between the glass substrate 10 and the through electrode 20 and the wiring precursor 30 ′ (and the first wiring portion 30 a after patterning) made of a conductive material.

  The inorganic adhesion layer is selected from the group consisting of tin oxide, indium oxide, zinc oxide, nickel-phosphorus (Ni-P), chromium, chromium oxide, aluminum nitride, copper nitride, aluminum oxide, tantalum, titanium and copper 1 It can be formed of one or more materials. The inorganic adhesion layer may be a single layer or a laminated structure of layers of different materials (for example, chromium / copper or titanium / copper). Each of the constituent layers of the inorganic adhesive layer composed of a single layer and the inorganic adhesive layer composed of a plurality of layers may be formed of a single material, or two or more of the aforementioned materials (for example, tin oxide and indium oxide) May be included. In order to sufficiently improve the adhesion between the conductive material layer and the glass substrate 10, the thickness of the inorganic adhesion layer is preferably in the range of 0.1 μm to 1 μm, but is limited to that range. It is not something. The inorganic adhesion layer can be formed using any technique known in the art, such as a sputtering method or an electroless plating method.

  The conductive material is desirably a material having high adhesion to the inorganic adhesion layer and high electrical connection stability. Conductive materials that can be used are, for example, metals selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, tin-copper, An alloy selected from the group consisting of tin-bismuth and tin-lead.

  The through electrode 20 and the wiring precursor 30 ′ made of a conductive material can be formed by, for example, an electroless plating method or an electrolytic plating method. Here, the inorganic adhesion layer also functions as a seed layer for plating. As shown in FIG. 5, electroconductive plating may be performed under the condition of conformal plating, and a conductive material may be attached to the surface of the glass substrate 10 and the side walls of the through holes 12. Alternatively, electrolytic plating may be performed under the conditions of filled via plating so that the conductive material is attached to the surface of the glass substrate 10 and at the same time, the inside of the through hole 12 may be filled with the conductive material. The selection of conditions for conformal plating or filled via plating also depends on the aspect ratio of the through hole 12. The aspect ratio of the through hole 12 means the ratio of the height of the through hole 12 to the hole diameter of the through hole 12 (in this embodiment, the thickness of the glass substrate 10). Due to the recent increase in the density of semiconductor devices, it is required to reduce the hole diameter of the through hole 12, and the aspect ratio of the through hole 12 tends to increase. When the aspect ratio is 5 or more, there is a possibility that voids are generated inside the through holes 12 under the conditions of filled via plating. Therefore, when the aspect ratio of the through hole 12 is 5 or more, it is desirable to select the conformal plating conditions and form the through electrode 20 having a uniform film thickness. On the other hand, when the aspect ratio of the through-hole 12 is less than 5, filled via plating conditions can be selected to reduce the resistance of the through-electrode 20.

  Subsequently, as shown in FIG. 6, the wiring precursor 30 ′ formed on the surface of the glass substrate 10 is patterned to form the first wiring part 30 a, thereby obtaining the core substrate 100. When the inorganic adhesive layer having conductivity exists under the wiring precursor 30 ', the inorganic adhesive layer is patterned together with the wiring precursor 30'. The first wiring part 30 a is divided into a plurality of parts, and at least a part of the plurality of parts is electrically connected to the through electrode 20. The remaining portions of the plurality of portions that are not electrically connected to the through electrode 20 can be used, for example, as part of the wiring of a three-dimensional circuit, or can be used for mounting electronic components other than semiconductor elements. FIG. 6 shows a mode in which all the parts of the first wiring part 30 a are connected to any of the through electrodes 20. In the cross section shown in FIG. 6, it seems that the through electrode 20 in one through hole 12 is separated into two parts, but the through electrode 20 in one through hole 12 is integrated. It is a matter that can be easily understood by those skilled in the art.

  On the other hand, when the step (3) is performed by the semi-additive method, first, a patterned first resist layer (not shown) may be formed on the inorganic adhesion layer formed on the surface of the glass substrate 10. Good. The patterned resist layer has openings in the through holes 12 and the periphery thereof, and in regions where the first wiring portions 30a are to be formed. The conductive material can then be deposited by electroplating using the inorganic adhesion layer exposed in the opening of the resist layer as a seed layer. Electrolytic plating may be performed under conformal plating conditions or filled via plating conditions. Thereafter, the resist layer is removed and the inorganic adhesion layer not covered with the first wiring portion 30a is removed, whereby the through electrode 20 and the first wiring portion 30a having a desired pattern can be formed. The inorganic adhesion layer is removed by etching using a separately formed second resist layer (having a reverse pattern of the pattern of the first resist layer) as a mask, or etching using the first wiring portion 30a as a sacrificial mask. Can be implemented. When the inorganic adhesion layer is not conductive, the inorganic adhesion layer that is not covered by the first wiring part 30a may not be removed.

  Regarding the pattern continuous from the power connection terminal at the time of electrolytic plating, as another method, the inorganic adhesive layer formed on the surface of the glass substrate 10 may be patterned first. Next, a conductive material is attached by electrolytic plating having a pattern corresponding to the desired first wiring portion 30a on the surface of the glass substrate 10 and using an inorganic adhesion layer covering the side wall of the through hole 12 as a seed layer. Thus, the through electrode 20 and the first wiring portion 30a having a desired pattern can be formed. However, it is necessary to pay attention to an isolated pattern that cannot be electrically connected to the power supply connection terminal because electrolytic plating cannot be performed. Electrolytic plating may be performed under conformal plating conditions or filled via plating conditions.

  Optionally, a filling layer 40 that fills the voids in the through holes 12 may be formed. For example, the filling layer 40 that fills the voids in the through holes 12 is formed for the intermediate product shown in FIG. 5 in which the through electrodes 20 and the wiring precursors 30 ′ are formed and the voids exist in the through holes 12. be able to.

  The filling layer 40 can be formed using a conductive material. The conductive material that can be used to form the filling layer 40 is (a) a powder of a metal selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium, and tin, or tin-silver, tin -A powder of an alloy selected from the group consisting of silver-copper, tin-copper, tin-bismuth, and tin-lead, and (b) a resin binder. The filling layer 40 can be formed by filling the through hole 12 with a conductive material using a screen printing method, a dispenser, or the like. Here, the conductive material overflowing above the surface of the glass substrate 10 is preferably removed by a polishing process such as chemical mechanical polishing (CMP). At this time, it is preferable that excessive polishing of the filling layer material is prevented to prevent dishing (the surface of the filling layer 40 is recessed from the surface of the glass substrate 10). The dishing amount is preferably 1/2 or less of the gap of the conformal plating, and more preferably 1/4 or less of the gap of the conformal plating. For example, by using a polishing material containing silica, cerium oxide, alumina, hydrogen peroxide, and the like and polishing processing with the surface of the glass substrate 10 as an end point, the overflowing conductive material and the wiring precursor 30 on the surface of the glass substrate 10 are obtained. By removing ', an intermediate product (a so-called “flat state”) in which the surfaces of the glass substrate 10, the through electrode 20 and the filling layer 40 are coplanar can be obtained.

  Thereafter, by using the above-described procedure, the conductive material is attached to the surfaces of the glass substrate 10, the through electrode 20 and the filling layer 40, and the attached conductive material is patterned to form the first wiring portion 30a. Can do. In this case, the first wiring portion 30 a is connected to the upper and lower surfaces of the conductive filling layer 40 in addition to the upper and lower surfaces of the through electrode 20, thereby reducing the wiring resistance against the current that flows through the through hole 12. It is possible to make it.

  Alternatively, the through electrode 20 and the first wiring part 30a are formed, and the filling layer 40 that fills the voids in the through holes 12 is formed for the intermediate product shown in FIG. May be. In this case, the filling layer 40 is preferably formed using an insulating material such as a thermoplastic resin. The filling layer 40 can be formed by filling the through holes 12 with an insulating material using a screen printing method, a dispenser, or the like. Alternatively, in the fifth embodiment to be described later, the filling layer 40 may be formed by filling the through hole 12 with an insulating material simultaneously with the formation of the insulating resin layer 50.

[Second Embodiment]
The method for manufacturing a core substrate according to the second embodiment of the present invention includes (1) a step of providing insulating layers on both surfaces of the glass substrate, (2) forming openings in the insulating layer, and the glass substrate. A step of forming a through hole in the substrate, (3) a step of immersing the glass substrate obtained in step (2) in an etching solution containing hydrogen fluoride to increase the diameter of the through hole, and (4) the glass Forming a through-hole in the substrate and a through-electrode in the opening of the insulating layer, and a wiring portion on the surface of the insulating layer, and the through-electrode and the wiring portion are in electrical communication with each other Features.

  In step (1), insulating layers 16 are formed on both surfaces of the glass substrate 10 as shown in FIG. The insulating material for forming the insulating layer 16 includes at least one selected from the group consisting of an epoxy resin, a phenol resin, a polyimide resin, a polycycloolefin resin, and a polybenzoxazole (PBO) resin. The insulating material may further include an insulating inorganic filler such as silica (silicon oxide). The insulating material desirably has a higher linear expansion coefficient than the conductive material forming the wiring part 30 and a higher elastic modulus than the conductive material forming the wiring part 30. By having such a linear expansion coefficient and an elastic modulus, the stress applied between the wiring part 30 and the glass substrate 10 can be reduced, and peeling of the wiring part 30 can be prevented. The insulating material desirably has a linear expansion coefficient of, for example, 30 to 100 ppm / ° C.

  The insulating material may be in the form of a self-supporting dry film, or may be a liquid such as a solution, a dispersion, or an emulsion. When an insulating material in the form of a self-supporting dry film is used, the insulating layer 16 is formed by laminating the dry film on both surfaces of the glass substrate 10 using any technique known in the art. can do. In the case where a liquid insulating material is used, the insulating layer 16 is formed by applying an insulating material to both surfaces of the glass substrate 10 using any technique known in the art and drying it. Can do.

  In step (2), as shown in FIG. 8, the opening 18 is formed in the insulating layer 16, and at the same time, the through hole 12 is formed in the glass substrate 10 in the opening 18. A thermal strain region 14 exists around the through hole 12. Step (2) is preferably performed by laser light irradiation. The laser used and its irradiation conditions are the same as those described in the step (1) of the first embodiment. Since the insulating layer 16 exists on both surfaces of the glass substrate 10, laser light may be irradiated from both surfaces. In general, since the insulating material of the insulating layer 16 is more sensitive to laser light than the glass substrate, the opening 18 of the insulating layer 16 has a larger diameter than the through hole 12 of the glass substrate 10. Then, the thermal strain region 14 is exposed. In addition, smears (that is, resin residues) may be generated on the surface of the insulating layer 16 due to laser light irradiation. If necessary, smear generated on the surface of the insulating layer 16 may be removed by a desmear process using any means known in the art.

  In step (3), as shown in FIG. 9, the glass substrate 10 obtained in step (2) is immersed in an etchant containing hydrogen fluoride to increase the hole diameter of the through hole 12. Step (3) can be carried out in the same manner as step (2) of the first embodiment. In the present embodiment, the surface of the glass substrate 10 does not contact the etching solution except for the opening 18 of the insulating layer 16. Therefore, it is possible to suppress a decrease in the film thickness of the glass substrate 10 in this step.

  In FIG. 9, a state where the side wall of the opening 18 of the insulating layer 16 and the side wall of the through hole 12 of the glass substrate 10 are flush with each other (so-called “level” state) is shown. However, it is not necessary to match both side walls, and a step may exist between the side wall of the opening 18 and the side wall of the through hole 12. In the step (3), even if it exists, the step between the side wall of the opening 18 and the side wall of the through hole 12 is reduced, so that the step acts on the through electrode 20 obtained in the step (4). The stress can be reduced.

  In step (4), the through hole 12 of the glass substrate 10, the through electrode 20 in the opening 18 of the insulating layer 16, and the first wiring part 30a on the surface of the insulating layer 16 are formed. Also in the present embodiment, the first wiring part 30 a is divided into a plurality of parts, and at least a part of the plurality of parts of the first wiring part 30 a is electrically connected to the through electrode 20. Step (4) can be performed in the same manner as step (3) of the first embodiment. For example, first, as shown in FIG. 10, the through electrode 12 in the through hole 12 of the glass substrate 10 and the opening 18 of the insulating layer 16, and the wiring precursor 30 ′ on the surface of the insulating layer 16 are formed. Can be formed. Subsequently, the wiring precursor 30 ′ is patterned to form the first wiring part 30 a, and the core substrate 100 shown in FIG. 11 can be obtained.

  Furthermore, also in this embodiment, you may form the filling layer 40 which fills the space | gap in the through-hole 12 arbitrarily. The formation of the filling layer 40 can be performed by the means described in the first embodiment.

[Third Embodiment]
The method for manufacturing a core substrate according to the third embodiment of the present invention includes (1) a step of forming a non-through hole on one surface of a glass substrate, and (2) a step of hooking the glass substrate obtained in step (1). A step of increasing the hole diameter of the non-through hole by immersing in an etching solution containing hydrogen fluoride, and (3) polishing the other surface of the glass substrate obtained in step (2) to penetrate the non-through hole. A step of forming a hole, and (4) a step of forming a through electrode in the through hole and a wiring part on the surface of the glass substrate, and the through electrode and the wiring part are in electrical communication with each other It is characterized by.

  In step (1), as shown in FIG. 12, a non-through hole 12 ′ is formed in one surface 10 f of the glass substrate 10. The process (1) is performed in the same manner as the process (1) of the first embodiment, except that the processing is performed only from the surface 10f and the non-through hole 12 ′ is formed instead of the through hole 12. it can. In the present embodiment, the thermal strain region 14 is formed on the side wall and the bottom surface of the non-through hole 12 '.

  In step (2), as shown in FIG. 13, the thermal strain region 14 formed on the side wall and the bottom surface of the non-through hole 12 'is removed to increase the hole diameter of the non-through hole 12'. Step (2) can be carried out in the same manner as step (2) of the first embodiment. However, in the present embodiment, the other surface 10r of the glass substrate 10 may be exposed to the etching solution by immersing the glass substrate 10 in the etching solution, or the etching solution may be sprayed only on the surface 10f. The surface 10r may not be exposed to the etching solution using the means.

  In step (3), the surface 10r of the glass substrate 10 is polished so that the non-through hole 12 'becomes the through hole 12. The glass substrate 10 obtained in this step has the structure shown in FIG. This step can be performed using any means known in the art. For example, this process can be carried out using an abrasive containing cerium oxide under conditions that optimize the thickness of the glass substrate 10 and the diameter of the through-holes 12 obtained. What is necessary is just to select the polishing amount in this process suitably. By polishing even after the through-hole 12 is formed, it is possible to suppress the formation of a bowl-shaped “burr” on the surface 10r side of the through-hole 12 formed in this step. Further, at the end of this step, the arithmetic average roughness Ra of the surface (surface 10f and surface 10r) of the glass substrate 10 can be set to 10 nm or less.

  In the step (4), the core substrate 100 is obtained by forming the through electrode 20 in the through hole 12 and the first wiring part 30 a on the surface of the glass substrate 10. Step (4) can be performed in the same manner as step (3) of the first embodiment. The core substrate 100 obtained in this step has the structure shown in FIG.

[Fourth Embodiment]
The core substrate manufacturing method of the fourth embodiment of the present invention includes (1) a step of forming a non-through hole on one surface of a glass substrate, and (2) a glass substrate obtained in step (1). Dipping in an etching solution containing hydrogen fluoride to increase the diameter of the non-through hole, and simultaneously making the non-through hole a through hole; and (3) the through electrode in the through hole and the glass substrate surface Forming the wiring part, and the through electrode and the wiring part are in electrical communication with each other.

  In the present embodiment, in the etching process of the step (2) of the third embodiment, simultaneously with the removal of the thermal strain region 14, the non-through hole is converted into a through hole, and the polishing process of the step (3) is omitted. This is a modification of the third embodiment. Step (1) and step (3) of this embodiment can be carried out in the same manner as step (1) and step (4) of the third embodiment.

  In the step (2), an etching solution is applied to both surfaces (surface 10f and surface 10r) of the glass substrate 10 in which the non-through holes 12 'are formed, for example, by dipping. In this respect, this embodiment is different from the third embodiment in which an etching solution may be applied only to the surface 10f. As a result, etching from the bottom surface of the non-through hole 12 ′ and the surface 10 r of the glass substrate 10 proceeds to completely remove the bottom portion of the non-through hole 12 ′, thereby forming the through hole 12. Therefore, the etching amount set in the step (2) is set to 0.25 times or more the thickness of the glass substrate 10 on the bottom surface of the non-through hole 12 ′ at the end of the step (1).

  In this embodiment, since the process of polishing the surface 10r of the glass substrate (that is, the process (3) of the third embodiment) can be omitted, the manufacturing cost can be further reduced.

  In the core substrate 100 obtained by the methods of the first to fourth embodiments, since the diameter of the through electrode 20 is controlled more precisely, the interval (pitch) between adjacent through electrodes 20 can be reduced. It becomes. These effects are useful in that a printed circuit board, which will be described later, is adapted for mounting a semiconductor element having a plurality of highly integrated contacts.

  Further, the core substrate 100 obtained by the methods of the first to fourth embodiments does not have a thermal strain region that generates a microcrack that causes a failure. In addition, by eliminating dross and nodules on the surface of the glass substrate 10, steps and irregularities on the surface of the glass substrate 10 are reduced, and the flatness of the surface of the glass substrate 10 is improved. These effects are described in the following. In the printed circuit board, the uniformity of the line width, spacing and film thickness of the wiring part is improved, and the peeling and breakage of the wiring part due to the stress caused by heating and cooling are suppressed. Useful.

[Fifth Embodiment]
The method for manufacturing a printed circuit board according to the fifth embodiment of the present invention includes: (4) a step of manufacturing a core substrate by any one of the first to fourth embodiments; (5) a wiring step; 6) A step of providing a surface insulating layer having an opening exposing at least a part of the wiring portion formed in the sub-step (c) of the step (5) performed immediately before. The wiring step of step (5) includes (a) a sub-step of forming an insulating resin layer, (b) a wiring immediately below the insulating resin layer formed in sub-step (a) by providing a via hole in the insulating resin layer. A sub-step for exposing at least a part of the portion; (c) a conductive via in the via hole formed in the sub-step (b); and a wiring portion on the insulating resin layer formed in the sub-step (a) Then, the method includes a sub-process of electrically connecting the conductive via to the wiring portion immediately below the insulating resin layer and the wiring portion above the insulating resin layer. First, the case where the core substrate 100 obtained by the method of the first or third embodiment is used will be described with reference to FIGS.

  Step (5) is a wiring step for forming the insulating resin layer 50 and the wiring portion 30 on the core substrate 100. By repeating step (5) a plurality of times, the required number of insulating resin layers 50 and wiring portions 30 can be formed.

  The first sub-step (a) of the step (5) is a step for forming the insulating resin layer 50. As shown in FIG. 14, in the first step (5), in the sub-step (a), the insulating resin layers 50 are formed on both surfaces of the core substrate 100. On the other hand, in the second and subsequent steps (5), in the sub-step (a), the insulating resin layer 50 is formed so as to cover the insulating resin layer 50 and the wiring part 30 formed immediately before. FIG. 14 shows a case where the filling layer 40 that fills the through holes 12 of the glass substrate 10 is provided.

  The insulating resin layer 50 can be formed using an insulating material including at least one selected from the group consisting of an epoxy resin, a phenol resin, a polyimide resin, a polycycloolefin resin, and a PBO resin. The insulating material may further include an insulating inorganic filler such as silica (silicon oxide). Alternatively, the insulating resin layer may be formed using a negative or positive photosensitive insulating material. The insulating material may be in the form of a self-supporting dry film, or may be a liquid such as a solution, a dispersion, or an emulsion. When an insulating material in the form of a self-supporting dry film is used, the insulating resin layer 50 can be formed by laminating the dry film using any technique known in the art. When using a liquid insulating material, the insulating resin layer 50 can be formed by applying and drying the insulating material using any technique known in the art.

  Further, when there is a void in the through hole 12 of the glass substrate 10, the insulating filling layer 40 is formed simultaneously with the formation of the insulating resin layer 50 in the sub-step (a) of the first step (5). can do. For example, when the insulating resin layer 50 is formed using an insulating material in the form of a self-supporting dry film, the dry film is plastically deformed by applying an appropriate pressure in the vertical direction of the glass substrate 10 during lamination, The voids in the through holes 12 of the glass substrate 10 can be filled. Alternatively, when a liquid insulating material is used, by appropriately controlling the viscosity of the liquid insulating material and the wettability with respect to the side wall of the through-hole 12, the insulating material is retained in the gap and subsequently dried. Insulating filling layer 40 can be formed.

  The insulating materials 50 and 16 are higher in linear expansion coefficient than the conductive material forming the wiring portion 30 and higher than the conductive material forming the wiring portion 30, particularly when they are in direct contact with the glass substrate 10. It is desirable to have an elastic modulus. By having such a linear expansion coefficient and an elastic modulus, the stress applied between the wiring part 30 and the glass substrate 10 can be reduced, and peeling of the wiring part 30 can be prevented. The insulating material desirably has a linear expansion coefficient of 20 to 100 ppm / ° C., for example.

The second sub-step (b) of the step (5) is a step of forming the via hole 62 in the insulating resin layer 50 formed in the immediately preceding sub-step (a) as shown in FIG. The via hole 62 exposes a part of the wiring portion 30 (in FIG. 15, the first wiring portion 30a) that exists immediately below the insulating resin layer 50. For the sake of brevity, in the following description of the sub-steps (b) and (c), the wiring portion immediately below the insulating resin layer 50 is referred to as “first wiring portion 30a”. The means for forming the via hole 62 can be selected in consideration of the material of the insulating resin layer 50. When the insulating resin layer 50 is formed of a non-photosensitive resin such as an epoxy resin, a phenol resin, a polyimide resin, a polycycloolefin resin, or a PBO resin, the via hole 62 can be formed by laser light irradiation. Lasers that can be used include CO ₂ lasers, UV lasers, picosecond lasers, femtosecond lasers, and the like. In consideration of the processing speed, the shape of the via hole 62 to be formed, and the cost of the apparatus, it is preferable to use a CO ₂ laser. For example, the via hole 62 can be formed using a CO ₂ laser having a laser pulse width of 500 μs or less and a peak output of 2 kW or more. When smear is generated on the surface of the insulating resin layer 50 by the irradiation of the laser beam, a desmear process using any means known in the art may be performed. Alternatively, when the insulating resin layer 50 is formed of a photosensitive insulating material, the via hole 62 may be formed by a photolithography method (exposure and development) using any means known in the art. it can.

  In the third sub-step (c) of the step (5), the conductive via 60 in the via hole 62 formed in the sub-step (b) and the wiring portion 30 on the insulating resin layer 50 (in FIG. 15, A second wiring portion 30b). For the purpose of simplicity, in the following description of this sub-process, the wiring part 30 on the insulating resin layer 50 is referred to as a “second wiring part 30b”. The conductive via 60 formed in this step is electrically connected to the first wiring part 30a and the second wiring part 30b.

  As described in the step (3) of the first embodiment, the conductive via 60 and the second wiring portion 30b are (i) a step of forming an inorganic adhesion layer (not shown), and (ii) a seed of the inorganic adhesion layer. Forming a conductive via 60 and a wiring precursor (not shown) by conformal plating or filled via plating used as a layer; and (iii) patterning the wiring precursor and the inorganic adhesion layer to form the second wiring portion 30b. It can be formed by a subtractive method including a forming step. As another method, the conductive via 60 and the second wiring part 30b are formed by (i) a step of forming an inorganic adhesion layer (not shown), (ii) a step of forming a patterned resist layer on the surface of the inorganic adhesion layer, (iii) ) A step of forming the conductive via 60 and the second wiring part 30b by conformal plating or filled via plating using an inorganic adhesion layer not covered by the patterned resist layer as a seed layer; and (iv) a patterned resist. It can be formed by a semi-additive method including a step of removing the layer and the inorganic adhesion layer not covered with the second wiring part 30b. In each of the above two methods, when the inorganic adhesion layer does not have conductivity, the removal of the inorganic adhesion layer may be omitted.

  As still another method, the conductive via 60 and the second wiring part 30b include (i) a step of forming an inorganic adhesion layer (not shown), (ii) a step of forming a patterned resist layer on the surface of the inorganic adhesion layer, iii) a step of electroplating the opening of the resist layer, (iv) a step of removing the resist layer, (v) a step of removing the inorganic adhesion layer other than the wiring portion, and (vi) by conformal plating or filled via plating. The conductive via 60 and the second wiring part 30b can be formed by a method including a step.

  You may form the conduction | electrical_connection via 60 and the 2nd wiring part 30b by application | coating of the conductive paste containing a conductive metal, a binder, and a solvent, and heat processing. Conductive metals that can be used are metals selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, tin-copper, tin- Includes alloys selected from the group consisting of bismuth and tin-lead. Binders that can be used include any organic resin known in the art. Solvents that can be used include any organic solvent known in the art. The conductive paste can be applied using any means known in the art, such as a screen printing method or an ink jet method. The heat treatment of the conductive paste can be appropriately selected in consideration of the heat resistant temperature of each constituent layer constituting the printed circuit board. Typically, the heat treatment of the conductive paste is performed at a temperature in the range of 150 ° C to 180 ° C.

  As another method of the sub-step (c), the conductive via 60 and the second wiring part 30b may be formed separately. As described above, the conductive via 60 can be formed by a plating method under conformal plating conditions or filled via plating conditions, or by filling with a conductive paste. On the other hand, the second wiring portion 30b can be formed using a plating method, application of a conductive paste, or a dry film forming method such as a sputtering method or a vacuum evaporation method. The patterning of the second wiring part 30b may be performed using any means known in the art.

  In step (6), a surface insulating layer 70 having an opening 82 exposing a part of the wiring portion 30 is formed on the insulating resin layer 50 and the wiring portion 30 formed in the immediately preceding step (5). Thus, a printed circuit board 200 is obtained. 17 includes two layers of wiring portions 30 (first wiring portion 30a and second wiring portion 30b) and one insulating resin layer 50 on each surface of the glass substrate 10, and includes the insulating resin layer 50 and the conductive via 60. In addition, a configuration example in which the surface insulating layer 70 is formed on the second wiring portion 30b is shown.

  In consideration of the possibility of using solder when attaching the printed circuit board 200 to the package substrate and / or attaching the semiconductor element to the wired circuit board 200, the surface insulating layer 70 is made of solder material and solder. It is desirable to have resistance to the attaching process. The material for forming the surface insulating layer 70 includes any solder resist known in the art.

  The surface insulating layer 70 covers both surfaces of the intermediate product shown in FIG. 16 so as to completely cover the insulating resin layer 50, the conductive via 60 and the wiring part 30 formed in the step (5) performed immediately before. The opening 82 is formed so as to be covered with 70 material and subsequently expose at least a part of the uppermost wiring portion 30 (second wiring portion 30b in FIG. 16). The covering of the intermediate product and the formation of the opening 82 can be performed using any means known in the art. For example, the intermediate product may be coated using a general coating method such as spin coating, roll coating, spray coating, or the like. The opening 82 may be formed using laser light irradiation, etching (dry or wet), or the like. When the material of the surface insulating layer 70 has photosensitivity, the opening 82 can be formed by photolithography (exposure and development).

  When the core substrate 100 manufactured in the second embodiment is used in the present embodiment, the sub-step (a) of the first step (5) is performed on the insulating layer 16 that is the outermost layer of the core substrate 100. Except for this, a procedure similar to the above can be used. FIG. 18 shows a configuration example of a printed circuit board 200 formed using the core substrate 100 manufactured in the second embodiment. The configuration shown in FIG. 18 is shown in FIG. 17 except that the insulating layer 16 exists on both surfaces of the glass substrate 10 and the through electrode 20 is formed through the glass substrate 10 and the two insulating layers 16. The configuration is the same.

  Since the integration degree of the through electrode 20 in the core substrate 100 is improved, the printed circuit board 200 obtained by the method of the present embodiment is suitable for mounting a semiconductor element having a plurality of contacts with a high integration degree.

  Further, by improving the flatness of the surface of the core substrate 100, the uniformity of the line width, the interval, and the film thickness of the wiring portion in the printed circuit board 200 obtained by the method of the present embodiment is improved. As a result, it is possible to suppress the separation and breakage of the wiring portion due to the stress caused by heating and cooling. Therefore, the printed circuit board 200 obtained by the method of the present embodiment can realize high conduction reliability.

[Sixth Embodiment]
A method for manufacturing a semiconductor device according to a sixth embodiment of the present invention includes: (7) a step of manufacturing a printed circuit board by the method of the fifth embodiment; and (8) a conductive pad in the opening of the surface insulating layer. And (9) fixing a semiconductor element on the conductive pad.

  In step (8), the conductive pad 80 is formed as shown in FIG. 19 by filling the openings of the printed circuit board 200 shown in FIG. 17 with a conductive material. The same applies to the printed circuit board 200 shown in FIG. The filling of the conductive material can be performed using any means known in the art.

  In step (9), the semiconductor element 310 is fixed on the conductive pad 80. More specifically, the conductive pad 80 and the contact point of the semiconductor element 310 are connected. This step can be performed using, for example, a solder ball (not shown) or a conductive bump (not shown) provided on the semiconductor element 310 or the conductive pad 80. Further, an adhesive (not shown) may be applied to a region other than the contacts of the semiconductor element 310 for the purpose of securely fixing the semiconductor element 310.

  FIG. 20 shows a configuration example of the semiconductor device obtained in this embodiment. In the configuration shown in FIG. 20, the semiconductor device 300 having a configuration in which the semiconductor element 310 is fixed to one surface of the printed circuit board 200 and the other surface is connected to a package substrate (not shown) is shown. Therefore, FIG. 20 shows a configuration in which conductive bumps 90 for facilitating connection to the package substrate are provided on the surface opposite to the surface on which the semiconductor element 310 is fixed. In addition to the semiconductor element 310, other electronic components such as a resistance element, an inductance element, and a capacitor may be fixed to the printed circuit board 200. Further, when a plurality of semiconductor elements and electronic components are fixed to one wiring circuit board 200, a part of the plurality of semiconductor elements and electronic components is fixed to one surface of the wiring circuit board 200, and the other side of the wiring circuit board 200 is fixed. In this aspect, a configuration in which a plurality of semiconductor elements and some of the electronic components are fixed and at the same time connected to the package substrate may be employed.

  The semiconductor device 300 obtained by the method of the present embodiment can use the semiconductor element 310 having a plurality of contacts with a high degree of integration, and the wiring circuit board 200 has high conduction reliability. Can be reduced. Further, since the glass substrate 10 on which the through electrode 20 is formed has a linear expansion coefficient comparable to that of the semiconductor element 310, the generation of stress due to a dimensional change can be suppressed even when the temperature of the semiconductor device 300 rises. . Therefore, since there is a low possibility that a failure such as disconnection or peeling occurs during use, the semiconductor device 300 obtained by the method of this embodiment can achieve high reliability.

Example 1
This example relates to a method of manufacturing a core substrate of the first embodiment, a method of manufacturing a printed circuit board of the fifth embodiment using the obtained core substrate, and the semiconductor device of the sixth embodiment. It relates to a manufacturing method.

  As the glass substrate 10, a low expansion glass having dimensions of length × width × thickness of 200 × 200 × 0.3 mm was prepared. The glass substrate 10 had an arithmetic average roughness Ra of 10 nm and a linear expansion coefficient of 3.8 ppm / ° C.

A CO ₂ laser was irradiated from one surface of the glass substrate 10 to form a through hole 12 as shown in FIG. In this example, 100 through holes arranged in a square matrix of 10 rows and 10 columns were formed. The distance between adjacent rows and the distance between adjacent columns was 500 μm. The pulse width of the CO ₂ laser used was 50 μs, the peak output was 7 kW, and the number of shots was 6. The through hole 12 had a hole diameter of 30 μm on the surface irradiated with the CO ₂ laser, and had a hole diameter of 20 μm on the opposite surface. Both surfaces of the glass substrate 10 before the etching treatment had a maximum height Rz of 6 μm. At this time, the ratio of the number of through-holes in which microcracks occurred around the total number of formed through-holes was measured to evaluate the occurrence of microcracks.

Subsequently, the glass substrate 10 in which the through holes 12 were formed was etched by being immersed in an aqueous solution containing 3% hydrogen fluoride and having a temperature of 25 ° C. The etching amount was set to 20 μm. As shown in FIG. 4, the through-hole 12 of the glass substrate 10 after etching had a hole diameter of 70 μm on the surface irradiated with the CO ₂ laser, and a hole diameter of 60 μm on the opposite surface. Further, both surfaces of the glass substrate 10 after the etching treatment had a maximum height Rz of 3 μm. From this result, it can be seen that dross and nodules on the surface of the glass substrate 10 generated by the laser light irradiation can be efficiently removed.

  Next, a sputtering method is used to form a Ti layer having a film thickness of 50 nm and a Cu layer having a film thickness of 300 nm on both surfaces of the glass substrate 10 and the side walls of the through-holes 12. An adhesion layer (not shown) was formed. Subsequently, a Cu film having a film thickness of 5 μm was deposited by electrolytic plating under conformal plating conditions using the obtained inorganic adhesion layer as an electrode on the deposition side, and as shown in FIG. The through electrode 20 was formed, and a wiring precursor 30 ′ was formed on both surfaces of the glass substrate 10.

  Next, the laminated structure of the inorganic adhesion layer and the wiring precursor 30 ′ on both surfaces of the glass substrate 10 is patterned using a photolithography method to form the first wiring part 30 a having a film thickness of 4 μm. A core substrate 100 shown in FIG. 6 was obtained. The patterning was performed under the condition that the first wiring part 30a having an L / S value of 20 μm / 20 μm was obtained. The actually obtained first wiring part 30a had an L / S value of 20 ± 0.5 μm / 20 ± 0.5 μm.

  Subsequently, an ABF-GXT31 dry film (manufactured by Ajinomoto Fine Techno Co., Ltd.) made of an epoxy resin and having a film thickness of 12.5 μm is laminated on both surfaces of the core substrate 100, and as shown in FIG. A resin layer 50 was formed. At this time, the pressure in the vertical direction of the glass substrate 10 is applied to the dry film to plastically deform the dry film to fill the voids remaining in the through-holes 12, and the insulating filling layer 40 is formed. Obtained.

  Next, the insulating resin layer 50 was irradiated with UV-YAG laser light to form via holes 62 penetrating the insulating resin layer 50 as shown in FIG. The via hole 62 had a hole diameter of 20 μm. Next, formation of an inorganic adhesion layer (not shown), formation of a Cu layer by electrolytic plating under filled via plating conditions, and patterning of the inorganic adhesion layer and the Cu layer on the surface of the insulating resin layer 50 are performed, as shown in FIG. As shown, the conductive via 60 and the second wiring part 30b were formed.

  Subsequently, a photosensitive solder resist was applied so as to cover the insulating resin layer 50 and the second wiring part 30b. Further, pattern exposure and development were performed on the photosensitive solder resist film to form an opening 82 that exposes a part of the second wiring part 30b, thereby obtaining a printed circuit board 200 shown in FIG. About the obtained printed circuit board, the thermal shock test (TST) based on JEDEC JESD22-A106B and C was implemented, and the incidence rate of disconnection was measured. TST was performed by performing 400 heating and cooling cycles with a maximum temperature of 125 ° C. and a minimum temperature of −55 ° C. The incidence of disconnection after TST was less than 20%.

  The second wiring part 30b exposed in the opening 82 is subjected to Ni electroless plating, Pt electroless plating, and Au electroless plating on the seed layer, and NiPtAu is formed in the opening 82 as shown in FIG. A conductive pad 80 made of a laminated film was formed. Finally, the semiconductor element 310 was fixed to the conduction pad 80 using solder, and the semiconductor device 300 shown in FIG. 20 was obtained.

(Example 2)
This example relates to a method for manufacturing the core substrate of the second embodiment, a method for manufacturing the printed circuit board of the fifth embodiment using the obtained core substrate, and the semiconductor device of the sixth embodiment. It relates to a manufacturing method.

  As the glass substrate 10, a low expansion glass having dimensions of length × width × thickness of 200 × 200 × 0.3 mm was prepared. The glass substrate 10 had an arithmetic average roughness Ra of 10 nm and a linear expansion coefficient of 3.8 ppm / ° C.

  ABF-GXT31 dry film (Ajinomoto Fine Techno Co., Ltd.) made of epoxy resin and laminated on both surfaces of the glass substrate 10 is laminated to form an insulating layer 16 as shown in FIG. did.

The CO ₂ laser was irradiated from both surfaces of the glass substrate 10 to form the opening 18 of the insulating layer 16 and the through hole 12 of the glass substrate 10 as shown in FIG. Similar to Example 1, 100 through holes arranged in a square matrix of 10 rows and 10 columns were formed. The distance between adjacent rows and the distance between adjacent columns was 500 μm. The pulse width of the CO ₂ laser used was 50 μs, the peak output was 7 kW, and the number of shots was 8. The opening of the insulating layer 16 had a hole diameter of 50 μm on the outer surface and a hole diameter of 40 μm at the interface with the glass substrate 10. Further, the through hole 12 of the glass substrate 10 had a hole diameter of 30 μm on the surface irradiated with the CO ₂ laser, and had a hole diameter of 20 μm on the opposite surface. Both surfaces of the insulating layer 16 before the etching treatment had a maximum height Rz of 6 μm. Further, in the same manner as in Example 1, the occurrence of microcracks was evaluated.

Subsequently, the intermediate product shown in FIG. 8 was immersed in an aqueous solution containing 3% hydrogen fluoride and having a temperature of 25 ° C. to perform etching. The etching amount was set to 10 μm. As shown in FIG. 9, the through hole 12 of the glass substrate 10 after etching had a hole diameter of 50 μm on the surface irradiated with the CO ₂ laser, and had a hole diameter of 40 μm on the opposite surface. Further, the surface of the insulating layer 16 after the etching treatment on the side irradiated with the CO ₂ laser had a maximum height Rz of 6 μm. From this result, it can be seen that nodules generated by laser light irradiation and scattered on the surface of the insulating layer 16 could be efficiently removed.

  Next, a sputtering method is used to form a Ti layer having a thickness of 50 nm and a Cu layer having a thickness of 300 on both surfaces of the insulating layer 16 and the sidewalls of the opening 18 and the through-hole 12. An inorganic adhesion layer (not shown) consisting of two layers was formed. Subsequently, a Cu film having a film thickness of 5 μm was deposited by electrolytic plating under conformal plating conditions using the obtained inorganic adhesion layer as an electrode on the deposition side, and as shown in FIG. A through electrode 20 was formed in the hole 12. A Cu film was also formed on the surfaces of the two insulating layers 16.

  Subsequently, a mixed resin material of silicon oxide and epoxy resin was screen-printed in the opening 18 of the insulating layer 16 and the void in the through hole 12 of the glass substrate 10 to form the filling layer 40. Subsequently, the CMP method using a slurry containing cerium oxide, hydrogen peroxide, and silica removes the filling layer protruding from the surface of the insulating layer 16, the inorganic adhesion layer on the surface of the insulating layer 16, and the Cu film, and insulating The surfaces of the layer 16 and the filling layer 40 were flattened.

  Next, the 1st wiring part 30a was formed by the semi-additive method shown below. A Ti layer having a thickness of 50 nm and a Cu layer having a thickness of 300 were formed on the surfaces of the insulating layer 16 and the filling layer 40, and an inorganic adhesion layer (not shown) composed of two layers was formed. A resist film (not shown) having an opening corresponding to a wiring pattern having an L / S value of 20 μm / 20 μm was formed on the inorganic adhesion layer. A first wiring portion 30a having a thickness of 4 μm was formed by electroplating using the exposed inorganic adhesion layer as a seed layer. Subsequently, the resist film was removed, and the portion of the inorganic adhesion layer that was not covered with the first wiring portion 30a was removed, and the core substrate 100 having the filling layer 40 was obtained. The actually obtained first wiring part 30a had an L / S value of 20 ± 0.5 μm / 20 ± 0.5 μm.

  Subsequently, an ABF-GXT31 dry film (Ajinomoto Fine Techno Co., Ltd.) made of an epoxy resin and having a thickness of 12.5 μm was laminated on both surfaces of the core substrate 100 to form an insulating resin layer 50.

  Next, the via-hole 62 penetrating the insulating resin layer 50 was formed by irradiating the insulating resin layer 50 with UV-YAG laser light. The via hole 62 had a hole diameter of 20 μm. Next, formation of an inorganic adhesion layer (not shown), formation of a Cu layer by electrolytic plating under filled via plating conditions, and patterning of the inorganic adhesion layer and the Cu layer on the surface of the insulating resin layer 50 are performed, as shown in FIG. As shown, the conductive via 60 and the second wiring part 30b were formed.

  Subsequently, a photosensitive solder resist was applied so as to cover the insulating resin layer 50 and the second wiring part 30b. Furthermore, pattern exposure and development were performed on the photosensitive solder resist film to form an opening 82 that exposes a part of the second wiring portion 30b, thereby obtaining a printed circuit board 200 shown in FIG. TST was performed on the obtained printed circuit board in the same manner as in Example 1. The incidence of disconnection after TST was less than 20%.

  Ni electroless plating, Pt electroless plating, and Au electroless plating were applied to the second wiring part 30 b exposed in the opening 82, and a conductive pad 80 made of a NiPtAu laminated film was formed in the opening 82. Finally, the semiconductor element 310 was fixed to the conduction pad 80 using solder, and the semiconductor device 300 was obtained.

(Example 3)
This example relates to a method of manufacturing a core substrate of the third embodiment, a method of manufacturing a printed circuit board of the fifth embodiment using the obtained core substrate, and the semiconductor device of the sixth embodiment. It relates to a manufacturing method.

  As the glass substrate 10, a low expansion glass having dimensions of length × width × thickness of 200 × 200 × 0.4 mm was prepared. The glass substrate 10 had an arithmetic average roughness Ra of 10 nm and a linear expansion coefficient of 3.8 ppm / ° C.

A CO ₂ laser was irradiated from the one surface 10f side of the glass substrate 10 to form a non-through hole 12 ′ as shown in FIG. 100 non-through holes arranged in a square matrix of 10 rows and 10 columns were formed. The distance between adjacent rows and the distance between adjacent columns was 500 μm. The pulse width of the CO ₂ laser used was 50 μs, the peak output was 7 kW, and the number of shots was 8. The non-through hole 12 ′ had a hole diameter of 30 μm on the surface irradiated with the CO ₂ laser and a depth of 0.35 mm. Both surfaces of the glass substrate 10 before the etching treatment had a maximum height Rz of 6 μm. Further, in the same manner as in Example 1, the occurrence of microcracks was evaluated.

Subsequently, the glass substrate 10 having the non-through holes 12 ′ formed therein was etched by being immersed in an aqueous solution containing 3% hydrogen fluoride and having a temperature of 25 ° C. The etching amount was set to 20 μm. As shown in FIG. 13, the non-through hole 12 ′ of the glass substrate 10 after the etching had a hole diameter of 70 μm on the surface irradiated with the CO ₂ laser and a depth of 0.35 mm. Moreover, the glass substrate 10 after etching had a thickness of 0.36 mm. Furthermore, both surfaces of the glass substrate 10 after the etching treatment had a maximum height Rz of 3 μm. From this result, it can be seen that dross and nodules on the surface of the glass substrate 10 generated by the laser light irradiation can be efficiently removed.

  Next, the other surface 10r of the glass substrate 10 was polished using an abrasive mainly composed of cerium oxide, and the non-through holes 12 'were converted into the through holes 12. The obtained glass substrate having the through hole 12 had the form shown in FIG.

  Next, the through electrode 20 and the first wiring part 30a were formed by the semi-additive method described below. A Ti layer having a thickness of 50 nm and a Cu layer having a thickness of 300 were formed on the surface of the glass substrate 10 and on the side wall of the through-hole 12 to form an inorganic adhesion layer (not shown) composed of two layers. . A resist film (not shown) having an opening corresponding to a wiring pattern having an L / S value of 20 μm / 20 μm was formed on the inorganic adhesion layer. The through electrode 20 having a thickness of 5 μm and the first wiring part 30 a having a thickness of 4 μm were formed by electroplating using the exposed inorganic adhesion layer as a seed layer. Subsequently, the resist film was removed, and the portion of the inorganic adhesion layer that was not covered with the first wiring portion 30a was removed, and the core substrate 100 shown in FIG. 6 was obtained. The actually obtained first wiring part 30a had an L / S value of 20 ± 0.5 μm / 20 ± 0.5 μm.

  Thereafter, the insulating resin layer 50, the conductive via 60, the second wiring portion 30b, the surface insulating layer 70, and the opening 82 of the surface insulating layer 70 are formed by the same procedure as in Example 1, and the wiring circuit shown in FIG. A substrate 200 was obtained. TST was performed on the obtained printed circuit board in the same manner as in Example 1. The incidence of disconnection after TST was less than 20%.

  Furthermore, the conductive pad 80 was formed and the semiconductor element 310 was fixed by the same procedure as in Example 1, and the semiconductor device 300 shown in FIG. 20 was obtained.

Example 4
This example relates to a method of manufacturing the core substrate of the fourth embodiment, a method of manufacturing the printed circuit board of the fifth embodiment using the obtained core substrate, and the semiconductor device of the sixth embodiment. It relates to a manufacturing method.

  As the glass substrate 10, a low expansion glass having dimensions of length × width × thickness of 200 × 200 × 0.4 mm was prepared. The glass substrate 10 had an arithmetic average roughness Ra of 10 nm and a linear expansion coefficient of 3.8 ppm / ° C.

A CO ₂ laser was irradiated from the one surface 10f side of the glass substrate 10 to form a non-through hole 12 ′ as shown in FIG. 100 non-through holes arranged in a square matrix of 10 rows and 10 columns were formed. The distance between adjacent rows and the distance between adjacent columns was 500 μm. The pulse width of the CO ₂ laser used was 50 μs, the peak output was 7 kW, and the number of shots was 8. The non-through hole 12 ′ had a hole diameter of 30 μm on the surface irradiated with the CO ₂ laser and a depth of 0.38 mm. Both surfaces of the glass substrate 10 before the etching treatment had a maximum height Rz of 6 μm. Further, in the same manner as in Example 1, the occurrence of microcracks was evaluated.

Subsequently, the glass substrate 10 having the non-through holes 12 ′ formed therein was etched by being immersed in an aqueous solution containing 3% hydrogen fluoride and having a temperature of 25 ° C. The etching amount was set to 20 μm. The glass substrate 10 after etching had a thickness of 0.36 mm. A non-through hole 12 ′ of the glass substrate 10 before etching shown in FIG. 12 penetrates the glass substrate 10 to become a through hole 12 shown in FIG. The obtained through-hole 12 had a hole diameter of 9070 μm on the surface irradiated with the CO ₂ laser. Furthermore, both surfaces of the glass substrate 10 after the etching treatment had a maximum height Rz of 3 μm. From this result, it can be seen that dross and nodules on the glass surface 10 generated by laser light irradiation could be removed efficiently.

  Next, the through electrode 20 and the first wiring part 30a were formed by the same procedure as in Example 3 to obtain the core substrate 100 shown in FIG. Here, the design value of the L / S value of the first wiring part 30a was set to 20 μm / 20 μm. The actually obtained first wiring part 30a had an L / S value of 20 ± 0.5 μm / 20 ± 0.5 μm.

  Thereafter, the insulating resin layer 50, the conductive via 60, the second wiring portion 30b, the surface insulating layer 70, and the opening 82 of the surface insulating layer 70 are formed by the same procedure as in Example 1, and the wiring circuit shown in FIG. A substrate 200 was obtained. TST was performed on the obtained printed circuit board in the same manner as in Example 1. The incidence of disconnection after TST was less than 20%.

  Furthermore, the conductive pad 80 was formed and the semiconductor element 310 was fixed by the same procedure as in Example 1, and the semiconductor device 300 shown in FIG. 20 was obtained.

(Comparative Example 1)
The present embodiment relates to a conventional core substrate manufacturing method, a printed circuit board manufacturing method using the obtained core substrate, and a semiconductor device manufacturing method.

  As the glass substrate, low expansion glass having a size of length × width × thickness of 200 × 200 × 0.3 mm was prepared. The glass substrate had an arithmetic average roughness Ra of 10 nm and a linear expansion coefficient of 3.8 ppm / ° C.

A through hole was formed by irradiating a CO ₂ laser from one surface of the glass substrate. The pulse width of the CO ₂ laser used was 50 μs, the peak output was 7 kW, and the number of shots was 6. The through hole 12 had a hole diameter of 70 μm on the surface irradiated with the CO ₂ laser, and had a hole diameter of 50 μm on the opposite surface. Both surfaces of the glass substrate 10 before the etching treatment had a maximum height Rz of 6 μm. Further, in the same manner as in Example 1, the occurrence of microcracks was evaluated.

  Next, a sputtering method is used to form a Ti layer having a thickness of 50 nm and a Cu layer having a thickness of 300 on the surface of the glass substrate 10 and on the sidewalls of the through-holes 12 to form an inorganic layer composed of two layers. An adhesion layer (not shown) was formed. A resist film (not shown) having an opening corresponding to a desired wiring pattern was formed on the inorganic adhesion layer. The through electrode 20 having a thickness of 5 μm and the first wiring part 30 a having a thickness of 6 μm were formed by electrolytic plating using the exposed inorganic adhesion layer as a seed layer. Subsequently, the resist film was removed and the portion of the inorganic adhesion layer that was not covered with the first wiring portion was removed to obtain a core substrate. Here, the design value of the L / S value of the first wiring part 30a was set to 20 μm / 20 μm. The actually obtained first wiring part 30a had an L / S value of 20 ± 2 μm / 20 ± 2 μm.

  Thereafter, an insulating resin layer, a conductive via, a second wiring portion, a surface insulating layer, and an opening portion of the surface insulating layer were formed by the same procedure as in Example 1 to obtain a printed circuit board.

  Further, a conductive pad was formed and a semiconductor element was fixed in the same procedure as in Example 1, thereby obtaining a semiconductor device.

(Evaluation)
The evaluation results of Examples 1 to 4 and Comparative Example 1 are shown in Table 1.

  Regarding the microcrack occurrence rate when the through-hole 12 is formed, it can be seen that in Examples 1 to 4 according to the method of the present invention, the occurrence of microcracks could be effectively suppressed. On the other hand, in Comparative Example 4 in which the heat strain region was not removed after the formation of the through hole, a high microcrack generation rate was obtained. The length of the largest microcrack generated in the glass substrate of Comparative Example 4 reached 20 μm. From this result, it was found that etching removal of the thermal strain region 14 after the formation of the through hole 12 is very effective for suppressing microcracks.

  Further, from the comparison of the maximum height Ra of the glass substrate or the glass substrate having an insulating layer formed on both sides, in Examples 1 to 4 according to the method of the present invention, the maximum height Rz is small, and dross and nodules on the surface Was found to be almost nonexistent. On the other hand, the glass substrate of Comparative Example 4 has a large maximum height Rz, and it can be seen that there are a large number of dross and / or nodules. From these comparisons, it has been found that the etching process after the formation of the through hole 12 is also effective in removing dross and nodules.

  Furthermore, in Examples 1 to 4 according to the present invention, the wiring part (first wiring part 30a) formed on the glass substrate or the insulating layer has a line width and an interval with a high accuracy of ± 0.5 μm with respect to the design value. Had. On the other hand, in Comparative Example 1, the variation in the line width and interval of the wiring portion increased to ± 2 μm. This result is considered to be because dross and / or nodules were removed by the etching process after the through-hole 12 was formed, and the flatness of the surface forming the wiring portion was improved.

  And by controlling the line width of the wiring part with high accuracy, the reliability of the wiring circuit board and the semiconductor device using the wiring circuit board could be improved. Specifically, in the wired circuit boards of Examples 1 to 4 according to the present invention, the disconnection rate after TST could be reduced to 20% or less. In addition, when the wired circuit board of Examples 1-4 after TST was observed, many disconnections are caused by breakage of the through electrodes, and disconnections of the wiring portions formed on the glass substrate or the insulating layer are almost not. I found that there was no. From this, it can be seen that the improvement of the flatness of the surface on which the wiring portion is formed by the etching process and the prevention of the occurrence of microcracks contribute to the improvement of the reliability of the wiring circuit board and the semiconductor device. Furthermore, in the printed circuit board of Examples 1-4, it turned out that the edge in the upper end and lower end of a through-hole is gentle curved surface shape (what is called chamfered state) by an etching process. The shape of the edge described above is considered to suppress the concentration of stress on the through electrode and the wiring portion at the upper and lower ends of the through hole, and it is considered that further improvement in reliability can be realized. On the other hand, the disconnection rate after TST of the printed circuit board of Comparative Example 1 is 20 to 40%, and in addition to the disconnection of the wiring portion formed on the surface of the glass substrate, the upper end and the lower end of the through hole Disconnection of the through electrode and the wiring part was observed. This result is considered to be due to the low flatness of the glass substrate surface and the occurrence of stress concentration at the upper and lower ends of the through holes.

DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Through-hole 3 Thermal strain area | region 4 Micro crack 5 Dross 10 Glass substrate 10f One surface of a glass substrate 10r The other surface of a glass substrate 12 Through-hole 12 'Non-through-hole 14 Thermal-strain area | region 16 Insulating layer 18 Opening part 20 through electrode 30 (a, b) (first, second) wiring portion 30 ′ wiring precursor 40 filling layer 50 insulating resin layer 60 conductive via 62 via hole 70 surface insulating layer 80 conductive pad 90 conductive bump 82 opening 100 Core substrate 200 Wiring circuit substrate 300 Semiconductor device 310 Semiconductor element

Claims (26)

(1) forming a through hole in a glass substrate;
(2) A step of immersing the glass substrate obtained in the step (1) in an etching solution containing hydrogen fluoride to increase the diameter of the through hole;
(3) including a step of forming a through electrode in the through hole and a wiring portion on a surface of the glass substrate, wherein the through electrode and the wiring portion are in electrical communication with each other A method for manufacturing a substrate.   The hole diameter of the through hole at the end of the step (1) is 50 μm or less, and the hole diameter of the through hole at the end of the step (2) is 10 to 40 μm larger than the hole diameter of the through hole at the end of the process (1). The method for manufacturing a core substrate according to claim 1, wherein:   2. The core substrate manufacturing method according to claim 1, wherein the maximum height Rz of the surface of the glass substrate at the end of the step (2) is 5 μm or less. The method of manufacturing a core substrate according to claim 1, wherein the step (1) is performed by light irradiation using a CO ₂ laser.   Each of the through electrode and the wiring part is independently a metal selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, 2. The method for manufacturing a core substrate according to claim 1, comprising a conductive material selected from the group consisting of an alloy selected from the group consisting of tin-copper, tin-bismuth, and tin-lead. (1) providing an insulating layer on both surfaces of the glass substrate;
(2) forming an opening in the insulating layer and forming a through hole in the glass substrate;
(3) immersing the glass substrate obtained in the step (2) in an etching solution containing hydrogen fluoride to increase the diameter of the through hole;
(4) forming a through hole in the glass substrate and a through electrode in the opening of the insulating layer, and a wiring part on the surface of the insulating layer, wherein the through electrode and the wiring part are in electrical communication with each other A method for manufacturing a core substrate, characterized in that:   The core according to claim 6, wherein the insulating layer includes at least one selected from the group consisting of an epoxy resin, a phenol resin, a polyimide resin, a polycycloolefin resin, and a polybenzoxazole (PBO) resin. A method for manufacturing a substrate.   The method of manufacturing a core substrate according to claim 7, wherein the insulating layer further includes an inorganic filler.   The diameter of the through hole at the end of the step (2) is 50 μm or less, and the diameter of the through hole at the end of the step (3) is 10 to 40 μm larger than the diameter of the through hole at the end of the step (2). The method for manufacturing a core substrate according to claim 6, wherein   The method for manufacturing a core substrate according to claim 6, wherein the maximum height Rz of the surface of the insulating layer at the end of step (3) is 5 μm or less. The method for manufacturing a core substrate according to claim 6, wherein the step (2) is performed by light irradiation using a CO ₂ laser.   Each of the through electrode and the wiring part is independently a metal selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, The method for manufacturing a core substrate according to claim 6, comprising a conductive material selected from the group consisting of an alloy selected from the group consisting of tin-copper, tin-bismuth, and tin-lead. (1) forming a non-through hole on one surface of the glass substrate;
(2) immersing the glass substrate obtained in the step (1) in an etching solution containing hydrogen fluoride to increase the diameter of the non-through hole;
(3) polishing the other surface of the glass substrate obtained in the step (2) to make the non-through hole a through hole;
(4) A core substrate comprising: a through electrode in the through hole; and a step of forming a wiring portion on the surface of the glass substrate, wherein the through electrode and the wiring portion are in electrical communication. Manufacturing method.   The hole diameter of the non-through hole at the end of step (1) is 50 μm or less, and the hole diameter of the non-through hole at the end of step (2) is 10 to 40 μm than the hole diameter of the non-through hole at the end of step (1). The method for manufacturing a core substrate according to claim 13, wherein the core substrate is large.   The method for manufacturing a core substrate according to claim 13, wherein the maximum height Rz of the surface of the glass substrate at the end of step (2) is 5 µm or less. The method of manufacturing a core substrate according to claim 13, wherein the step (1) is performed by light irradiation using a CO ₂ laser.   Each of the through electrode and the wiring part is independently a metal selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, 14. The method of manufacturing a core substrate according to claim 13, comprising a conductive material selected from the group consisting of an alloy selected from the group consisting of tin-copper, tin-bismuth, and tin-lead. (1) forming a non-through hole on one surface of the glass substrate;
(2) A step of immersing the glass substrate obtained in step (1) in an etching solution containing hydrogen fluoride to increase the diameter of the non-through hole, and simultaneously making the non-through hole a through-hole;
(3) including a step of forming a through electrode in the through hole and a wiring portion on the surface of the glass substrate, wherein the through electrode and the wiring portion are in electrical communication with each other. Manufacturing method.   The diameter of the non-through hole at the end of step (1) is 50 μm or less, and the diameter of the through-hole at the end of step (2) is 10 to 40 μm larger than the diameter of the non-through hole at the end of step (1). The method for manufacturing a core substrate according to claim 18.   The method for manufacturing a core substrate according to claim 18, wherein the maximum height Rz of the surface of the glass substrate at the end of step (2) is 5 µm or less. The method for manufacturing a core substrate according to claim 18, wherein the step (1) is performed by light irradiation using a CO ₂ laser.   Each of the through electrode and the wiring part is independently a metal selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, 19. The method for manufacturing a core substrate according to claim 18, comprising a conductive material selected from the group consisting of an alloy selected from the group consisting of tin-copper, tin-bismuth, and tin-lead. (4) A step of manufacturing a core substrate by the method according to any one of claims 1 to 22;
(5) Wiring process,
(A) forming an insulating resin layer;
(B) providing a via hole in the insulating resin layer to expose at least a part of the wiring portion directly below the insulating resin layer formed in the sub-step (a);
(C) A conductive via in the via hole formed in the sub-step (b) and a wiring portion on the insulating resin layer formed in the sub-step (a) are formed, and the conductive via is connected to the sub-step (a And a wiring process carried out by electrically connecting the wiring part directly below the insulating resin layer formed in step) and the wiring part on the insulating resin layer formed in sub-step (a);
(6) A printed circuit board comprising a step of providing a surface insulating layer having an opening exposing at least a part of the wiring portion formed in the substep (c) of the step (5) performed immediately before. Manufacturing method.   The method for manufacturing a wired circuit board according to claim 23, wherein the wiring step of step (5) is repeatedly performed a plurality of times.   Each of the conductive via formed in the sub-step (c) of the step (5) and the wiring portion formed in the sub-step (c) of the step (5) is independently copper, silver, gold, nickel, A metal selected from the group consisting of platinum, palladium, ruthenium and tin, and a group consisting of an alloy selected from the group consisting of tin-silver, tin-silver-copper, tin-copper, tin-bismuth, and tin-lead. The method for manufacturing a printed circuit board according to claim 23, comprising a conductive material selected from: (7) A step of manufacturing a printed circuit board by the method according to any one of claims 23 to 25;
(8) A method of manufacturing a semiconductor device, comprising: forming a conductive pad in the opening of the surface insulating layer; and (9) fixing a semiconductor element on the conductive pad.