JP2016058483A - Interposer, semiconductor device, and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interposer that can form micro wiring, to provide a semiconductor device comprising the interposer, and to provide a method of manufacturing the semiconductor device.SOLUTION: An interposer 4 comprises: a main body part 11; a first filler control layer 31 provided on one principal surface 11a of the main body part 11 and containing a first resin and a first filler; and a first resin control layer 32 provided on the first filler control layer 31 and containing a second resin and a second filler. Since a ratio of the second resin to a total sum of the second resin and the second filler in the first resin control layer 32, is larger than a ratio of the first resin to a total sum of the first resin and the first filler in the first filler control layer 31, unevenness generated on a surface of the first filler control layer 31 caused by the first filler is alleviated by the first resin control layer 32, and the flatness of the surface is improved.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an interposer, a semiconductor device, and a method for manufacturing a semiconductor device.

  A semiconductor chip such as an IC chip or an LSI may be connected to an external substrate such as a daughter board or a printed wiring board via a connecting member called an interposer. For example, Patent Document 1 below describes an interposer formed from a silicon wafer by applying TSV (Through Silicon Via) technology. Patent Documents 2 to 4 listed below describe an interposer having a mode different from that of Patent Document 1 below.

JP 2001-102479 A Japanese Patent Laid-Open No. 2002-37362 JP 2002-261204 A JP 2000-332168 A

  In recent years, with the advance of technology, the wiring in a semiconductor chip is miniaturized and the number of terminals of the semiconductor chip is increasing. Therefore, an interposer in which fine wiring applicable to such a semiconductor chip is formed is required.

  An object of this invention is to provide the interposer which can form fine wiring, a semiconductor device provided with the said interposer, and the method of manufacturing the said semiconductor device.

  An interposer according to one aspect of the present invention is provided on a main body, one main surface of the main body, and includes a first filler dominant layer including a first resin and a first filler, and a first filler dominant layer. And a first resin dominant layer including a second resin and a second filler, and the ratio of the second resin to the total of the second filler and the second resin in the first resin dominant layer is the first filler dominant layer. Is larger than the ratio of the first resin to the total of the first filler and the first resin.

  In this interposer, the first filler dominant layer and the first resin dominant layer are sequentially provided on one main surface of the main body. The ratio of the second resin to the total of the second filler and the second resin in the first resin dominant layer is larger than the ratio of the first resin to the total of the first filler and the first resin in the first filler dominant layer. ing. That is, the content rate of the second resin in the first resin dominant layer is higher than the content rate of the first resin in the first filler dominant layer. Thereby, the unevenness | corrugation which generate | occur | produces on the surface of the 1st filler dominant layer resulting from a filler is reduced by the 1st resin dominant layer, and the flatness of the surface improves. Even if the fine wiring is formed on the first resin dominant layer, disconnection of the fine wiring can be suppressed. Therefore, it is possible to provide an interposer that can form fine wiring.

  The first filler dominant layer may have a first opening, and the first resin dominant layer may have a second opening that overlaps the first opening in the thickness direction of the main body. . In this case, for example, when the opening is formed in the first filler dominant layer and the first resin dominant layer by laser irradiation, the collapse of the first resin dominant layer generated around the second opening is suppressed, and the second opening Spreading is suppressed. Accordingly, since the area of the flat region of the first resin dominant layer increases, it is possible to effectively form fine wiring.

  In the first filler dominant layer, the ratio of the first filler to the total of the first filler and the first resin is 60% by volume or more and 80% by volume or less. In the first resin dominant layer, the second filler and the second filler The ratio of the second filler to the total resin may be 5% by volume to 30% by volume. In this case, the unevenness generated on the surface of the first filler dominant layer due to the first filler is sufficiently reduced by the first resin dominant layer, and the surface flatness is improved.

  Further, the maximum height roughness of the first resin dominant layer may be 10 nm or more and 50 nm or less. In this case, it is possible to easily form the first resin dominant layer and to effectively form fine wiring.

  Further, the thickness of the first resin dominant layer may be thinner than the thickness of the first filler dominant layer. In this case, fine wiring can be formed without unnecessarily thickening the first resin dominant layer.

  The thickness of the first filler dominant layer may be 3 μm or more and 15 μm or less, and the thickness of the first resin dominant layer may be 2 μm or more and 5 μm or less. In this case, fine wiring can be formed without unnecessarily thickening the first filler dominant layer and the first resin dominant layer.

  Further, the main body may be a glass substrate provided with a plurality of through wirings. In this case, the main body is inexpensive and has high strength, and the main body can be easily enlarged. Further, the linear expansion coefficient increases stepwise from the main body portion to the first resin dominant layer. Thereby, the crack which may be generated when the first filler dominant layer is formed on the main body and when the first resin dominant layer is formed on the first filler dominant layer can be suppressed.

  The interposer is provided on the other main surface of the main body, and is provided in contact with the second filler dominant layer including the third resin and the third filler, and the second filler dominant layer. A second resin dominant layer containing four fillers, and the ratio of the fourth resin to the total of the fourth resin and the fourth filler in the second resin dominant layer is the third resin and third in the second filler dominant layer. It is larger than the ratio of the third resin to the total filler. In this case, the resin layer laminated | stacked on both the main surfaces in a main-body part is formed. Thereby, the curvature resulting from the difference of the linear expansion coefficient of a main-body part and the linear expansion coefficient of a resin layer is suppressed.

  Moreover, the laminated body which has the some conductor circuit provided on the 1st resin dominant layer and was mutually laminated | stacked may be provided, and the thickness of each conductor circuit may be thinner than the thickness of the 1st resin dominant layer.

  Further, at least one of the first resin and the second resin may contain at least one selected from the group consisting of an epoxy resin, a phenol resin, an epoxy phenol resin, a polyimide resin, a cycloolefin resin, and a benzoxazole resin.

  The average particle size of at least one of the first filler and the second filler may be 0.1 μm or more and 2 μm or less. In this case, a decrease in flatness of the surfaces of the first filler dominant layer and the first resin dominant layer is suppressed, and a decrease in fluidity of the first resin and the second resin is suppressed.

  Moreover, at least one of the first filler and the second filler may contain at least one selected from the group consisting of inorganic oxides, carbides, inorganic nitrides, inorganic salts, and silicates. In this case, the linear expansion coefficients of the first filler dominant layer and the first resin dominant layer are reduced.

  A semiconductor device according to another embodiment of the present invention includes any of the interposers described in the above paragraphs and a semiconductor chip mounted on the first resin dominant layer of the interposer. In this semiconductor device, an interposer in which fine wiring can be formed is used. Therefore, the semiconductor chip can be a high-end semiconductor chip having a large number of terminals, and a semiconductor device having high performance can be provided.

  A method for manufacturing a semiconductor device according to another embodiment of the present invention includes a step of preparing any of the interposers described in the above paragraph and a step of mounting a semiconductor chip on the interposer. In this semiconductor device, an interposer in which fine wiring can be formed is used. Therefore, a high-end semiconductor chip having a large number of terminals can be mounted on the first resin dominant layer of the interposer, and a semiconductor device having high performance can be manufactured.

  Moreover, the wiring pattern in the laminated body provided on the first resin dominant layer of the interposer may be provided by a semi-additive method.

  In addition, the through wiring provided in the main body is connected to the wiring pattern in the laminate through the first opening of the first filler dominant layer and the second opening of the first resin dominant layer formed by laser irradiation. May be. In this case, the collapse of the first resin dominant layer generated around the second opening due to the laser irradiation is suppressed, and the spread of the second opening is suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, the interposer which can form fine wiring, the semiconductor device which has the high performance using the said interposer, and the manufacturing method of the said semiconductor device can be provided.

FIG. 1 is a cross-sectional view illustrating a semiconductor device including an interposer according to this embodiment. FIG. 2 is a cross-sectional view illustrating the interposer according to this embodiment. FIG. 3 is an enlarged cross-sectional view of a part of FIG. 4A to 4C are cross-sectional views illustrating an example of a method for manufacturing an interposer. 5A to 5C are cross-sectional views illustrating an example of a method for manufacturing an interposer. 6A to 6C are cross-sectional views illustrating an example of a method for manufacturing an interposer. FIG. 7 is a schematic cross-sectional view illustrating a main body portion and a resin layer of an interposer according to a comparative example. FIG. 8 is a schematic cross-sectional view showing a main body portion and a resin layer of the interposer according to the present embodiment. FIG. 9 is a cross-sectional observation photograph of the example. FIG. 10 is a cross-sectional observation photograph of a comparative example. FIG. 11 is a plane observation photograph of the resin layer of the example. FIG. 12 is a plane observation photograph of the resin film layer of the comparative example.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals are used for the same elements or elements having the same functions, and redundant description is omitted.

  FIG. 1 is a diagram for explaining a semiconductor device including an interposer according to this embodiment. As shown in FIG. 1, the semiconductor device 1 includes semiconductor chips 2 and 3 and an interposer 4. The semiconductor chips 2 and 3 are mounted on one main surface 4 a of the interposer 4. The semiconductor chips 2 and 3 are mounted on the interposer 4 by, for example, a flip chip method. Specifically, the semiconductor chip 2 is connected to a terminal 5 provided on the main surface 4a of the interposer 4, and the semiconductor chip 3 is connected to a terminal 6 provided on the main surface 4a. Yes. A terminal 7 provided on the other main surface 4b of the interposer 4 is provided with solder balls 8 for connection to an external substrate. The terminals 5 to 7 are, for example, a conductive layer containing a metal such as Au, Cu, or Ni, a Cu post, or a solder bump. The solder ball 8 is, for example, a gold ball bump (for example, gold, an alloy containing Au, or a gold bump made of a metal composite having a surface plated with Au, or a bump formed of Au-based solder).

  FIG. 2 is a diagram illustrating the interposer according to the present embodiment. As shown in FIG. 2, the interposer 4 includes a main body 11, resin layers 12 and 13, and laminates 14 and 15.

The main body 11 includes a base material 21 having a plurality of through holes 22 and a plurality of through wires 23 corresponding to the plurality of through holes 22. The base material 21 is, for example, a glass substrate or a silicon wafer. In the present embodiment, a glass substrate is used as the base material 21 from the viewpoint of enabling mass processing on a large panel. Glass substrates are silica (SiO ₂₎ is sufficient if the main component. For example, quartz glass, borosilicate glass, alkali-free glass, soda glass, sapphire glass, or the like is used as the glass. The thickness of the base material 21 may be, for example, 50 μm or more and 500 μm or less, or 100 μm or more and 300 μm or less. The thickness of the base material 21 is preferably thin if handling is possible. The linear expansion coefficient (CTE: Coefficient of Thermal Expansion) of the base material 21 is, for example, not less than −1.0 ppm / ° C. and not more than 10 ppm / ° C. The linear expansion coefficient in the present embodiment has a length that changes in response to a temperature rise within a temperature range of 20 ° C. to 260 ° C., for example.

  The plurality of through holes 22 are provided from one main surface 11 a to the other main surface 11 b of the main body 11 along the thickness direction of the main body 11. The plurality of through holes 22 are formed using a technique called TGV (Through-Glass Via). The diameter of the plurality of through holes 22 may be, for example, 50 μm or more and less than 400 μm, or 50 μm or more and 100 μm or less. The diameters of the plurality of through holes 22 are appropriately set so that a conductive portion 23a described later is filled in the through holes 22.

  Each of the plurality of through wirings 23 is provided on the conductive portion 23a filled in the corresponding plurality of through holes 22, the conductive portion 23b provided on the one main surface 11a, and the other main surface 11b. And a conductive portion 23c. The plurality of through wirings 23 are conductors made of a metal such as Au, Cu, or Ni.

  FIG. 3 is an enlarged view of a part of FIG. As shown in FIG. 3, the resin layer 12 is provided on one main surface 11 a of the main body 11, and includes a first filler dominant layer 31 and a first resin dominant layer 32. The resin layer 12 has a plurality of openings 12a. The opening 12 a overlaps the through wiring 23 of the main body 11. The opening 12a is filled with a conductive via 16 containing a metal such as Au, Cu, or Ni. The maximum height roughness Rz on the main surface 12b of the resin layer 12 based on JIS B 0601: 2013 is, for example, not less than 10 nm and not more than 50 nm. When the maximum height roughness Rz of the resin layer 12 is 10 nm or more, the resin layer 12 can be easily formed. When the maximum height roughness Rz of the resin layer 12 is 50 nm or less, it is possible to prevent the main surface 12b near the opening 12a from being uneven.

  The first filler dominant layer 31 is provided on one main surface 11a and includes a filler (first filler) and a resin (first resin). The first filler dominant layer 31 has an opening (first opening) 31a that is a part of the opening 12a. The film thickness of the first filler dominant layer 31 is not less than 3 μm and not more than 15 μm, for example. When the film thickness of the 1st filler dominant layer 31 is 3 micrometers or more, the short circuit with the main-body part 11 and the laminated body 14 can be suppressed. When the film thickness of the first filler dominant layer 31 is 15 μm or less, the volume of the conductive via 16 filling the opening 12a can be reduced.

As the resin in the first filler dominant layer 31, for example, one of epoxy resin, phenol resin, epoxy phenol resin, polyimide resin, cycloolefin resin, and benzoxazole resin (PBO) or two or more of these resins are mixed. Resin. The filler in the first filler dominant layer 31 is, for example, an inorganic oxide (for example, silica, alumina or titania), a carbide (for example, graphite), an inorganic nitride (for example, aluminum nitride), an inorganic salt, and a silicate. Of these, one or two or more of these are mixed. The average particle diameter of the filler in the first filler dominant layer 31 may be, for example, 0.1 μm or more and 2 μm or less, 0.1 μm or more and 1 μm or less, or 0.1 μm or more and 0.8 μm or less. When the average particle diameter of the filler is 0.1 μm or more, it is possible to suppress a decrease in the fluidity of the resin and to keep the linear expansion coefficient in the first filler dominant layer 31 uniform. When the average particle diameter of the filler is 2 μm or less, a decrease in flatness of the first filler dominant layer 31 can be suppressed, and the maximum height roughness Rz of the main surface 12b of the resin layer 12 can be 50 nm or less. .

  In the 1st filler dominant layer 31, the ratio of the filler with respect to the sum total of resin and a filler is 60 volume% or more and 80 volume% or less, for example. By making the ratio of the filler with respect to the sum total of resin and filler 60 volume% or more, the linear expansion coefficient of the 1st filler dominant layer 31 can be closely approached to the linear expansion coefficient of the base material 21. For example, when the resin of the first filler dominant layer 31 is epoxy phenol, the filler is a silica filler, and the ratio of the filler to the total of the resin and the filler is 60% by volume to 80% by volume, the first filler dominant layer 31 The linear expansion coefficient can be set to 12 ppm / ° C. or more and 20 ppm / ° C. or less. Moreover, it can suppress that a filler falls from the 1st filler dominant layer 31 by making the ratio of the filler with respect to the sum total of resin and a filler 80 volume% or less.

  As shown in FIG. 3, the first resin dominant layer 32 is provided on the first filler dominant layer 31 and includes a filler (second filler) and a resin (second resin). The first resin dominant layer 32 is a part of the opening 12 a and has an opening (second opening) 32 a that overlaps the opening 31 a in the film thickness direction of the main body 11. The film thickness of the first resin dominant layer 32 may be, for example, 2 μm or more and 10 μm or less, or 2 μm or more and 5 μm or less. When the film thickness of the first resin dominant layer 32 is 2 μm or more, the unevenness of the main surface 12b of the resin layer 12 due to the filler is alleviated, and the maximum height roughness Rz of the resin layer 12 is 50 nm or less. Can do. When the film thickness of the first resin dominant layer 32 is 10 μm or less, the volume of the conductive via 16 filling the opening 12a can be reduced. The film thickness of the first resin dominant layer 32 may be thinner than the film thickness of the first filler dominant layer 31.

  The resin in the first resin dominant layer 32 is, for example, one of epoxy resin, phenol resin, epoxy phenol resin, polyimide resin, cycloolefin resin, and benzoxazole resin, or a resin in which two or more of these resins are mixed. is there. In addition, the filler in the first resin dominant layer 32 is, for example, one of inorganic oxide, carbide, inorganic nitride, inorganic salt, and silicate, or a material in which two or more of these are mixed. The average particle diameter of the filler in the first resin dominant layer 32 may be, for example, 0.1 μm or more and 2 μm or less, 0.1 μm or more and 1 μm or less, or 0.1 μm or more and 0.8 μm or less. When the average particle diameter of the filler is 0.1 μm or more, a decrease in resin fluidity can be suppressed, and the linear expansion coefficient in the first resin dominant layer 32 can be kept uniform. When the average particle diameter of the filler is 2 μm or less, it is possible to suppress a decrease in flatness of the first resin dominant layer 32 and to set the maximum height roughness Rz of the resin layer 12 to 50 nm or less.

  In the first resin dominant layer 32, the ratio of the filler to the total of the resin and the filler is, for example, 5% by volume or more and 30% by volume or less. That is, the ratio of the resin to the total filler and resin in the first resin dominant layer 32 is greater than the ratio of the resin to the total filler and resin in the first filler dominant layer 31. By making the ratio of the filler with respect to the sum total of resin and filler 5 volume% or more, the linear expansion coefficient of the 1st resin dominant layer 32 can be closely approached to the linear expansion coefficient of the 1st filler dominant layer 31. FIG. For example, when the resin of the first resin dominant layer 32 is epoxyphenol, the filler is a silica filler, and the ratio of the filler to the total of the resin and filler is 5% by volume to 30% by volume, the first resin dominant layer 32 The linear expansion coefficient can be set to 15 ppm / ° C. or more and 30 ppm / ° C. or less. Further, by setting the ratio of the filler to the total of the resin and the filler to be 30% by volume or less, the filler is detached from the main surface 12b of the resin layer 12 when the opening 12a is formed, and the opening around the main surface 12b is formed. The expansion of the diameter of the part 12a can be suppressed.

  As shown in FIG. 2, the resin layer 13 is provided on the other main surface 11 b of the main body 11. The resin layer 13 desirably has the same configuration as the resin layer 12 from the viewpoint of suppressing warpage of the main body 11. Therefore, the resin layer 13 includes, for example, a resin layer (second filler dominant layer) corresponding to the first filler dominant layer 31 and a resin layer (second resin dominant layer) corresponding to the first resin dominant layer 32. ing. In this case, the ratio of the resin to the total of the resin (fourth resin) and the filler (fourth filler) in the second resin dominant layer is the ratio of the resin (third resin) and the filler (third filler) in the second filler dominant layer. It is larger than the ratio of the resin to the total. The resin layer 13 has a plurality of openings 13a. The opening 13 a overlaps the through wiring 23 of the main body 11. The opening 13a is filled with a conductive via 17 containing a metal such as Au, Cu, or Ni.

  The laminate 14 is provided on the resin layer 12 (or the first resin dominant layer 32) and has a wiring pattern 14a. The wiring pattern 14a is a conductive portion including a metal such as Au, Cu, or Ni. The wiring pattern 14 a is provided inside the stacked body 14 and is connected to the conductive via 16 of the resin layer 12. That is, the wiring pattern 14 a is connected to the through wiring 23 through the conductive via 16 filled in the opening 12 a of the resin layer 12. Moreover, the terminals 5 and 6 provided on the main surface 4a of the interposer 4 which is the surface of the laminated body 14 are connected to the wiring pattern 14a.

  The multilayer body 14 is a multilayer structure having a plurality of conductor circuits 41 stacked on each other. Each of the plurality of conductor circuits 41 includes a resin layer 41a, a conductive via 41b, and a conductive portion 41c. The resin layer 41a is formed of, for example, one of an epoxy resin, a phenol resin, an epoxy phenol resin, a polyimide resin, a cycloolefin resin, and a benzoxazole resin, or a resin in which two or more of these resins are mixed. A wiring pattern 14 a is formed by the conductive vias 41 b and the conductive portions 41 c in the plurality of conductor circuits 41. The film thickness of each of the plurality of conductor circuits 41 is thinner than the film thickness of the first resin dominant layer 32 in the resin layer 12 and is, for example, 2 μm or more and 8 μm or less. The number of layers of the plurality of conductor circuits 41 is changed as necessary.

  The laminated body 15 is provided on the resin layer 13 and has a plurality of openings 15a. The opening 15a is filled with a conductive via 18 containing a metal such as Au, Cu, or Ni. The conductive via 18 is connected to the through wiring 23 through the conductive via 17. The laminated body 15 desirably has the same configuration as the laminated body 14 from the viewpoint of suppressing the warpage of the main body 11. Therefore, the multilayer body 15 is a multilayer structure, and includes a plurality of resin layers 42 stacked on each other, for example, corresponding to the resin layers 41a of the plurality of conductor circuits 41 stacked on each other. A terminal 7 is provided on the other main surface 4 b of the interposer 4 that is the surface of the laminated body 15. The terminal 7 is connected to the conductive via 18.

  Next, with reference to FIGS. 4A to 4C, FIGS. 5A to 5C, and FIGS. 6A and 6B, a method for manufacturing the interposer according to this embodiment will be described. . 4 (a) to 4 (c), 5 (a) to 5 (c), and 6 (a) and 6 (b) are diagrams illustrating an example of a method for manufacturing an interposer.

  First, as shown in FIG. 4A, a plurality of through holes 22 extending along the thickness direction of the base material 21 are formed in the base material 21. For example, the plurality of through holes 22 are formed in the base material 21 by using a drilling jig such as laser irradiation, wet etching, or a drill.

  Next, as illustrated in FIG. 4B, the through wiring 23 is formed in the base material 21. For example, first, after the through hole 22 is filled with the conductive portion 23a, the through wiring 23 is formed by forming the conductive portions 23b and 23c. Alternatively, the through hole of the base material 21 may be filled with a conductive material, and after the conductive material is formed on the entire surface of the base material 21, a part of the conductive material may be removed to form the through wiring 23. Good. Thereby, the main-body part 11 is formed.

  The conductive portions 23a to 23c may be formed by sputtering, vacuum deposition, or the like, or may be formed by plating or the like. When the plating method is used, it is easy to form a metal film uniformly in the through hole 22. Further, since it is not necessary to use a film forming apparatus having a vacuum chamber and a pump, the through wiring 23 can be formed at low cost.

  When a conductive substance is formed on the entire surface of the substrate 21 by plating or the like, the substrate excluding the conductive portions 23a filled in the through holes 22 and the conductive portions 23b and 23c formed on the surface of the substrate 21 21 Conductive material on the surface is removed. In this case, the conductive material is removed by, for example, etching. Moreover, you may remove electroconductive substances other than the electroconductive part 23a with which the through-hole 22 was filled. In this case, the conductive material may be removed by, for example, mechanical polishing, sand blasting, etching, or the like. In addition, chemical mechanical polishing (CMP) may be performed to completely remove the conductive material. When the conductive material other than the conductive portion 23a is removed, the conductive portions 23b and 23c in the through wiring 23 are formed by, for example, sputtering.

  Further, the through wiring 23 may be formed by using an electroless plating method. For example, an electroless plating method can be used by forming an organic layer capable of supporting an electroless plating catalyst or a metal layer serving as a seed layer on the substrate 21. In this case, the through hole 22 can be filled in a short time.

  Below, the specific example of the electroless-plating method is demonstrated. First, when the base material 21 is a glass substrate containing silicon oxide as a main component, an organic layer is formed by supplying a silane coupling agent or the like to the surface of the base material 21. Electroless plating can be applied to the substrate 21 by supporting a catalyst (for example, a metal such as palladium or platinum) on the functional group of the organic layer. In this specific example, Cu plating is performed from the viewpoint of easily performing plating and from the viewpoint of using a metal having high thermal conductivity.

  The functional group of the silane coupling agent composing the organic layer desirably contains an electron donating group. This is because the electron donating group interacts with a metal ion which is a catalyst for electroless plating, and ions can be selectively adsorbed on the organic layer. Examples of the electron donating group of the silane coupling agent include an amino group or a thiol group. In addition, the metal ions adsorbed on the organic layer become a metal by performing a reduction treatment, and can be used as a catalyst. For example, metal ions can be reduced by adding a reducing agent to the electroless plating solution. The reducing agent to be added is, for example, sodium hypophosphite, dimethylamine borane, formalin, sodium borohydride, hydrazine or the like. In addition, when a metal ion is not reduced by the reducing agent added in the electroless plating solution, the metal ion is reduced in advance before performing electroless plating. For example, when palladium ions are adsorbed on the organic layer as a catalyst, reduction can be achieved if the reducing agent added to the electroless plating solution is sodium hypophosphite or dimethylamine borane. On the other hand, for example, when formaldehyde is used as a reducing agent, palladium ions cannot be reduced. In this case, palladium ions are reduced using dimethylamine borane or the like before electroless plating.

  Next, as illustrated in FIG. 4C, the resin layer 12 is formed on one main surface 11 a of the main body 11. For example, the resin layer 12 is formed by laminating the first filler dominant layer 31 and the first resin dominant layer 32 together and laminating the single layer on the main body 11. For example, it is formed by vacuum lamination, rubber press, and hot press using a vacuum laminator. The vacuum laminating is performed, for example, at room temperature or around 100 ° C. for 30 seconds to 40 seconds. The rubber press is performed, for example, under the conditions of 0.08 MPa to 1.4 MPa, 90 ° C. to 100 ° C., and 40 seconds to 80 seconds. Hot pressing is performed, for example, under conditions of 0.08 MPa to 1.4 MPa, 100 ° C. to 120 ° C., and 40 seconds to 80 seconds. The resin layer 13 is formed on the other main surface 11b by the above method.

  Next, as shown in FIG. 5A, an opening 12a is formed in the resin layer 12 by laser irradiation. For example, the opening 12a is formed using a UV laser such as a YAG third harmonic (355 nm), a YAG fourth harmonic (266 nm), or a KrF excimer laser. For example, laser irradiation is performed so that the diameter of the opening 12a is 10 μm or more and 20 μm or less. For example, when a carbon dioxide laser is used, it is difficult to control the diameter of the opening 12a to 10 μm or more and 20 μm or less because it has a high wavelength but a long wavelength. Therefore, it is desirable to use a UV laser for forming the opening 12a.

  After the opening 12a is formed in the resin layer 12 by UV laser, desmear treatment using potassium permanganate is performed to remove smear (residue). For example, the desmear treatment using potassium permanganate is performed in the order of a swelling step, a potassium permanganate treatment step, and a neutralization step. By performing desmear treatment using potassium permanganate, it is possible to remove smear of the resin layer 12 and flatten the main surface 12b of the resin layer 12. The opening 13a is formed in the resin layer 13 by the above method.

  Further, the conductive via 16 is filled in the opening 12 a of the resin layer 12 that has been subjected to the desmear process, and the conductive layer 51 is formed on the main surface 12 b of the resin layer 12. The conductive via 16 and the conductive layer 51 are formed by, for example, sputtering, vacuum deposition, plating, or the like. The conductive layer 51 is patterned by using, for example, a resist. The thickness of the resist varies depending on the line and space (hereinafter, L / S) of the conductive layer 51, and is, for example, 5 μm to 25 μm. Further, the conductive via 17 is filled in the opening 13 a of the resin layer 13 by the same method, and the conductive layer 52 is formed on the main surface of the resin layer 13.

  Next, as shown in FIG. 5B, the conductor layer 41 is formed by forming the resin layer 41 a and the conductive via 41 b on the conductive layer 51. The resin layer 41a in the conductor circuit 41 is formed by, for example, an ink jet method or a spin coat method. The conductive via 41b is filled in, for example, an opening provided by irradiating the resin layer 41a with a laser. Here, the conductive layer 51 corresponds to the conductive portion 41c of the conductor circuit 41, and the conductive via 41b and the conductive portion 41c of the conductive circuit 41 are formed by, for example, a semi-additive method. In the semi-additive method, a seed layer such as a Cu layer is formed, a resist having a desired pattern is formed on the seed layer, and an exposed portion of the seed layer is thickened by an electrolytic plating method or the like to remove the resist. Thereafter, the thin seed layer is etched to obtain the conductive via 41b and the conductive portion 41c. Further, the resin layer 42 is formed on the main surface of the resin layer 13 by the same method.

  Next, as shown in FIG. 5C, FIG. 6A, and FIG. 6B, the laminate 14 having the wiring pattern 14a is formed by forming the necessary number of layers of the conductor circuit 41. To do. For example, as shown in FIG. 5C, a conductive portion 41c is formed using a resist 43 patterned on the conductor circuit 41, and then the resist 43 is removed as shown in FIG. 6A. To do. And the laminated body 14 is formed by laminating | stacking the several conductor circuit 41 by the method demonstrated above.

  Next, terminals 5 and 6 are formed on the main surface of the laminate 14. The wiring pattern 14a is formed by, for example, a semi-additive method. Further, on the resin layer 13, a laminated body 15 including a plurality of resin layers 42 and including the conductive vias 18 is formed, and the terminals 7 are formed on the main surface of the laminated body 15. Thereby, the interposer 4 is formed.

  Further, by mounting the semiconductor chips 2 and 3 on the formed interposer 4, the semiconductor device 1 shown in FIG. 1 is formed. In this case, the semiconductor chip 2 is connected to the terminal 5 of the interposer 4 and the semiconductor chip 3 is connected to the terminal 6. The interposer 4 and the semiconductor chips 2 and 3 may be joined via solder, or after joining via solder, the joint may be sealed with underfill.

  In the interposer 4 according to the present embodiment described above, the resin layer 12 in which the first filler dominant layer 31 and the first resin dominant layer 32 are sequentially laminated is provided on one main surface 11a of the main body 11. ing. Further, the ratio of the resin to the total of the resin and filler in the first resin dominant layer 32 is larger than the ratio of the resin to the total of the resin and filler in the first filler dominant layer 31. That is, the resin content in the first resin dominant layer 32 is higher than the resin content in the first filler dominant layer 31. Thereby, the unevenness | corrugation which generate | occur | produces on the surface of the 1st filler dominant layer 31 resulting from a filler is reduced by the 1st resin dominant layer 32, and the flatness of the main surface 12b of the resin layer 12 improves. Even if the wiring pattern 14a is formed on the first resin dominant layer 32, disconnection of the wiring pattern 14a can be suppressed. Accordingly, it is possible to provide the interposer 4 in which the wiring pattern 14a which is a fine wiring can be formed.

  The first filler dominant layer 31 has an opening 31 a, and the first resin dominant layer 32 has an opening 32 a that overlaps the opening 31 a in the thickness direction of the main body 11. The effect produced by this is demonstrated using a comparative example. FIG. 7 is a cross-sectional view illustrating a main body portion and a resin layer of an interposer according to a comparative example. FIG. 8 is a cross-sectional view showing the main body and the resin layer of the interposer according to the present embodiment.

  First, an interposer according to a comparative example will be described. As shown in FIG. 7, in the interposer 104 according to the comparative example, a single resin layer 112 is provided on one main surface 11 a of the main body 11. The resin layer 112 includes a resin and a filler, and the ratio of the resin to the total of the resin and the filler in the resin layer 112 is the same as that of the first filler dominant layer 31 of the present embodiment. The resin and filler of the resin layer 112 are the same as the resin and filler of the first filler dominant layer 31. The resin layer 112 is provided with a plurality of openings 112a. The opening 112 a is provided by laser irradiation, and includes a first region 161 located on the main body 11 side and a second region 162 located on the main surface 112 b side of the resin layer 112.

  As shown in FIG. 7, by forming the opening 112a in the resin layer 112 by laser irradiation, the center diameter L2 in the second region 162 is larger than the center diameter L1 in the first region 161. Specifically, the resin of the resin layer 112 collapses as the energy of the irradiated laser propagates in the vicinity of the main surface 112b. Thereby, the filler dispersed in the resin layer 112 falls off, and the diameter of the opening 112a in the vicinity of the main surface 112b of the resin layer 112 increases. A step S having a depth of 1 to 2 μm is formed by the first region 161 and the second region 162. As described above, when the diameter of the opening 112a in the main surface 112b of the resin layer 112 is increased and the step S is formed, a region where the wiring on the main surface 112b can be formed becomes narrow.

  For example, when the opening 112a is formed to have a diameter of about 20 μm, the diameter of the opening 112a in the main surface 112b is about 40 μm. In this case, the formation conditions of vias (conductive vias) / lands (terminal portions, conductive portions) are, for example, 60 μm / 90 μm or more. Moreover, since the ratio of the filler in the resin layer 112 is large, the maximum height roughness Rz is increased. For this reason, L / S of the wiring layer formed on the main surface 112b of the resin layer 112 is, for example, 10 μm / 10 μm or more.

  Here, as the ratio of the filler in the resin layer 112 increases, the resin per unit volume of the resin layer 112 decreases. For this reason, the resin layer 112 is easily collapsed, and the diameter of the opening 112a is easily widened. In order not to increase the diameter of the opening 112a, it is conceivable to increase the ratio of the resin in the resin layer. Therefore, the ratio of the resin to the total of the resin and filler in the resin layer according to the comparative example is the same as that of the first resin dominant layer 32 of the present embodiment. In this case, even if a part of the resin in the resin layer collapses, the remaining resin suppresses the filler from falling off. Thereby, it is suppressed that the diameter of the opening part of the main surface vicinity of a resin layer spreads. However, when the main body 11 is formed of a silicon wafer or a glass substrate, the difference between the linear expansion coefficient of the main body 11 and the linear expansion coefficient of the resin layer is increased. As a result, the amount of positional deviation between the through wiring 23 of the main body 11 and the opening 112a of the resin layer 112 may increase, the resin layer 112 may crack, and the resin layer 112 may peel from the main body 11. There is.

  On the other hand, as shown in FIG. 8, in the interposer 4 according to the present embodiment, the resin layer 12 provided on the one main surface 11 a of the main body portion 11 includes the first filler dominant layer 31 and the first filler dominant layer 31 that are sequentially stacked. The first resin dominant layer 32 is provided, and the ratio of the resin to the total resin and filler in the first resin dominant layer 32 is larger than the ratio of the resin to the total resin and filler in the first filler dominant layer 31. ing. That is, the resin content in the first resin dominant layer 32 is higher than the resin content in the first filler dominant layer 31. Thereby, for example, when the openings 31a and 32a are formed in the first filler dominant layer 31 and the first resin dominant layer 32 by laser irradiation, the collapse of the first resin dominant layer 32 generated around the opening 32a is suppressed. The Moreover, when the opening part 12a is provided in the resin layer 12, it is suppressed that the diameter of the opening part of the main surface 12b vicinity of the resin layer 12 spreads. As described above, by increasing the area of the flat region on the main surface 12b of the resin layer 12, it is possible to effectively form fine wiring. For example, the opening 12a can be formed in the resin layer 12 so that the via / land condition is 20 μm / 30 μm or less at a pitch of 40 μm to 55 μm, and the L / S condition satisfies 4 μm / 4 μm. It is possible to form the wiring pattern 14a.

  Moreover, in the 1st filler dominant layer 31, the ratio of the filler with respect to the sum total of resin and a filler is 60 volume% or more and 80 volume% or less, and in the 1st resin dominant layer 32, the ratio of the filler with respect to the sum total of resin and a filler is 5 volume% or more and 30 volume% or less may be sufficient. In this case, the unevenness generated on the surface of the first filler dominant layer 31 due to the filler is sufficiently reduced by the first resin dominant layer 32, and the flatness of the main surface 12b of the resin layer 12 is improved.

  Further, the maximum height roughness Rz of the first resin dominant layer 32 may be not less than 10 nm and not more than 50 nm. In this case, the first resin dominant layer 32 can be easily formed, and the wiring pattern 14a can be effectively formed.

  Further, the thickness of the first resin dominant layer 32 may be smaller than the thickness of the first filler dominant layer 31. In this case, the wiring pattern 14a can be formed without unnecessarily thickening the first resin dominant layer 32.

  Further, the thickness of the first filler dominant layer 31 may be 3 μm or more and 15 μm or less, and the thickness of the first resin dominant layer 32 may be 2 μm or more and 5 μm or less. In this case, the wiring pattern 14a can be formed without unnecessarily increasing the thickness of the first filler dominant layer 31 and the first resin dominant layer 32.

  Further, the main body 11 may be a glass substrate provided with a plurality of through wirings 23. In this case, the main body 11 is inexpensive and has high strength, and the main body 11 can be easily enlarged. Further, the linear expansion coefficient increases stepwise from the main body 11 to the first resin dominant layer 32. Thereby, the crack which may be generated when the first filler dominant layer 31 is formed on the main body 11 and when the first resin dominant layer 32 is formed on the first filler dominant layer 31 can be suppressed. In addition, the linear expansion coefficient of the main body 11 is close to the linear expansion coefficient of the semiconductor chips 2 and 3 mounted on the interposer 4. For this reason, the dimensional change of the main-body part 11 after a heating becomes small, and mounting of the semiconductor chips 2 and 3 can be performed favorably. Further, by providing the through wiring 23 in the main body 11, the interposer 4 and the semiconductor chips 2 and 3 can be connected in a multi-pin parallel manner. Thereby, excellent electrical characteristics can be obtained and low power consumption can be achieved.

  The interposer 4 includes a resin layer 13 provided on the other main surface 11b of the main body 11, and the resin layer 13 includes a second filler dominant layer containing a resin and a filler, and a second filler dominant layer. A second resin dominant layer including a resin and a filler provided in contact with the layer, and the ratio of the resin to the total of the resin and filler in the second resin dominant layer is the ratio of the resin and filler in the second filler dominant layer. It may be larger than the ratio of the resin to the total. In this case, in the main body 11, the resin layer 12 is formed on one main surface 11a, and the resin layer 13 is formed on the other main surface 11b. Thereby, the curvature resulting from the difference of the linear expansion coefficient of the main-body part 11 and the linear expansion coefficient of the resin layer 12 is suppressed.

  The average particle size of the filler contained in the first filler dominant layer 31 and the filler contained in the first resin dominant layer 32 may be 0.1 μm or more and 2 μm or less. In this case, the deterioration of the flatness of the surfaces of the first filler dominant layer 31 and the first resin dominant layer 32 is suppressed, and the resin contained in the first filler dominant layer 31 and the resin contained in the first resin dominant layer 32 The decrease in fluidity is suppressed.

  The filler contained in the first filler dominant layer 31 and the filler contained in the first resin dominant layer 32 are at least one selected from the group consisting of inorganic oxides, carbides, inorganic nitrides, inorganic salts, and silicates. It may contain. In this case, the linear expansion coefficients of the first filler dominant layer 31 and the first resin dominant layer 32 are reduced.

  Further, the semiconductor device 1 manufactured using the interposer 4 according to the present embodiment includes the semiconductor chips 2 and 3 mounted on the stacked body 15 provided on the first resin dominant layer 32 of the interposer 4. . Since the semiconductor device 1 uses the interposer 4 in which fine wiring can be formed, the semiconductor chips 2 and 3 can be high-end semiconductor chips with a large number of terminals, and the semiconductor device 1 having high performance. Can provide.

  Further, the through wiring 23 provided in the main body 11 is connected to the wiring pattern 14a through the opening 31a of the first filler dominant layer 31 and the opening 32a of the first resin dominant layer 32 formed by laser irradiation. May be. In this case, the collapse of the first resin dominant layer 32 generated around the opening 32a due to laser irradiation is suppressed, and the spread of the opening 32a is suppressed.

  The interposer, the semiconductor device, and the semiconductor device manufacturing method according to the present invention are not limited to the above-described embodiments, and various other modifications are possible. For example, in the above embodiment, the resin layer 13 is not necessarily provided.

  The resin layer included in the resin layer 12 is not limited to the first filler dominant layer 31 and the first resin dominant layer 32, and the resin layer 12 may include three or more resin layers. For example, an intermediate layer containing a resin and a filler may be included between the first filler dominant layer 31 and the first resin dominant layer 32. In this case, the ratio of the filler to the total of the resin and filler in the intermediate layer is smaller than the first filler dominant layer 31 and larger than the first resin dominant layer 32. Thereby, the change of the linear expansion coefficient from the main-body part 11 to the laminated body 14 becomes still more moderate. In this case, it is preferable that the resin layer 13 also includes three or more resin layers.

  Moreover, the wiring pattern 14a in the laminated body 14 is not limited to the semi-additive method, and is formed by a known method such as a subtractive method or a full additive method. Here, the subtractive method is a method in which a resist having a desired pattern is formed on a conductor layer such as a Cu layer, an unnecessary conductor layer is etched, and then the resist is removed to obtain a wiring pattern 14a. In the full additive method, an electroless plating catalyst is adsorbed on the resin layer, a resist having a desired pattern is formed on the resin layer, and the catalyst is activated while leaving the resist as an insulating film. In this method, after a conductor such as Cu is deposited in the resist opening by the method, the resist is removed to obtain a desired wiring pattern 14a.

  The present invention will be described in more detail with reference to the following examples, but the present invention is not limited to these examples.

(Example)
In the example, as shown in FIG. 2, the resin layer 12 was formed on one main surface 11 a of the main body 11. As the main body 11, a glass substrate (Corning Eagle XG non-alkali glass, thickness: 300 μm) was used, and a plurality of through wirings 23 were formed in the glass substrate. The resin layer 12 was a resin sheet in which a first filler dominant layer 31 having a thickness of 12 μm and a first resin dominant layer 32 having a thickness of 2 μm were laminated to each other. The first filler dominant layer 31 is mainly composed of resin (epoxyphenol) and filler (SiO ₂ ), and the ratio of the resin to the total of the resin and filler in the first filler dominant layer 31 is adjusted to 30% by volume (ie, The ratio of the filler to the total of the resin and filler in the first filler dominant layer 31 was adjusted to 70% by volume). Further, the first resin ruling 32 is a resin (epoxy phenol) and fillers (SiO ₂₎ as main components, and adjusting the proportion of the resin to the total of the resin and the filler in the first resin ruling 32 to 80 vol% (That is, the ratio of the filler to the total resin and filler in the first resin dominant layer 32 was adjusted to 20% by volume). The average particle size of the filler contained in the first filler dominant layer 31 and the first resin dominant layer 32 was about 0.5 μm. Rubber press using a vacuum laminator (V160 manufactured by Nichigo Morton Co., Ltd.) under conditions of rubber press 0.1 MPa, 100 ° C., 60 seconds, then hot press under conditions of 1.0 MPa, 110 ° C., 90 seconds The resin layer 12 was laminated on one main surface 11a of the main body 11.

  Using a YAG laser device (MODEL 5330 manufactured by ESI JAPAN Co., Ltd.) that emits the third harmonic (355 nm) to the resin layer 12 laminated on the main body 11, conditions of a frequency of 70 KHz, an output of 0.2 W, and a pulse width of 10 s Opening 12a was formed. A desmear process was performed after forming the openings 12a, and the openings 12a having a processing diameter set to 15 μm were formed at a pitch of 40 μm.

  Next, the main body 11 and the resin layer 12 were immersed in an aqueous palladium chloride solution (0.2 g / L) at room temperature for 10 minutes, and palladium ions serving as a catalyst were supported in the resin layer 12. The resin layer 12 to which the catalyst was attached was immersed in a solution containing 0.1 mol / L dimethylamine borane at 60 ° C. for 30 seconds to reduce the supported palladium ions. Subsequently, electroless copper plating was performed using the reduced palladium as a nucleus, and a Cu film having a thickness of 0.5 μm was uniformly formed on the resin layer 12 and in the opening 12a.

  On the Cu film formed by electroless plating, a resist (RY5319 manufactured by Hitachi Chemical Co., Ltd.) was formed to a thickness of 19 μm, and then patterned through exposure and development. Conductive vias 16 were filled in the openings 12a by electrolytic copper plating in the patterned portion, and then the resist was removed. By forming a resin layer at the place where the resist was removed, a conductor circuit 41 having L / S set to 4 μm / 4 μm was formed. A plurality of conductor circuits 41 that were laminated to each other were formed by the same method, and the laminated body 14 was formed. In addition, the interposer 4 was formed by forming the resin layer 13, the conductive via 17, the laminate 15, and the terminal 7 on the other main surface 11 b of the main body 11.

(Comparative example)
In the comparative example, in place of the resin layer 12 of the example, a single resin film containing a filler (ABF made by Ajinomoto Fine Techno Co., Ltd., ABF series GX-T31) was used in the same steps and conditions as in the example. An interposer was formed.

(Observation of resin layer shape)
The cross-sectional structure of the resin layer 12 of the interposer of the example and the cross-sectional structure of the resin film of the interposer according to the comparative example are each observed by SEM (Hitachi High-Resolution FE-SEM S-4800, manufactured by Hitachi High-Technologies Corporation). did. FIG. 9 is a cross-sectional observation photograph of the example, and FIG. 10 is a cross-sectional observation photograph of the comparative example. As shown in FIG. 9, the resin layer 12 includes a first filler dominant layer 31 and a first resin dominant layer 32, and the ratio of the filler to the resin and filler in the first filler dominant layer 31 is the first. It was confirmed that it was larger than the resin dominant layer 32. On the other hand, as shown in FIG. 10, it was confirmed that the resin film 212 has a single layer structure.

(Opening shape observation)
The shape of the opening 12a of the resin layer 12 of the interposer of the example and the shape of the opening of the resin film of the interposer according to the comparative example were each observed by SEM. FIG. 11 is a plane observation photograph of the resin layer of the example, and FIG. 12 is a plane observation photograph of the resin film of the comparative example. As shown in FIG. 11, it was confirmed that the main surface 12b around the opening 12a of the resin layer 12 was flat. On the other hand, as shown in FIG. 12, the diameter of the opening 212a in the surface 212b of the resin film 212 is about twice the set value, and it was confirmed that the step S1 was formed. Therefore, it is confirmed that the resin layer 12 having the first filler dominant layer 31 and the first resin dominant layer 32 has a smaller diameter of the opening than the single resin layer containing the filler. It was done.

(Measurement of maximum height roughness Rz)
The maximum height roughness Rz of the resin layer 12 of the interposer of the example and the resin film of the interposer according to the comparative example was measured. These maximum height roughnesses Rz were measured using an optical interference type surface shape measuring instrument (Japan WYKO Corporation, NT-3300). The results of Examples and Comparative Examples are shown in Table 1 below.

(Peel strength measurement)
The peel strength of the wiring provided on the resin layer 12 of the interposer of the example and the peel strength of the wiring provided on the resin film of the interposer according to the comparative example were measured. Here, the peel strength of the wiring is a force required for the wiring to peel from the resin layer or the resin film. Using a bond tester (BT-4000 manufactured by Daisy Japan Co., Ltd.), the peel strength of a bundle of 10 wires having the L / S set to 4 μm / 4 μm was measured. The number of measurements was 20 times. The results of Examples and Comparative Examples are average values of each peel strength, and the results are shown in Table 1 below.

  As shown in Table 1 above, it was confirmed that the maximum height roughness Rz of the resin layer 12 of the example was smaller than that of the resin film of the comparative example. Further, it was confirmed that the peel strength of the wiring of the example was about three times the peel strength of the wiring of the comparative example.

  According to the interposer, the semiconductor device, and the method of manufacturing the semiconductor device of the present invention, the interposer capable of forming fine wiring, the semiconductor device having high performance using the interposer, and the method of manufacturing the semiconductor device Can provide.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2, 3 ... Semiconductor chip, 4,104 ... Interposer, 11 ... Main-body part, 11a ... One main surface, 11b ... The other main surface, 12, 13, 112 ... Resin layer, 12a, 13a ... Opening part, 14, 15 ... Laminated body, 14a ... Wiring pattern, 21 ... Substrate, 22 ... Through hole, 23 ... Through wiring, 31 ... First filler dominant layer, 31a ... Opening part (first opening part), 32 ... 1st resin control layer, 32a ... Opening part (2nd opening part), 41 ... Conductor circuit.

Claims (16)

The main body,
A first filler-dominating layer provided on one main surface of the main body and including a first resin and a first filler;
A first resin dominating layer provided on the first filler dominating layer and comprising a second resin and a second filler;
With
The ratio of the second resin to the sum of the second filler and the second resin in the first resin dominant layer is the first resin relative to the sum of the first filler and the first resin in the first filler dominant layer. Greater than the proportion of
Interposer. The first filler dominant layer has a first opening,
2. The interposer according to claim 1, wherein the first resin dominant layer has a second opening that overlaps the first opening in the thickness direction of the main body. In the first filler dominant layer, a ratio of the first filler to a total of the first resin and the first filler is 60% by volume or more and 80% by volume or less,
The interposer according to claim 1 or 2, wherein in the first resin dominant layer, a ratio of the second filler to a total of the second resin and the second filler is 5% by volume or more and 30% by volume or less.   The interposer according to any one of claims 1 to 3, wherein the maximum height roughness of the first resin dominant layer is 10 nm or more and 50 nm or less.   The interposer according to any one of claims 1 to 4, wherein a thickness of the first resin dominant layer is thinner than a thickness of the first filler dominant layer. The thickness of the first filler dominant layer is 3 μm or more and 15 μm or less,
The interposer according to any one of claims 1 to 5, wherein a thickness of the first resin dominant layer is 2 µm or more and 5 µm or less.   The interposer according to any one of claims 1 to 6, wherein the main body is a glass substrate on which a plurality of through wirings are provided. A second filler-dominating layer provided on the other main surface of the main body portion and containing a third resin and a third filler;
A second resin dominating layer provided in contact with the second filler dominating layer and including a fourth resin and a fourth filler;
The ratio of the fourth resin to the total of the fourth resin and the fourth filler in the second resin dominant layer is the third resin relative to the total of the third resin and the third filler in the second filler dominant layer. The interposer according to any one of claims 1 to 7, wherein the interposer is larger than the ratio of. Provided on the first resin dominant layer, comprising a laminate having a plurality of conductor circuits laminated on each other,
The interposer according to any one of claims 1 to 8, wherein a thickness of each of the conductor circuits is thinner than a thickness of the first resin dominant layer.   At least one of the first resin and the second resin contains at least one selected from the group consisting of an epoxy resin, a phenol resin, an epoxy phenol resin, a polyimide resin, a cycloolefin resin, and a benzoxazole resin. The interposer according to any one of 9.   The interposer according to any one of claims 1 to 10, wherein an average particle diameter of at least one of the first filler and the second filler is 0.1 µm or more and 2 µm or less.   At least one of the first filler and the second filler contains at least one selected from the group consisting of inorganic oxides, carbides, inorganic nitrides, inorganic salts, and silicates. The interposer according to one item. The interposer according to any one of claims 1 to 12,
A semiconductor chip mounted on the resin-dominating layer of the interposer;
A semiconductor device comprising: Preparing the interposer according to any one of claims 1 to 12,
Mounting a semiconductor chip on the interposer;
A method for manufacturing a semiconductor device comprising:   The method of manufacturing a semiconductor device according to claim 14, wherein the wiring pattern in the stacked body provided on the first resin dominant layer of the interposer is provided by a semi-additive method.   The through wiring provided in the main body is connected to the wiring pattern through the first opening of the first filler dominant layer and the second opening of the first resin dominant layer formed by laser irradiation. The method of manufacturing a semiconductor device according to claim 15.