JP2015122513A - 電子デバイスをパッケージングするためのシステムおよび方法 - Google Patents
電子デバイスをパッケージングするためのシステムおよび方法 Download PDFInfo
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- JP2015122513A JP2015122513A JP2015004979A JP2015004979A JP2015122513A JP 2015122513 A JP2015122513 A JP 2015122513A JP 2015004979 A JP2015004979 A JP 2015004979A JP 2015004979 A JP2015004979 A JP 2015004979A JP 2015122513 A JP2015122513 A JP 2015122513A
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- solder
- electronic device
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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Abstract
Description
Claims (14)
- 電子デバイスのウエハレベルパッケージング方法であり、
半田ジェットのための半田を溶融する工程と、
前記半田ジェットからの溶融半田をウエハレベルパッケージ電子デバイスの第1の構成要素の基板上に溶融半田の複数の個々のドットをパターン状に堆積させる工程と、
前記電子デバイスの第2の構成要素が前記第1の構成要素から持ち上げられるように、前記電子デバイスの第2の構成要素を、前記電子デバイスの前記第1の構成要素上に堆積された半田の前記パターンに位置合わせする工程と、
前記電子デバイスの前記第1の構成要素上に前記パターン状に堆積された半田を再溶融させ且つリフローさせる工程と、
前記半田が再溶融される際に、前記電子デバイスの前記第1の構成要素および前記電子デバイスの第2の構成要素を圧縮して、前記パターン状に堆積された半田の連続したリフローと前記第1の構成要素及び第2の構成要素の接合とが同時に起こって前記第2の構成要素が前記パターンの部分に接合するようさせる工程と、を含む方法。 - 請求項1記載の方法において、
前記電子デバイスの前記第1の構成要素および当該電子デバイスの前記第2の構成要素を真空中に配置する工程を更に備える、方法。 - 請求項1記載の方法において、
前記半田ジェットからの溶融半田を電子デバイスの第1の構成要素の基板上にパターン状に堆積させる前記工程は、当該半田ジェットからの溶融半田を当該電子デバイスの前記第1の構成要素の基板に形成される金属パターン上へ堆積させる工程を含む、方法。 - 請求項1記載の方法において、
前記半田ジェットからの溶融半田を電子デバイスの第1の構成要素の基板上にパターンを成して堆積させる前記工程は、溶融半田の複数の個々のドットの少なくとも一部同士の間に複数の隙間を備えるパターン状に当該半田ジェットからの溶融半田を堆積させる工程を含む、方法。 - 請求項1記載の方法において、
前記電子デバイスの前記第1の構成要素と当該電子デバイスの前記第2の構成要素との間の隙間を密封シールする工程を更に備える、方法。 - 請求項1記載の方法において、
前記電子デバイスが赤外線検出器を備える、方法。 - 請求項1に記載の方法において、前記半田が金80%を含んでいる、方法。
- 電子デバイスのウエハレベルパッケージング方法であり、
第1の基板上に、個々の半田滴を、該半田滴間に滴間隙間が形成されるパターンで堆積させる工程と、
第2の基板を、前記第1の基板及び前記半田滴のパターンに対して位置合わせする工程であって、前記第1の基板と前記第2の基板とが実質的に平行で前記第1の基板と第2の基板との間に基板間隙間が存在するように前記第2の基板を位置合わせする工程と、
前記基板間の隙間に真空を形成する工程と、
少なくとも部分的に未溶融である半田滴を、リフローが始まるまで加熱する工程と、を含み、
前記第1と前記第2の基板とを圧縮することにより、該圧縮中に、前記半田滴間隙間によって付与される空間によって、圧力が圧縮によって前記基板間の隙間から逃げるのが可能にされ、前記半田滴が溶融して、半田の帯と前記第1及び第2の基板とによって規定される領域に密封シールを形成する連続した帯が形成されるようにする、ことを特徴とする方法。 - 請求項8に記載の方法において、前記パターンが第1の基板上に形成される、方法。
- 請求項8に記載の方法において、前記圧縮が重力によって付与される、方法。
- 請求項8に記載の方法において、前記圧縮がアライメント装置によって付与される、方法。
- 請求項8に記載の方法において、前記真空コンダクタンス隙間が300マイクロメートルを超えている、方法。
- 請求項8記載の方法において、前記電子デバイスが赤外線検出器を備えている、方法。
- 請求項8記載の方法において、前記半田滴が金80%を含んでいる、方法。
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US9570321B1 (en) | 2015-10-20 | 2017-02-14 | Raytheon Company | Use of an external getter to reduce package pressure |
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