JP2015065479A5

JP2015065479A5 -

Info

Publication number: JP2015065479A5
Application number: JP2014260268A
Authority: JP
Filing date: 2014-12-24
Publication date: 2015-05-21
Anticipated expiration: 2030-01-22

Claims

A first semiconductor wafer having a pixel array in which a photoelectric conversion unit, at least one transfer transistor, a reset transistor, and an amplifying transistor are formed;
A logic circuit on which a signal processing circuit is formed; a second semiconductor wafer bonded to the first semiconductor wafer;
A through-connection hole formed through the first semiconductor wafer and reaching a wiring formed in the second semiconductor wafer;
A first connection conductor embedded in the through-connection hole;
A connection hole formed through the first semiconductor wafer and reaching the wiring formed in the first semiconductor wafer;
A second connection conductor embedded in the connection hole,
The first connection conductor and the wiring formed on the second semiconductor wafer are connected, and the second connection conductor and the wiring formed on the first semiconductor wafer are connected. A semiconductor device in which the pixel array and the logic circuit are electrically connected.

The semiconductor device according to claim 1, further comprising an electrode pad that electrically connects the first connection conductor and the second connection conductor and is exposed to the first semiconductor wafer side.

The semiconductor device according to claim 1, wherein the through-hole and the connection hole are provided close to each other, and the through-hole is provided outside the connection hole.

4. The semiconductor device according to claim 1, further comprising a third connection conductor that is electrically connected to the logic circuit and exposed on a back surface side of the second semiconductor wafer. 5.

The semiconductor device according to claim 1, wherein the first connection conductor and the second connection conductor are formed outside a region where the pixel array is formed.

The semiconductor device according to claim 1, wherein an insulating film is formed on the through-connection hole and a side wall of the connection hole.

Forming a first semiconductor wafer including a pixel array in which a photoelectric conversion unit and at least one transfer transistor, a reset transistor, and an amplification transistor are formed;
Forming a second semiconductor wafer comprising a logic circuit on which a signal processing circuit is formed;
Bonding the first semiconductor wafer and the second semiconductor wafer;
Thinning the first semiconductor wafer;
Forming a through-connection hole that penetrates through the first semiconductor wafer and reaches a wiring formed in the second semiconductor wafer;
Embedding a first connection conductor in the through-connection hole;
Forming a connection hole penetrating through the first semiconductor wafer and reaching a wiring formed in the first semiconductor wafer;
Embedding a second connection conductor in the connection hole. A method for manufacturing a semiconductor device.

The method for manufacturing a semiconductor device according to claim 7, further comprising a step of electrically connecting the first connection conductor and the second connection conductor to form an electrode pad exposed to the first semiconductor wafer. .

The method for manufacturing a semiconductor device according to claim 7, wherein the through-connection hole and the connection hole are provided close to each other, and the through-connection hole is formed outside the connection hole.

10. The method according to claim 7, further comprising: forming a third connection conductor that penetrates through the second semiconductor wafer and is exposed on a back surface side of the second semiconductor wafer and is electrically connected to the logic circuit. The manufacturing method of the semiconductor device in any one.

The method of manufacturing a semiconductor device according to claim 7, wherein the through-hole is formed outside a region where the pixel array is formed.

The method for manufacturing a semiconductor device according to claim 7, further comprising a step of forming an insulating film on the through-connection hole and a side wall of the connection hole.

A solid-state imaging device;
An optical system for guiding incident light to the photoelectric conversion unit of the solid-state imaging device;
A signal processing circuit for processing an output signal of the solid-state imaging device,
The solid-state imaging device
A first semiconductor wafer formed into a thin film having a pixel array in which the photoelectric conversion unit, at least one transfer transistor, a reset transistor, and an amplification transistor are formed;
A logic circuit on which a signal processing circuit is formed; a second semiconductor wafer bonded to the first semiconductor wafer;
A through-connection hole formed through the first semiconductor wafer and reaching a wiring formed in the second semiconductor wafer;
A first connection conductor embedded in the through-connection hole;
A connection hole formed through the first semiconductor wafer and reaching the wiring formed in the first semiconductor wafer;
A second connection conductor embedded in the connection hole,
The first connection conductor and the wiring formed on the second semiconductor wafer are connected, and the second connection conductor and the wiring formed on the first semiconductor wafer are connected. An electronic device in which the pixel array and the logic circuit are electrically connected.