JP2014530483A - 非注入障壁領域を含む半導体デバイス及びその製造方法 - Google Patents
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Abstract
Description
本発明は、2011年9月9日に出願された「非注入障壁領域を含む半導体デバイス及びその製造方法」という名称の米国仮特許出願第61/532,762号の利益及び該特許出願に対する優先権を主張するものであり、該特許出願の開示内容はその全体が引用により本明細書に組み入れられる。本発明は、2010年3月8日に出願された「ヘテロ接合障壁領域を含む半導体デバイス及びその製造方法」という名称の米国特許出願第12/719,412号(代理人整理番号5308−1186)の一部継続出願であり、該特許出願の開示内容はその全体が引用により本明細書に組み入れられる。
110 活性領域
114 ドリフト領域
114A 露出部分
115 エッジ終端領域
116 電流サージパッド
130 ヘテロ接合障壁領域
Claims (33)
- n型ドリフト領域を含む炭化ケイ素層と、
前記ドリフト領域との間にショットキー接合部を形成する接点と、
前記炭化ケイ素層上のp型接合障壁領域と、
を含み、前記p型接合障壁領域は、前記ドリフト領域との間にPNヘテロ接合部を形成するp型ポリシリコン領域を含み、前記接点と電気的に接続される、
ことを特徴とする電子デバイス。 - 前記接点と前記ドリフト領域の間の前記ショットキー接合部が、前記接合障壁領域と前記ドリフト領域の間のPNヘテロ接合部よりも低い順電圧でターンオンするように構成される、
ことを特徴とする請求項1に記載の電子デバイス。 - 前記接点が、前記p型ポリシリコン領域へのオ−ム接点を形成し、前記ヘテロ接合障壁領域と前記ドリフト領域の間の前記PNヘテロ接合部が、前記ショットキー接合部のターンオン電圧よりも高い順電圧であって、前記ヘテロ接合障壁領域と前記ドリフト領域の間の前記PNヘテロ接合部が前記ドリフト領域内に少数キャリアを注入し始める低い電圧で多数キャリアを伝導し始めるように構成される、
ことを特徴とする請求項1に記載の電子デバイス。 - 前記接点に横方向に隣接する前記炭化ケイ素層の表面にガードリング終端領域をさらに含み、該ガードリング終端領域が、前記ドリフト領域上の第2のp型ポリシリコン領域を含み、該第2のp型ポリシリコン領域が、ゼロバイアス条件下で前記接点から電気的に絶縁される、
ことを特徴とする請求項1に記載の電子デバイス。 - 前記炭化ケイ素層の前記表面に、前記ドリフト領域の導電型とは逆の導電型を有する接合終端領域をさらに含み、該接合終端領域内に、前記第2のp型ポリシリコン領域が広がる、
ことを特徴とする請求項1に記載の電子デバイス。 - 前記接合障壁領域が、前記ドリフト領域内の複数のp型ポリシリコン領域と、前記接点の下方の前記ドリフト領域内に存在して前記接点に電気的に接続されたp型ポリシリコン少数キャリア注入パッドとを含む、
ことを特徴とする請求項1に記載の電子デバイス。 - 前記少数キャリア注入パッドの、前記炭化ケイ素層の主表面に平行な水平面における表面積が、前記接合障壁領域内の前記複数のp型ポリシリコン領域のうちの1つの水平面における表面積よりも大きい、
ことを特徴とする請求項6に記載の電子デバイス。 - 前記少数キャリア注入パッドの、前記炭化ケイ素層の主表面に平行な水平面における表面積が、前記接点の下方にある前記ドリフト領域の水平面内における表面積の少なくとも約10%である、
ことを特徴とする請求項6に記載の電子デバイス。 - 前記接点とは反対側の前記ドリフト領域上のn+炭化ケイ素接触層と、該接触層上の第2の接点とをさらに含む、
ことを特徴とする請求項1に記載の電子デバイス。 - 第1の導電型を有するドリフト領域と、
前記ドリフト領域との間に金属半導体接合部を形成する接点と、
前記ドリフト領域上の接合障壁領域と、
を含み、前記接合障壁領域が、前記第1の導電型とは逆の第2の導電型を有するとともに、前記ドリフト領域上のヘテロ接合障壁領域を含み、該ヘテロ接合障壁領域が、前記ドリフト領域との間にPNヘテロ接合部を形成し、前記接点と電気的に接触する、
ことを特徴とする電子デバイス。 - 前記接点と前記ドリフト領域の間の前記金属半導体接合部が、前記接合障壁領域と前記ドリフト領域の間のPNヘテロ接合部よりも低い順電圧でターンオンするように構成されたショットキー接合部を含む、
ことを特徴とする請求項10に記載の電子デバイス。 - 前記接点が、前記ヘテロ接合障壁領域へのオ−ム接点を形成し、前記ヘテロ接合障壁領域と前記ドリフト領域の間の前記PNヘテロ接合部が、前記金属半導体接合部のターンオン電圧よりも高い順電圧であって、前記ヘテロ接合障壁領域と前記ドリフト領域の間の前記PNヘテロ接合部が前記ドリフト領域内に少数キャリアを注入し始める低い電圧で多数キャリアを伝導し始めるように構成される、
ことを特徴とする請求項10に記載の電子デバイス。 - 前記ドリフト領域上に存在して前記金属半導体接合部に横方向に隣接するガードリング終端領域をさらに含み、該ガードリング終端領域が、第2のヘテロ接合障壁領域を含む、
ことを特徴とする請求項10に記載の電子デバイス。 - 前記ヘテロ接合障壁領域が、前記ドリフト領域上の複数のp型ポリシリコン領域と、前記接点の下方の前記ドリフト領域上に存在して前記接点に電気的に接続された少なくとも1つのp型ポリシリコン少数キャリア注入パッドとを含む、
ことを特徴とする請求項10に記載の電子デバイス。 - 前記少数キャリア注入パッドの幅が、前記接合障壁領域の幅よりも大きい、
ことを特徴とする請求項14に記載の電子デバイス。 - 前記少数キャリア注入パッドの水平方向の表面積が、前記接合障壁領域内の前記複数のポリシリコン領域のうちの1つの水平方向の表面積よりも大きい、
ことを特徴とする請求項10に記載の電子デバイス。 - 前記ドリフト領域がn型炭化ケイ素を含み、前記ヘテロ接合障壁領域がp型ポリシリコンを含む、
ことを特徴とする請求項10に記載の電子デバイス。 - 前記ドリフト領域がn型炭化ケイ素を含み、前記ヘテロ接合障壁領域がp型窒化ガリウムを含む、
ことを特徴とする請求項10に記載の電子デバイス。 - 前記ドリフト領域の表面に存在して前記デバイスの活性領域を内部に定める終端領域をさらに含み、
前記活性領域の総表面積に対する、前記ヘテロ接合障壁領域が占める前記活性領域の表面積の割合が、約2%〜約40%である、
ことを特徴とする請求項10に記載の電子デバイス。 - 前記活性領域の総表面積に対する、前記ヘテロ接合障壁領域が占める前記活性領域の表面積の割合が、約4%〜約30%である、
ことを特徴とする請求項19に記載の電子デバイス。 - 前記活性領域の総表面積に対する、前記ヘテロ接合障壁領域が占める前記活性領域の表面積の割合が、約10%〜約30%である、
ことを特徴とする請求項19に記載の電子デバイス。 - 前記活性領域の総表面積に対する、前記ヘテロ接合障壁領域が占める前記活性領域の表面積の割合が、約20%〜約30%である、
ことを特徴とする請求項19に記載の電子デバイス。 - 電子デバイスの形成方法であって、
第1の導電型を有するドリフト領域を設けるステップと、
前記ドリフト領域上に、前記ドリフト領域とは異なる材料を含み、前記ドリフト領域の前記導電型とは逆の導電型を有し、前記ドリフト領域との間にPNヘテロ接合部を提供するヘテロ接合障壁領域を設けるステップと、
前記ドリフト領域上及び前記ヘテロ接合障壁領域上に、前記ドリフト領域との間にショットキー接合部を形成し、前記ヘテロ接合障壁領域との間にオ−ム接合部を形成する接点を形成するステップと、
を含むことを特徴とする方法。 - 前記ドリフト領域がn型炭化ケイ素を含み、前記ヘテロ接合障壁領域がp型ポリシリコンを含む、
ことを特徴とする請求項23に記載の方法。 - 前記ドリフト領域上に、前記ショットキー接合部に横方向に隣接するガードリング終端領域を設けるステップをさらに含み、前記ガードリング終端領域が、前記ドリフト領域上の第2のヘテロ接合障壁領域を含むことができる、
ことを特徴とする請求項23に記載の方法。 - 前記ヘテロ接合障壁領域を設けるステップが、前記ドリフト領域内に凹部をエッチングするステップと、前記凹部内にポリシリコン層を堆積させるステップと、前記ポリシリコン層を、前記ドリフト領域の導電型とは逆の導電型を有するようにドープするステップと、前記ポリシリコン層をパターニングするステップとを含む、
ことを特徴とする請求項23に記載の方法。 - 第1の導電型を有するドリフト領域を含む炭化ケイ素層と、
前記ドリフト領域の表面上に存在して、前記ドリフト領域との間にショットキー接合部を形成する接点と、
前記ショットキー接合部に隣接する前記炭化ケイ素層の前記表面に接するガードリングと、
を含み、前記ガードリングが、前記ドリフト領域の導電型とは逆の導電型を有するとともに、前記炭化ケイ素層との間にヘテロ接合部を形成する材料を含み、
前記ガードリングが、ポリシリコン及び/又は窒化ガリウムを含む、
ことを特徴とする電子デバイス。 - 第1の導電型を有するドリフト領域と、
前記ドリフト領域との間に金属半導体接合部を形成する接点と、
前記ドリフト領域上に存在して前記接合部に横方向に隣接する、前記第1の導電型とは逆の第2の導電型を有するガードリングと、
を含み、
前記ガードリングが、前記ドリフト領域との間にPNヘテロ接合部を形成する金属を含む、
ことを特徴とする電子デバイス。 - 前記ガードリングが、ドープされたポリシリコンを含む、
ことを特徴とする請求項28に記載の電子デバイス。 - 前記ドリフト領域上の前記第2の導電型を有する接合障壁領域をさらに含み、
前記接合障壁領域は、前記ドリフト領域上のヘテロ接合障壁領域を含み、
前記ヘテロ接合障壁領域は、前記ドリフト領域との間にPNヘテロ接合部を形成し、前記接点と電気的に接触する、
ことを特徴とする請求項28に記載の電子デバイス。 - 前記接点と前記ドリフト領域の間の前記金属半導体接合部が、前記接合障壁領域と前記ドリフト領域の間のPNヘテロ接合部よりも低い順電圧でターンオンするように構成されたショットキー接合部を含む、
ことを特徴とする請求項30に記載の電子デバイス。 - 前記接点が、前記ヘテロ接合障壁領域へのオ−ム接点を形成し、前記ヘテロ接合障壁領域と前記ドリフト領域の間の前記PNヘテロ接合部が、前記金属半導体接合部のターンオン電圧よりも高い順電圧であって、前記ヘテロ接合障壁領域と前記ドリフト領域の間の前記PNヘテロ接合部が前記ドリフト領域内に少数キャリアを注入し始める低い電圧で多数キャリアを伝導し始めるように構成される、
ことを特徴とする請求項30に記載の電子デバイス。 - 前記ヘテロ接合障壁領域が、前記ドリフト領域上の複数のp型ポリシリコン領域と、前記接点の下方の前記ドリフト領域上に存在して前記接点に電気的に接続された少なくとも1つのp型ポリシリコン少数キャリア注入パッドとを含む、
ことを特徴とする請求項30に記載の電子デバイス。
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