JP2014526807A - はんだ接合部におけるボイド抑制のためのシステムおよび方法 - Google Patents
はんだ接合部におけるボイド抑制のためのシステムおよび方法 Download PDFInfo
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- H—ELECTRICITY
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H05K3/3457—Solder materials or compositions; Methods of application thereof
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16113—Disposition the whole bump connector protruding from the surface
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/1624—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/818—Bonding techniques
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- H01L2224/92—Specific sequence of method steps
- H01L2224/9201—Forming connectors during the connecting process, e.g. in-situ formation of bumps
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- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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Abstract
Description
30mm2のサーマルパッドを有し、0.05から0.10mmの基板からの離隔支持体および2または4mmのプリフォームを備える部品で実験を行った。典型的な厚さである約0.062インチのFR4ガラスエポキシ印刷回路基板を用いた。基板の仕上げは、有機表面保護剤(OSP)であった。はんだペーストは、SAC3054タイプ4粉末を用いた。円盤状プリフォームは、直径4mm、厚さ0.1mm、および直径2mm、厚さ0.1mmの寸法のSAC305合金であった。リフロープロファイルは、当産業で用いられるものの典型である直線ランプ(温度対時間)およびソークプロファイルの両方を用いた。印刷されたペーストパターンは、プリフォームなし100%被覆率(対照群)と、パッド面積の50%から20%未満まで下がる被覆率を有する、印刷されたはんだペーストの様々な窓枠パターンとを含めた。50%被覆率に対応して、はんだ接合部容量の45%となった小さいプリフォームを用いた。20%未満の被覆率に対応して、大きいプリフォームを用いた。これは、はんだ接合部にたいしてかなり高いパーセンテージ(80%よりも大きい)となった。
1つまたは2つ以上の実施形態によるボイド抑制プリフォームを図5に示されるように形成した。暗色の領域は、印刷されたはんだペーストを表し、他方、白色の領域は、フラックスで覆われたはんだプリフォームを表す。これらのフラックスで覆われたプリフォームは、試験中、再現可能な結果をもたらした。
Claims (23)
- はんだ接合部においてボイド形成を抑制する方法であって、
はんだペースト堆積物を基板に塗布することと、
はんだプリフォームを前記はんだペースト堆積物に載置することと、
素子を前記はんだプリフォームおよび前記はんだペースト堆積物の上に配置することと、
前記はんだ接合部を前記素子と前記基板との間に形成するように前記はんだペースト堆積物および前記はんだプリフォームを処理することと
を備える、はんだ接合部においてボイド形成を抑制する方法。 - 前記基板が印刷回路基板であり、前記素子が集積回路パッケージである、請求項1に記載の方法。
- 前記処理するステップが、前記はんだペースト堆積物および前記はんだプリフォームを約140℃から約275℃までの温度に加熱することを備える、請求項1に記載の方法。
- 複数のプリフォームを前記はんだペースト堆積物にさらに備える、請求項1に記載の方法。
- 前記はんだペースト堆積物が、前記はんだプリフォームの厚さよりも厚いか等しい厚さに塗布される、請求項1に記載の方法。
- 前記はんだペースト堆積物を前記基板に塗布することが、前記はんだペーストを所定のパターンで前記基板上に印刷することを備える、請求項1に記載の方法。
- 前記はんだプリフォームの直径が、約1mmから約15mmの間である、請求項1に記載の方法。
- 前記はんだプリフォームの厚さが、約0.025mmから約0.2mmの間である、請求項1に記載の方法。
- 前記はんだプリフォームが、少なくとも約99.9重量%の純金属または純金属からなる合金を備える、請求項1に記載の方法。
- 前記純金属または前記純金属からなる合金が、スズ、銀、アンチモン、銅、鉛、ニッケル、インジウム、パラジウム、ガリウム、カドミウム、およびビスマスのうちの少なくとも1つを備える、請求項9に記載の方法。
- 前記はんだプリフォームが、実質的にフラックスを含まない、請求項1に記載の方法。
- 前記はんだ接合部が、ボイド空間の面積が約40%未満であることを特徴とする、請求項1に記載の方法。
- 前記はんだプリフォームが、処理後の容量で前記はんだ接合部の約25容量%から約95容量%に寄与する、請求項12に記載の方法。
- アセンブリであって、
印刷回路基板と、
前記印刷回路基板に結合される素子と、
前記印刷回路基板と前記素子との間にはんだ接合部とを備え、
前記はんだ接合部の約25容量%から約95容量%が、処理後、はんだプリフォームを包含する、アセンブリ。 - 前記はんだ接合部が、スズ、銀、アンチモン、銅、鉛、ニッケル、インジウム、パラジウム、ガリウム、カドミウム、およびビスマスのうちの少なくとも1つを備える、請求項14に記載のアセンブリ。
- 前記はんだ接合部が、ボイド空間の面積が約40%未満であることを特徴とする、請求項14に記載のアセンブリ。
- 素子を印刷回路基板に組み立てるためのキットであって、
はんだペーストと、
約1mmから約15mmの直径および約0.025mmから0.2mmの厚さを有する少なくとも1つのはんだプリフォームと
を備え、
前記少なくとも1つのはんだプリフォームが、少なくとも約99.9重量%の純金属または純金属からなる合金を備える、
素子を印刷回路基板に組み立てるためのキット。 - 前記少なくとも1つのはんだプリフォームが、テープアンドリールパッケージの上に配置される、請求項17に記載のキット。
- 前記少なくとも1つのはんだプリフォームが、ピックアンドプレース処理のためのトレイの上に配置される、請求項17に記載のキット。
- 前記少なくとも1つのはんだプリフォームが、自動機械加工可能な実装において実装される、請求項17に記載のキット。
- はんだ接合部におけるボイド抑制を促進する方法であって、
はんだプリフォームを提供することと、
前記はんだプリフォームを処理前に印刷回路基板の上のはんだペースト堆積物に塗布して、前記はんだ接合部を形成する命令を提供することと
を備える、はんだ接合部におけるボイド抑制を促進する方法。 - はんだペーストを提供することをさらに備える、請求項19に記載の方法。
- 印刷回路基板と集積回路パッケージとの間のはんだ接合部であって、
前記はんだ接合部が、ボイド空間の面積が約40%未満であることを特徴とし、
前記はんだ接合部の約25容量%から約95容量%が、処理後、はんだプリフォームを包含する、印刷回路基板と集積回路パッケージとの間のはんだ接合部。
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US201161539260P | 2011-09-26 | 2011-09-26 | |
US61/539,260 | 2011-09-26 | ||
PCT/US2012/057116 WO2013049061A1 (en) | 2011-09-26 | 2012-09-25 | Systems and methods for void reduction in a solder joint |
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JP2014526807A true JP2014526807A (ja) | 2014-10-06 |
JP2014526807A5 JP2014526807A5 (ja) | 2015-11-12 |
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EP (1) | EP2761979A4 (ja) |
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CN (1) | CN104025727B (ja) |
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CA (1) | CA2849459A1 (ja) |
HK (1) | HK1201668A1 (ja) |
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US10537030B2 (en) * | 2014-08-25 | 2020-01-14 | Indium Corporation | Voiding control using solid solder preforms embedded in solder paste |
FR3094172B1 (fr) | 2019-03-19 | 2022-04-22 | St Microelectronics Grenoble 2 | Dispositif électronique comprenant un composant électronique monté sur un substrat de support et procédé de montage |
DE102020129830A1 (de) | 2020-11-12 | 2022-05-12 | Endress+Hauser SE+Co. KG | Verfahren zum Auflöten mindestens eines ersten Bauelements auf eine Oberfläche einer ersten Leiterplatte |
DE102020129831A1 (de) | 2020-11-12 | 2022-05-12 | Endress+Hauser SE+Co. KG | Verfahren zum Auflöten eines Bauelements auf eine Oberfläche einer ersten Leiterplatte |
KR102594797B1 (ko) * | 2021-06-15 | 2023-10-27 | 박정재 | Pcb에 실장되는 반도체소자를 위한 방열장치 |
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---|---|---|---|---|
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- 2012-09-25 MX MX2014003639A patent/MX340340B/es active IP Right Grant
- 2012-09-25 JP JP2014532095A patent/JP6203731B2/ja active Active
- 2012-09-25 MY MYPI2014000885A patent/MY185277A/en unknown
- 2012-09-25 BR BR112014007196A patent/BR112014007196A2/pt not_active Application Discontinuation
- 2012-09-25 CN CN201280048839.1A patent/CN104025727B/zh active Active
- 2012-09-25 WO PCT/US2012/057116 patent/WO2013049061A1/en active Application Filing
- 2012-09-25 EP EP12837297.6A patent/EP2761979A4/en not_active Withdrawn
- 2012-09-25 CA CA2849459A patent/CA2849459A1/en not_active Abandoned
- 2012-09-25 KR KR1020147008801A patent/KR20140079391A/ko not_active Application Discontinuation
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Also Published As
Publication number | Publication date |
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BR112014007196A2 (pt) | 2017-04-04 |
CA2849459A1 (en) | 2013-04-04 |
KR20140079391A (ko) | 2014-06-26 |
HK1201668A1 (en) | 2015-09-04 |
WO2013049061A9 (en) | 2014-05-08 |
EP2761979A4 (en) | 2015-08-05 |
MX2014003639A (es) | 2015-05-15 |
WO2013049061A1 (en) | 2013-04-04 |
EP2761979A1 (en) | 2014-08-06 |
IN2014DN03157A (ja) | 2015-05-22 |
JP6203731B2 (ja) | 2017-09-27 |
CN104025727B (zh) | 2017-08-29 |
CN104025727A (zh) | 2014-09-03 |
MY185277A (en) | 2021-04-30 |
US20140328039A1 (en) | 2014-11-06 |
MX340340B (es) | 2016-07-05 |
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